* [PATCH] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
@ 2021-06-30 18:39 H.J. Lu
2021-07-01 16:27 ` Florian Weimer
0 siblings, 1 reply; 7+ messages in thread
From: H.J. Lu @ 2021-06-30 18:39 UTC (permalink / raw)
To: libc-alpha
From
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated,
which is set to indicate to updated software that the loaded microcode is
forcing RTM abort.
1. Add RTM_ALWAYS_ABORT to CPUID features.
2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.
3. Check RTM feature, instead of usability, against /proc/cpuinfo.
This fixes BZ #28033.
---
manual/platform.texi | 3 +++
sysdeps/x86/bits/platform/x86.h | 2 +-
sysdeps/x86/cpu-features.c | 4 +++-
sysdeps/x86/include/cpu-features.h | 6 +++---
sysdeps/x86/tst-cpu-features-supports.c | 2 +-
sysdeps/x86/tst-get-cpu-features.c | 1 +
6 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/manual/platform.texi b/manual/platform.texi
index 4cd029cfad..8ec7f385e9 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -525,6 +525,9 @@ capability.
@item
@code{RTM} -- RTM instruction extensions.
+@item
+@code{RTM_ALWAYS_ABORT} -- Abort all transactions.
+
@item
@code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug.
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 26e3b67ede..5509b1ad87 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -211,7 +211,7 @@ enum
x86_cpu_AVX512_VP2INTERSECT = x86_cpu_index_7_edx + 8,
x86_cpu_INDEX_7_EDX_9 = x86_cpu_index_7_edx + 9,
x86_cpu_MD_CLEAR = x86_cpu_index_7_edx + 10,
- x86_cpu_INDEX_7_EDX_11 = x86_cpu_index_7_edx + 11,
+ x86_cpu_RTM_ALWAYS_ABORT = x86_cpu_index_7_edx + 11,
x86_cpu_INDEX_7_EDX_12 = x86_cpu_index_7_edx + 12,
x86_cpu_INDEX_7_EDX_13 = x86_cpu_index_7_edx + 13,
x86_cpu_SERIALIZE = x86_cpu_index_7_edx + 14,
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index a1d8d11cc4..d9093f11ac 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -67,7 +67,6 @@ update_usable (struct cpu_features *cpu_features)
CPU_FEATURE_SET_USABLE (cpu_features, HLE);
CPU_FEATURE_SET_USABLE (cpu_features, BMI2);
CPU_FEATURE_SET_USABLE (cpu_features, ERMS);
- CPU_FEATURE_SET_USABLE (cpu_features, RTM);
CPU_FEATURE_SET_USABLE (cpu_features, RDSEED);
CPU_FEATURE_SET_USABLE (cpu_features, ADX);
CPU_FEATURE_SET_USABLE (cpu_features, CLFLUSHOPT);
@@ -97,6 +96,9 @@ update_usable (struct cpu_features *cpu_features)
CPU_FEATURE_SET_USABLE (cpu_features, FSRCS);
CPU_FEATURE_SET_USABLE (cpu_features, PTWRITE);
+ if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT))
+ CPU_FEATURE_SET_USABLE (cpu_features, RTM);
+
#if CET_ENABLED
CPU_FEATURE_SET_USABLE (cpu_features, IBT);
CPU_FEATURE_SET_USABLE (cpu_features, SHSTK);
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
index 4f1c4ee402..59e01df543 100644
--- a/sysdeps/x86/include/cpu-features.h
+++ b/sysdeps/x86/include/cpu-features.h
@@ -229,7 +229,7 @@ enum
#define bit_cpu_AVX512_VP2INTERSECT (1u << 8)
#define bit_cpu_INDEX_7_EDX_9 (1u << 9)
#define bit_cpu_MD_CLEAR (1u << 10)
-#define bit_cpu_INDEX_7_EDX_11 (1u << 11)
+#define bit_cpu_RTM_ALWAYS_ABORT (1u << 11)
#define bit_cpu_INDEX_7_EDX_12 (1u << 12)
#define bit_cpu_INDEX_7_EDX_13 (1u << 13)
#define bit_cpu_SERIALIZE (1u << 14)
@@ -463,7 +463,7 @@ enum
#define index_cpu_AVX512_VP2INTERSECT CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_9 CPUID_INDEX_7
#define index_cpu_MD_CLEAR CPUID_INDEX_7
-#define index_cpu_INDEX_7_EDX_11 CPUID_INDEX_7
+#define index_cpu_RTM_ALWAYS_ABORT CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_12 CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_13 CPUID_INDEX_7
#define index_cpu_SERIALIZE CPUID_INDEX_7
@@ -697,7 +697,7 @@ enum
#define reg_AVX512_VP2INTERSECT edx
#define reg_INDEX_7_EDX_9 edx
#define reg_MD_CLEAR edx
-#define reg_INDEX_7_EDX_11 edx
+#define reg_RTM_ALWAYS_ABORT edx
#define reg_INDEX_7_EDX_12 edx
#define reg_INDEX_7_EDX_13 edx
#define reg_SERIALIZE edx
diff --git a/sysdeps/x86/tst-cpu-features-supports.c b/sysdeps/x86/tst-cpu-features-supports.c
index a2cabc90be..867ea6b8e8 100644
--- a/sysdeps/x86/tst-cpu-features-supports.c
+++ b/sysdeps/x86/tst-cpu-features-supports.c
@@ -153,7 +153,7 @@ do_test (int argc, char **argv)
fails += CHECK_SUPPORTS (rdpid, RDPID);
fails += CHECK_SUPPORTS (rdrnd, RDRAND);
fails += CHECK_SUPPORTS (rdseed, RDSEED);
- fails += CHECK_SUPPORTS (rtm, RTM);
+ fails += CHECK_CPU_SUPPORTS (rtm, RTM);
fails += CHECK_SUPPORTS (serialize, SERIALIZE);
fails += CHECK_SUPPORTS (sha, SHA);
fails += CHECK_CPU_SUPPORTS (shstk, SHSTK);
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 583e1e6d49..cda78497cf 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -158,6 +158,7 @@ do_test (void)
CHECK_CPU_FEATURE (UINTR);
CHECK_CPU_FEATURE (AVX512_VP2INTERSECT);
CHECK_CPU_FEATURE (MD_CLEAR);
+ CHECK_CPU_FEATURE (RTM_ALWAYS_ABORT);
CHECK_CPU_FEATURE (SERIALIZE);
CHECK_CPU_FEATURE (HYBRID);
CHECK_CPU_FEATURE (TSXLDTRK);
--
2.31.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
2021-06-30 18:39 [PATCH] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033] H.J. Lu
@ 2021-07-01 16:27 ` Florian Weimer
2021-07-01 17:11 ` [PATCH v2] " H.J. Lu
0 siblings, 1 reply; 7+ messages in thread
From: Florian Weimer @ 2021-07-01 16:27 UTC (permalink / raw)
To: H.J. Lu via Libc-alpha
* H. J. Lu via Libc-alpha:
> From
>
> https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
>
> A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated,
> which is set to indicate to updated software that the loaded microcode is
> forcing RTM abort.
>
> 1. Add RTM_ALWAYS_ABORT to CPUID features.
> 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.
> 3. Check RTM feature, instead of usability, against /proc/cpuinfo.
Maybe not that this fixes the string/tst-memchr-rtm etc. test cases
after a microcde update?
> diff --git a/manual/platform.texi b/manual/platform.texi
> index 4cd029cfad..8ec7f385e9 100644
> --- a/manual/platform.texi
> +++ b/manual/platform.texi
> @@ -525,6 +525,9 @@ capability.
> @item
> @code{RTM} -- RTM instruction extensions.
>
> +@item
> +@code{RTM_ALWAYS_ABORT} -- Abort all transactions.
I think this means “Transactions always abort, making RTM unusable.”
(with unusable in both senses, !CPU_FEATURE_USABLE, and not useful).
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index a1d8d11cc4..d9093f11ac 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -67,7 +67,6 @@ update_usable (struct cpu_features *cpu_features)
> CPU_FEATURE_SET_USABLE (cpu_features, HLE);
> CPU_FEATURE_SET_USABLE (cpu_features, BMI2);
> CPU_FEATURE_SET_USABLE (cpu_features, ERMS);
> - CPU_FEATURE_SET_USABLE (cpu_features, RTM);
> CPU_FEATURE_SET_USABLE (cpu_features, RDSEED);
> CPU_FEATURE_SET_USABLE (cpu_features, ADX);
> CPU_FEATURE_SET_USABLE (cpu_features, CLFLUSHOPT);
> @@ -97,6 +96,9 @@ update_usable (struct cpu_features *cpu_features)
> CPU_FEATURE_SET_USABLE (cpu_features, FSRCS);
> CPU_FEATURE_SET_USABLE (cpu_features, PTWRITE);
>
> + if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT))
> + CPU_FEATURE_SET_USABLE (cpu_features, RTM);
> +
> #if CET_ENABLED
> CPU_FEATURE_SET_USABLE (cpu_features, IBT);
> CPU_FEATURE_SET_USABLE (cpu_features, SHSTK);
Is some change necessary to copy RTM_ALWAYS_ABORT to USABLE as well?
Any idea why the microcode update doesn't just clear the RPM bit in
CPUID? This is a bit awkward.
Thanks,
Florian
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
2021-07-01 16:27 ` Florian Weimer
@ 2021-07-01 17:11 ` H.J. Lu
2021-07-01 17:24 ` Florian Weimer
2021-07-01 19:22 ` H.J. Lu
0 siblings, 2 replies; 7+ messages in thread
From: H.J. Lu @ 2021-07-01 17:11 UTC (permalink / raw)
To: Florian Weimer; +Cc: H.J. Lu via Libc-alpha
[-- Attachment #1: Type: text/plain, Size: 2898 bytes --]
On Thu, Jul 1, 2021 at 9:27 AM Florian Weimer <fweimer@redhat.com> wrote:
>
> * H. J. Lu via Libc-alpha:
>
> > From
> >
> > https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
> >
> > A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated,
> > which is set to indicate to updated software that the loaded microcode is
> > forcing RTM abort.
> >
> > 1. Add RTM_ALWAYS_ABORT to CPUID features.
> > 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.
> > 3. Check RTM feature, instead of usability, against /proc/cpuinfo.
>
> Maybe not that this fixes the string/tst-memchr-rtm etc. test cases
> after a microcde update?
I changed it to
1. Add RTM_ALWAYS_ABORT to CPUID features.
2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the
string/tst-memchr-rtm etc. testcases on the affected processors, which
always fail after a microcde update.
3. Check RTM feature, instead of usability, against /proc/cpuinfo.
> > diff --git a/manual/platform.texi b/manual/platform.texi
> > index 4cd029cfad..8ec7f385e9 100644
> > --- a/manual/platform.texi
> > +++ b/manual/platform.texi
> > @@ -525,6 +525,9 @@ capability.
> > @item
> > @code{RTM} -- RTM instruction extensions.
> >
> > +@item
> > +@code{RTM_ALWAYS_ABORT} -- Abort all transactions.
>
> I think this means “Transactions always abort, making RTM unusable.”
> (with unusable in both senses, !CPU_FEATURE_USABLE, and not useful).
Fixed.
> > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> > index a1d8d11cc4..d9093f11ac 100644
> > --- a/sysdeps/x86/cpu-features.c
> > +++ b/sysdeps/x86/cpu-features.c
> > @@ -67,7 +67,6 @@ update_usable (struct cpu_features *cpu_features)
> > CPU_FEATURE_SET_USABLE (cpu_features, HLE);
> > CPU_FEATURE_SET_USABLE (cpu_features, BMI2);
> > CPU_FEATURE_SET_USABLE (cpu_features, ERMS);
> > - CPU_FEATURE_SET_USABLE (cpu_features, RTM);
> > CPU_FEATURE_SET_USABLE (cpu_features, RDSEED);
> > CPU_FEATURE_SET_USABLE (cpu_features, ADX);
> > CPU_FEATURE_SET_USABLE (cpu_features, CLFLUSHOPT);
> > @@ -97,6 +96,9 @@ update_usable (struct cpu_features *cpu_features)
> > CPU_FEATURE_SET_USABLE (cpu_features, FSRCS);
> > CPU_FEATURE_SET_USABLE (cpu_features, PTWRITE);
> >
> > + if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT))
> > + CPU_FEATURE_SET_USABLE (cpu_features, RTM);
> > +
> > #if CET_ENABLED
> > CPU_FEATURE_SET_USABLE (cpu_features, IBT);
> > CPU_FEATURE_SET_USABLE (cpu_features, SHSTK);
>
> Is some change necessary to copy RTM_ALWAYS_ABORT to USABLE as well?
Added.
> Any idea why the microcode update doesn't just clear the RPM bit in
> CPUID? This is a bit awkward.
I asked it internally.
> Thanks,
> Florian
>
Here is the v2 patch. OK for master?
Thanks.
--
H.J.
[-- Attachment #2: v2-0001-x86-Check-RTM_ALWAYS_ABORT-for-RTM-BZ-28033.patch --]
[-- Type: text/x-patch, Size: 6950 bytes --]
From 233a9d8ca75b56e35f6dc4ccd64f72872edf9d95 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Wed, 30 Jun 2021 10:47:06 -0700
Subject: [PATCH v2] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
From
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
* Intel TSX will be disabled by default.
* The processor will force abort all Restricted Transactional Memory (RTM)
transactions by default.
* A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated,
which is set to indicate to updated software that the loaded microcode is
forcing RTM abort.
* On processors that enumerate support for RTM, the CPUID enumeration bits
for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to
be set by default after microcode update.
* Workloads that were benefited from Intel TSX might experience a change
in performance.
* System software may use a new bit in Model-Specific Register (MSR) 0x10F
TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock
Elision (HLE) and RTM bits to indicate to software that Intel TSX is
disabled.
1. Add RTM_ALWAYS_ABORT to CPUID features.
2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the
string/tst-memchr-rtm etc. testcases on the affected processors, which
always fail after a microcde update.
3. Check RTM feature, instead of usability, against /proc/cpuinfo.
This fixes BZ #28033.
---
manual/platform.texi | 3 +++
sysdeps/x86/bits/platform/x86.h | 2 +-
sysdeps/x86/cpu-features.c | 5 ++++-
sysdeps/x86/include/cpu-features.h | 6 +++---
sysdeps/x86/tst-cpu-features-supports.c | 2 +-
sysdeps/x86/tst-get-cpu-features.c | 2 ++
6 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/manual/platform.texi b/manual/platform.texi
index 4cd029cfad..037dfc4f20 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -525,6 +525,9 @@ capability.
@item
@code{RTM} -- RTM instruction extensions.
+@item
+@code{RTM_ALWAYS_ABORT} -- Transactions always abort, making RTM unusable.
+
@item
@code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug.
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 26e3b67ede..5509b1ad87 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -211,7 +211,7 @@ enum
x86_cpu_AVX512_VP2INTERSECT = x86_cpu_index_7_edx + 8,
x86_cpu_INDEX_7_EDX_9 = x86_cpu_index_7_edx + 9,
x86_cpu_MD_CLEAR = x86_cpu_index_7_edx + 10,
- x86_cpu_INDEX_7_EDX_11 = x86_cpu_index_7_edx + 11,
+ x86_cpu_RTM_ALWAYS_ABORT = x86_cpu_index_7_edx + 11,
x86_cpu_INDEX_7_EDX_12 = x86_cpu_index_7_edx + 12,
x86_cpu_INDEX_7_EDX_13 = x86_cpu_index_7_edx + 13,
x86_cpu_SERIALIZE = x86_cpu_index_7_edx + 14,
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index a1d8d11cc4..563a206ac1 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -67,7 +67,6 @@ update_usable (struct cpu_features *cpu_features)
CPU_FEATURE_SET_USABLE (cpu_features, HLE);
CPU_FEATURE_SET_USABLE (cpu_features, BMI2);
CPU_FEATURE_SET_USABLE (cpu_features, ERMS);
- CPU_FEATURE_SET_USABLE (cpu_features, RTM);
CPU_FEATURE_SET_USABLE (cpu_features, RDSEED);
CPU_FEATURE_SET_USABLE (cpu_features, ADX);
CPU_FEATURE_SET_USABLE (cpu_features, CLFLUSHOPT);
@@ -83,6 +82,7 @@ update_usable (struct cpu_features *cpu_features)
CPU_FEATURE_SET_USABLE (cpu_features, MOVDIRI);
CPU_FEATURE_SET_USABLE (cpu_features, MOVDIR64B);
CPU_FEATURE_SET_USABLE (cpu_features, FSRM);
+ CPU_FEATURE_SET_USABLE (cpu_features, RTM_ALWAYS_ABORT);
CPU_FEATURE_SET_USABLE (cpu_features, SERIALIZE);
CPU_FEATURE_SET_USABLE (cpu_features, TSXLDTRK);
CPU_FEATURE_SET_USABLE (cpu_features, LAHF64_SAHF64);
@@ -97,6 +97,9 @@ update_usable (struct cpu_features *cpu_features)
CPU_FEATURE_SET_USABLE (cpu_features, FSRCS);
CPU_FEATURE_SET_USABLE (cpu_features, PTWRITE);
+ if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT))
+ CPU_FEATURE_SET_USABLE (cpu_features, RTM);
+
#if CET_ENABLED
CPU_FEATURE_SET_USABLE (cpu_features, IBT);
CPU_FEATURE_SET_USABLE (cpu_features, SHSTK);
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h
index 4f1c4ee402..59e01df543 100644
--- a/sysdeps/x86/include/cpu-features.h
+++ b/sysdeps/x86/include/cpu-features.h
@@ -229,7 +229,7 @@ enum
#define bit_cpu_AVX512_VP2INTERSECT (1u << 8)
#define bit_cpu_INDEX_7_EDX_9 (1u << 9)
#define bit_cpu_MD_CLEAR (1u << 10)
-#define bit_cpu_INDEX_7_EDX_11 (1u << 11)
+#define bit_cpu_RTM_ALWAYS_ABORT (1u << 11)
#define bit_cpu_INDEX_7_EDX_12 (1u << 12)
#define bit_cpu_INDEX_7_EDX_13 (1u << 13)
#define bit_cpu_SERIALIZE (1u << 14)
@@ -463,7 +463,7 @@ enum
#define index_cpu_AVX512_VP2INTERSECT CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_9 CPUID_INDEX_7
#define index_cpu_MD_CLEAR CPUID_INDEX_7
-#define index_cpu_INDEX_7_EDX_11 CPUID_INDEX_7
+#define index_cpu_RTM_ALWAYS_ABORT CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_12 CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_13 CPUID_INDEX_7
#define index_cpu_SERIALIZE CPUID_INDEX_7
@@ -697,7 +697,7 @@ enum
#define reg_AVX512_VP2INTERSECT edx
#define reg_INDEX_7_EDX_9 edx
#define reg_MD_CLEAR edx
-#define reg_INDEX_7_EDX_11 edx
+#define reg_RTM_ALWAYS_ABORT edx
#define reg_INDEX_7_EDX_12 edx
#define reg_INDEX_7_EDX_13 edx
#define reg_SERIALIZE edx
diff --git a/sysdeps/x86/tst-cpu-features-supports.c b/sysdeps/x86/tst-cpu-features-supports.c
index a2cabc90be..867ea6b8e8 100644
--- a/sysdeps/x86/tst-cpu-features-supports.c
+++ b/sysdeps/x86/tst-cpu-features-supports.c
@@ -153,7 +153,7 @@ do_test (int argc, char **argv)
fails += CHECK_SUPPORTS (rdpid, RDPID);
fails += CHECK_SUPPORTS (rdrnd, RDRAND);
fails += CHECK_SUPPORTS (rdseed, RDSEED);
- fails += CHECK_SUPPORTS (rtm, RTM);
+ fails += CHECK_CPU_SUPPORTS (rtm, RTM);
fails += CHECK_SUPPORTS (serialize, SERIALIZE);
fails += CHECK_SUPPORTS (sha, SHA);
fails += CHECK_CPU_SUPPORTS (shstk, SHSTK);
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 583e1e6d49..11fa3054b9 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -158,6 +158,7 @@ do_test (void)
CHECK_CPU_FEATURE (UINTR);
CHECK_CPU_FEATURE (AVX512_VP2INTERSECT);
CHECK_CPU_FEATURE (MD_CLEAR);
+ CHECK_CPU_FEATURE (RTM_ALWAYS_ABORT);
CHECK_CPU_FEATURE (SERIALIZE);
CHECK_CPU_FEATURE (HYBRID);
CHECK_CPU_FEATURE (TSXLDTRK);
@@ -322,6 +323,7 @@ do_test (void)
CHECK_CPU_FEATURE_USABLE (FSRM);
CHECK_CPU_FEATURE_USABLE (AVX512_VP2INTERSECT);
CHECK_CPU_FEATURE_USABLE (MD_CLEAR);
+ CHECK_CPU_FEATURE_USABLE (RTM_ALWAYS_ABORT);
CHECK_CPU_FEATURE_USABLE (SERIALIZE);
CHECK_CPU_FEATURE_USABLE (HYBRID);
CHECK_CPU_FEATURE_USABLE (TSXLDTRK);
--
2.31.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
2021-07-01 17:11 ` [PATCH v2] " H.J. Lu
@ 2021-07-01 17:24 ` Florian Weimer
2021-07-01 19:22 ` H.J. Lu
1 sibling, 0 replies; 7+ messages in thread
From: Florian Weimer @ 2021-07-01 17:24 UTC (permalink / raw)
To: H.J. Lu; +Cc: H.J. Lu via Libc-alpha
* H. J. Lu:
> Here is the v2 patch. OK for master?
Yes, looks okay to me. Thanks.
Florian
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
2021-07-01 17:11 ` [PATCH v2] " H.J. Lu
2021-07-01 17:24 ` Florian Weimer
@ 2021-07-01 19:22 ` H.J. Lu
2021-07-02 8:40 ` Florian Weimer
1 sibling, 1 reply; 7+ messages in thread
From: H.J. Lu @ 2021-07-01 19:22 UTC (permalink / raw)
To: Florian Weimer; +Cc: H.J. Lu via Libc-alpha
On Thu, Jul 1, 2021 at 10:11 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Thu, Jul 1, 2021 at 9:27 AM Florian Weimer <fweimer@redhat.com> wrote:
> >
> > * H. J. Lu via Libc-alpha:
> >
> > > From
> > >
> > > https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
> > >
> > > A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated,
> > > which is set to indicate to updated software that the loaded microcode is
> > > forcing RTM abort.
> > >
> > > 1. Add RTM_ALWAYS_ABORT to CPUID features.
> > > 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.
> > > 3. Check RTM feature, instead of usability, against /proc/cpuinfo.
> >
> > Maybe not that this fixes the string/tst-memchr-rtm etc. test cases
> > after a microcde update?
>
> I changed it to
>
> 1. Add RTM_ALWAYS_ABORT to CPUID features.
> 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the
> string/tst-memchr-rtm etc. testcases on the affected processors, which
> always fail after a microcde update.
> 3. Check RTM feature, instead of usability, against /proc/cpuinfo.
>
> > > diff --git a/manual/platform.texi b/manual/platform.texi
> > > index 4cd029cfad..8ec7f385e9 100644
> > > --- a/manual/platform.texi
> > > +++ b/manual/platform.texi
> > > @@ -525,6 +525,9 @@ capability.
> > > @item
> > > @code{RTM} -- RTM instruction extensions.
> > >
> > > +@item
> > > +@code{RTM_ALWAYS_ABORT} -- Abort all transactions.
> >
> > I think this means “Transactions always abort, making RTM unusable.”
> > (with unusable in both senses, !CPU_FEATURE_USABLE, and not useful).
>
> Fixed.
>
> > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> > > index a1d8d11cc4..d9093f11ac 100644
> > > --- a/sysdeps/x86/cpu-features.c
> > > +++ b/sysdeps/x86/cpu-features.c
> > > @@ -67,7 +67,6 @@ update_usable (struct cpu_features *cpu_features)
> > > CPU_FEATURE_SET_USABLE (cpu_features, HLE);
> > > CPU_FEATURE_SET_USABLE (cpu_features, BMI2);
> > > CPU_FEATURE_SET_USABLE (cpu_features, ERMS);
> > > - CPU_FEATURE_SET_USABLE (cpu_features, RTM);
> > > CPU_FEATURE_SET_USABLE (cpu_features, RDSEED);
> > > CPU_FEATURE_SET_USABLE (cpu_features, ADX);
> > > CPU_FEATURE_SET_USABLE (cpu_features, CLFLUSHOPT);
> > > @@ -97,6 +96,9 @@ update_usable (struct cpu_features *cpu_features)
> > > CPU_FEATURE_SET_USABLE (cpu_features, FSRCS);
> > > CPU_FEATURE_SET_USABLE (cpu_features, PTWRITE);
> > >
> > > + if (!CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT))
> > > + CPU_FEATURE_SET_USABLE (cpu_features, RTM);
> > > +
> > > #if CET_ENABLED
> > > CPU_FEATURE_SET_USABLE (cpu_features, IBT);
> > > CPU_FEATURE_SET_USABLE (cpu_features, SHSTK);
> >
> > Is some change necessary to copy RTM_ALWAYS_ABORT to USABLE as well?
>
> Added.
>
> > Any idea why the microcode update doesn't just clear the RPM bit in
> > CPUID? This is a bit awkward.
>
> I asked it internally.
Here it is
---
VMM vendors told us that clearing CPUID bits during ucode load is an absolute
no-go and caused a lot of SW instability in the past (also related to
VM migration
challenges where one system has the bit and the other does not).
---
> > Thanks,
> > Florian
> >
>
> Here is the v2 patch. OK for master?
>
> Thanks.
>
> --
> H.J.
--
H.J.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
2021-07-01 19:22 ` H.J. Lu
@ 2021-07-02 8:40 ` Florian Weimer
2021-07-02 15:03 ` H.J. Lu
0 siblings, 1 reply; 7+ messages in thread
From: Florian Weimer @ 2021-07-02 8:40 UTC (permalink / raw)
To: H.J. Lu; +Cc: H.J. Lu via Libc-alpha
* H. J. Lu:
>> > Any idea why the microcode update doesn't just clear the RPM bit in
>> > CPUID? This is a bit awkward.
>>
>> I asked it internally.
>
> Here it is
>
> ---
>
> VMM vendors told us that clearing CPUID bits during ucode load is an absolute
> no-go and caused a lot of SW instability in the past (also related to
> VM migration
> challenges where one system has the bit and the other does not).
> ---
I thought we had early microcode loading for that.
This new approach requires patching *everything*, not just glibc. For
example, I have a feeling that qemu-kvm does not pass through the
RTM_ALWAYS_ABORT CPU flag to guests, even though
With your patch, I still see
FAIL: string/tst-memchr-rtm
FAIL: string/tst-memcmp-rtm
FAIL: string/tst-memmove-rtm
FAIL: string/tst-memrchr-rtm
FAIL: string/tst-memset-rtm
FAIL: string/tst-strchr-rtm
FAIL: string/tst-strcpy-rtm
FAIL: string/tst-strlen-rtm
FAIL: string/tst-strncmp-rtm
FAIL: string/tst-strrchr-rtm
error: ../sysdeps/x86/tst-string-rtm.h:63: TSX abort rate: 100.00% (3000 out of 3000)
on a virtualized guest on a machine with this CPU:
cpu family : 6
model : 158
model name : Intel(R) Xeon(R) CPU E3-1240 v6 @ 3.70GHz
stepping : 9
microcode : 0xea
This started after a recent microcode update.
Thanks,
Florian
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
2021-07-02 8:40 ` Florian Weimer
@ 2021-07-02 15:03 ` H.J. Lu
0 siblings, 0 replies; 7+ messages in thread
From: H.J. Lu @ 2021-07-02 15:03 UTC (permalink / raw)
To: Florian Weimer; +Cc: H.J. Lu via Libc-alpha
On Fri, Jul 2, 2021 at 1:40 AM Florian Weimer <fweimer@redhat.com> wrote:
>
> * H. J. Lu:
>
> >> > Any idea why the microcode update doesn't just clear the RPM bit in
> >> > CPUID? This is a bit awkward.
> >>
> >> I asked it internally.
> >
> > Here it is
> >
> > ---
> >
> > VMM vendors told us that clearing CPUID bits during ucode load is an absolute
> > no-go and caused a lot of SW instability in the past (also related to
> > VM migration
> > challenges where one system has the bit and the other does not).
> > ---
>
> I thought we had early microcode loading for that.
>
> This new approach requires patching *everything*, not just glibc. For
> example, I have a feeling that qemu-kvm does not pass through the
> RTM_ALWAYS_ABORT CPU flag to guests, even though
>
> With your patch, I still see
>
> FAIL: string/tst-memchr-rtm
> FAIL: string/tst-memcmp-rtm
> FAIL: string/tst-memmove-rtm
> FAIL: string/tst-memrchr-rtm
> FAIL: string/tst-memset-rtm
> FAIL: string/tst-strchr-rtm
> FAIL: string/tst-strcpy-rtm
> FAIL: string/tst-strlen-rtm
> FAIL: string/tst-strncmp-rtm
> FAIL: string/tst-strrchr-rtm
>
> error: ../sysdeps/x86/tst-string-rtm.h:63: TSX abort rate: 100.00% (3000 out of 3000)
>
> on a virtualized guest on a machine with this CPU:
>
> cpu family : 6
> model : 158
> model name : Intel(R) Xeon(R) CPU E3-1240 v6 @ 3.70GHz
> stepping : 9
> microcode : 0xea
>
> This started after a recent microcode update.
We can also check CPU model and stepping before setting RTM usable in glibc.
--
H.J.
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-07-02 15:04 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-30 18:39 [PATCH] x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033] H.J. Lu
2021-07-01 16:27 ` Florian Weimer
2021-07-01 17:11 ` [PATCH v2] " H.J. Lu
2021-07-01 17:24 ` Florian Weimer
2021-07-01 19:22 ` H.J. Lu
2021-07-02 8:40 ` Florian Weimer
2021-07-02 15:03 ` H.J. Lu
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