Re: [PATCH] x86: Disable RTM on Skylake [BZ #27398]

["H.J. Lu" <hjl.tools@gmail.com>]

On Sat, Mar 27, 2021 at 1:13 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Sat, Mar 27, 2021 at 1:02 PM Florian Weimer <fw@deneb.enyo.de> wrote:
> >
> > * H. J. Lu:
> >
> > > On Sat, Mar 27, 2021 at 12:15 PM Florian Weimer <fw@deneb.enyo.de> wrote:
> > >>
> > >> * H. J. Lu via Libc-alpha:
> > >>
> > >> > Disable RTM explicitly on Skylake since CPUID may incorrectly report RTM
> > >> > feature.
> > >> > ---
> > >> >  sysdeps/x86/cpu-features.c | 4 ++++
> > >> >  1 file changed, 4 insertions(+)
> > >> >
> > >> > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> > >> > index d7248cbb45..3641a48407 100644
> > >> > --- a/sysdeps/x86/cpu-features.c
> > >> > +++ b/sysdeps/x86/cpu-features.c
> > >> > @@ -518,6 +518,10 @@ init_cpu_features (struct cpu_features *cpu_features)
> > >> >                with stepping >= 4) to avoid TSX on kernels that weren't
> > >> >                updated with the latest microcode package (which disables
> > >> >                broken feature by default).  */
> > >> > +         case 0x8e:
> > >> > +         case 0x9e:
> > >> > +           /* Disable RTM explicitly on Skylake since CPUID may report
> > >> > +              RTM feature incorrectly [BZ #27398].  */
> > >> >             CPU_FEATURE_UNSET (cpu_features, RTM);
> > >> >             break;
> > >> >           }
> > >>
> > >> Won't this affect the server parts as well?  I'm not sure if that's
> > >> what our users want.
> > >
> > > No since Xeon has a different model number (0x55).
> >
> > Hmm.  Xeon E3-1240 v6 has model number 158 (0x9e), too.
>
> Does it have RTM?

It does have TSX:

https://ark.intel.com/content/www/us/en/ark/products/97469/intel-xeon-processor-e3-1240-v6-8m-cache-3-70-ghz.html

Then my patch won't work.

-- 
H.J.