From: Zong Li <zong.li@sifive.com>
To: palmer@rivosinc.com, darius@bluespec.com, andrew@sifive.com,
dj@redhat.com, joseph@codesourcery.com, schwab@suse.de,
Florian Weimer via Libc-alpha <libc-alpha@sourceware.org>
Subject: Re: [PATCH] riscv: Get level 3 cache's information
Date: Fri, 21 Oct 2022 15:28:03 +0800 [thread overview]
Message-ID: <CANXhq0q4DkktwUL6XFdDjVs9XGM1VrtNGufNMz8d=fppjOAiTA@mail.gmail.com> (raw)
In-Reply-To: <20221021072311.26918-1-zong.li@sifive.com>
On Fri, Oct 21, 2022 at 3:23 PM Zong Li <zong.li@sifive.com> wrote:
>
> RISC-V architecture extends the cache information for level 3 cache
> in AUX vector in Linux v.6.1-rc1. This patch supports sysconf to get
> the level 3 cache information.
> ---
> sysdeps/unix/sysv/linux/riscv/sysconf.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/sysdeps/unix/sysv/linux/riscv/sysconf.c b/sysdeps/unix/sysv/linux/riscv/sysconf.c
> index b768ebf781..4772a9fc11 100644
> --- a/sysdeps/unix/sysv/linux/riscv/sysconf.c
> +++ b/sysdeps/unix/sysv/linux/riscv/sysconf.c
> @@ -90,6 +90,13 @@ __sysconf (int name)
> return sysconf_get_cache_associativity (AT_L2_CACHEGEOMETRY);
> case _SC_LEVEL2_CACHE_LINESIZE:
> return sysconf_get_cache_linesize (AT_L2_CACHEGEOMETRY);
> + case _SC_LEVEL3_CACHE_SIZE:
> + return sysconf_get_cache_size (AT_L3_CACHESIZE);
> + case _SC_LEVEL3_CACHE_ASSOC:
> + return sysconf_get_cache_associativity (AT_L3_CACHEGEOMETRY);
> + case _SC_LEVEL3_CACHE_LINESIZE:
> + return sysconf_get_cache_linesize (AT_L3_CACHEGEOMETRY);
> +
> default:
> return linux_sysconf (name);
> }
> --
> 2.17.1
>
Sorry for missing libc-alpha. Add libc-alpha in this loop.
next parent reply other threads:[~2022-10-21 7:28 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20221021072311.26918-1-zong.li@sifive.com>
2022-10-21 7:28 ` Zong Li [this message]
2022-11-02 1:58 ` Zong Li
2022-11-02 2:19 ` Palmer Dabbelt
2022-11-09 1:12 ` Zong Li
2022-11-09 14:42 ` Adhemerval Zanella Netto
2022-11-09 21:11 ` Palmer Dabbelt
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