From: Aurelien Jarno <aurelien@aurel32.net>
To: Noah Goldstein <goldstein.w.n@gmail.com>
Cc: libc-alpha@sourceware.org, "H . J . Lu" <hjl.tools@gmail.com>,
Sunil K Pandey <skpgkp2@gmail.com>
Subject: Re: [PATCH 4/4] x86-64: Require LZCNT for AVX2 memrchr implementation
Date: Sun, 2 Oct 2022 00:14:46 +0200 [thread overview]
Message-ID: <Yzi71mmaW4cx1qsl@aurel32.net> (raw)
In-Reply-To: <CAFUsyfJk4F-kjpKnphMmQnpY9bz8Tufrp-PgO02SgpB0hNV9Xw@mail.gmail.com>
On 2022-10-01 15:06, Noah Goldstein wrote:
> On Sat, Oct 1, 2022 at 12:09 PM Aurelien Jarno <aurelien@aurel32.net> wrote:
> >
> > The AVX2 memrchr implementation uses the lzcntl and lzcntq instructions,
> > which belongs to the LZCNT CPU feature.
> >
> > Fixes: af5306a735eb ("x86: Optimize memrchr-avx2.S")
> > Partially resolves: BZ #29611
> > ---
> > sysdeps/x86_64/multiarch/ifunc-avx2.h | 1 +
> > sysdeps/x86_64/multiarch/ifunc-impl-list.c | 7 +++++--
> > 2 files changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-avx2.h b/sysdeps/x86_64/multiarch/ifunc-avx2.h
> > index a57a9952f3..f1741083fd 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-avx2.h
> > +++ b/sysdeps/x86_64/multiarch/ifunc-avx2.h
> > @@ -37,6 +37,7 @@ IFUNC_SELECTOR (void)
> >
> > if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)
> > && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)
> > + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, LZCNT)
> > && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features,
> > AVX_Fast_Unaligned_Load, ))
> > {
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > index c628462d47..db5a2032d6 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c
> > @@ -209,13 +209,16 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
> > IFUNC_IMPL (i, name, memrchr,
> > X86_IFUNC_IMPL_ADD_V4 (array, i, memrchr,
> > (CPU_FEATURE_USABLE (AVX512VL)
> > - && CPU_FEATURE_USABLE (AVX512BW)),
> > + && CPU_FEATURE_USABLE (AVX512BW)
> > + && CPU_FEATURE_USABLE (LZCNT)),
>
> Also needs BMI2 for the `shlx`. Likewise for avx2 versions.
Good catch, I haven't look for that one, so I haven't encountered the
issue. Similarly there is 'shrx'.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2022-10-01 22:14 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-01 19:09 [PATCH 0/4] x86: Fix AVX2 string functions requiring BMI2 or LZCNT (BZ #29611) Aurelien Jarno
2022-10-01 19:09 ` [PATCH 1/4] x86: include BMI1 and BMI2 in x86-64-v3 level Aurelien Jarno
2022-10-01 19:09 ` [PATCH 2/4] x86-64: Require BMI2 for AVX2 strn(case)cmp and wcsncmp implementations Aurelien Jarno
2022-10-01 22:15 ` Noah Goldstein
2022-10-01 22:18 ` Noah Goldstein
2022-10-01 19:09 ` [PATCH 3/4] x86-64: Require BMI2 for AVX2 (raw|w)memchr implementations Aurelien Jarno
2022-10-01 19:09 ` [PATCH 4/4] x86-64: Require LZCNT for AVX2 memrchr implementation Aurelien Jarno
2022-10-01 22:06 ` Noah Goldstein
2022-10-01 22:14 ` Aurelien Jarno [this message]
2022-10-01 22:30 ` Noah Goldstein
2022-10-01 22:11 ` [PATCH 0/4] x86: Fix AVX2 string functions requiring BMI2 or LZCNT (BZ #29611) Noah Goldstein
2022-10-01 22:17 ` Aurelien Jarno
2022-10-01 22:17 ` Noah Goldstein
2022-10-02 9:35 ` Aurelien Jarno
2022-10-02 16:19 ` Noah Goldstein
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