* [PATCH] Fix IA-64 POSIX spinlocks
@ 2003-03-07 9:12 Jakub Jelinek
2003-03-09 12:05 ` Ulrich Drepper
0 siblings, 1 reply; 2+ messages in thread
From: Jakub Jelinek @ 2003-03-07 9:12 UTC (permalink / raw)
To: Ulrich Drepper, Roland McGrath; +Cc: Glibc hackers
Hi!
While looking at IA-64 NPTL, I've noticed IA-64 LT spinlocks never
worked. This patch updates them to what I have in my IA-64 NPTL
tree (passes tst-spin{1,2,3} then).
2003-03-07 Jakub Jelinek <jakub@redhat.com>
* sysdeps/ia64/pspinlock.c (__pthread_spin_lock,
__pthread_spin_trylock): Rewritten.
--- libc/linuxthreads/sysdeps/ia64/pspinlock.c.jj 2002-08-27 17:19:43.000000000 -0400
+++ libc/linuxthreads/sysdeps/ia64/pspinlock.c 2003-03-07 04:07:42.000000000 -0500
@@ -1,5 +1,5 @@
/* POSIX spinlock implementation. ia64 version.
- Copyright (C) 2000 Free Software Foundation, Inc.
+ Copyright (C) 2000, 2003 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Jes Sorensen <jes@linuxcare.com>
@@ -21,6 +21,7 @@
#include <errno.h>
#include <pthread.h>
#include "internals.h"
+#include <ia64intrin.h>
/* This implementation is inspired by the implementation used in the
Linux kernel. */
@@ -28,21 +29,15 @@
int
__pthread_spin_lock (pthread_spinlock_t *lock)
{
- asm volatile
- ("mov ar.ccv = r0\n\t"
- "mov r3 = 1\n\t"
- ";;\n"
- "1:\n\t"
- "ld4 r2 = %0\n\t"
- ";;\n\t"
- "cmp4.eq p0, p7 = r0, r2\n\t"
- "(p7) br.cond.spnt.few 1b \n\t"
- "cmpxchg4.acq r2 = %0, r3, ar.ccv\n\t"
- ";;\n\t"
- "cmp4.eq p0, p7 = r0, r2\n\t"
- "(p7) br.cond.spnt.few 1b\n\t"
- ";;\n"
- :: "m" (lock) : "r2", "r3", "p7", "memory");
+ int *p = (int *) lock;
+
+ while (__builtin_expect (__sync_val_compare_and_swap_si (p, 0, 1), 0))
+ {
+ /* Spin without using the atomic instruction. */
+ do
+ __asm __volatile ("" : : : "memory");
+ while (*p);
+ }
return 0;
}
weak_alias (__pthread_spin_lock, pthread_spin_lock)
@@ -51,16 +46,7 @@ weak_alias (__pthread_spin_lock, pthread
int
__pthread_spin_trylock (pthread_spinlock_t *lock)
{
- int oldval;
-
- asm volatile
- ("mov ar.ccv = r0\n\t"
- "mov r2 = 1\n\t"
- ";;\n\t"
- "cmpxchg4.acq %0 = %1, r2, ar.ccv\n\t"
- ";;\n"
- : "=r" (oldval) : "m" (lock) : "r2", "memory");
- return oldval > 0 ? 0 : EBUSY;
+ return __sync_val_compare_and_swap_si ((int *) lock, 0, 1) == 0 ? 0 : EBUSY;
}
weak_alias (__pthread_spin_trylock, pthread_spin_trylock)
Jakub
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] Fix IA-64 POSIX spinlocks
2003-03-07 9:12 [PATCH] Fix IA-64 POSIX spinlocks Jakub Jelinek
@ 2003-03-09 12:05 ` Ulrich Drepper
0 siblings, 0 replies; 2+ messages in thread
From: Ulrich Drepper @ 2003-03-09 12:05 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Roland McGrath, Glibc hackers
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Jakub Jelinek wrote:
> While looking at IA-64 NPTL, I've noticed IA-64 LT spinlocks never
> worked. This patch updates them to what I have in my IA-64 NPTL
> tree (passes tst-spin{1,2,3} then).
Thanks, I've applied it.
- --
- --------------. ,-. 444 Castro Street
Ulrich Drepper \ ,-----------------' \ Mountain View, CA 94041 USA
Red Hat `--' drepper at redhat.com `---------------------------
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.1 (GNU/Linux)
iD8DBQE+aRwr2ijCOnn/RHQRAkxtAJ9AlgRZxjeQjTEU6mf+M3uyh1G5PACfcujQ
nNql0dnDNd7U0FmvWwI4DxM=
=giUT
-----END PGP SIGNATURE-----
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2003-03-07 22:23 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2003-03-07 9:12 [PATCH] Fix IA-64 POSIX spinlocks Jakub Jelinek
2003-03-09 12:05 ` Ulrich Drepper
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).