From: Roland McGrath <roland@hack.frob.com>
To: "Joseph S. Myers" <joseph@codesourcery.com>
Cc: Richard Henderson <rth@twiddle.net>, <libc-ports@sourceware.org>
Subject: [PATCH 2/2 roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb.
Date: Tue, 12 Mar 2013 17:08:00 -0000 [thread overview]
Message-ID: <20130312170814.10BD22C074@topped-with-meat.com> (raw)
In-Reply-To: Joseph S. Myers's message of Tuesday, 12 March 2013 15:58:09 +0000 <Pine.LNX.4.64.1303121557190.450@digraph.polyomino.org.uk>
ports/ChangeLog.arm
* sysdeps/arm/armv6t2/memchr.S [NO_THUMB]:
Use .arm rather than .thumb, .thumb_func. Avoid cbz/cnbz instructions.
--- a/ports/sysdeps/arm/armv6t2/memchr.S
+++ b/ports/sysdeps/arm/armv6t2/memchr.S
@@ -42,10 +42,12 @@
.syntax unified
.text
+#ifdef NO_THUMB
+ .arm
+#else
.thumb
-
-@ ---------------------------------------------------------------------------
.thumb_func
+#endif
.global memchr
.type memchr,%function
ENTRY(memchr)
@@ -89,14 +91,22 @@ ENTRY(memchr)
15:
ldrd r4,r5, [r0],#8
+#ifndef NO_THUMB
subs r6, r6, #8
+#endif
eor r4,r4, r1 @ Get it so that r4,r5 have 00's where the bytes match the target
eor r5,r5, r1
uadd8 r4, r4, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0
sel r4, r3, r7 @ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
uadd8 r5, r5, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0
sel r5, r4, r7 @ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
+#ifndef NO_THUMB
cbnz r5, 60f
+#else
+ cmp r5, #0
+ bne 60f
+ subs r6, r6, #8
+#endif
bne 15b @ (Flags from the subs above) If not run out of bytes then go around again
pop {r4,r5,r6,r7}
@@ -110,13 +120,24 @@ ENTRY(memchr)
and r2,r2,#7 @ Leave the count remaining as the number after the double words have been done
20:
+#ifndef NO_THUMB
cbz r2, 40f @ 0 length or hit the end already then not found
+#else
+ cmp r2, #0
+ beq 40f
+#endif
21: @ Post aligned section, or just a short call
ldrb r3,[r0],#1
+#ifndef NO_THUMB
subs r2,r2,#1
eor r3,r3,r1 @ r3 = 0 if match - doesn't break flags from sub
cbz r3, 50f
+#else
+ eors r3, r3, r1
+ beq 50f
+ subs r2, r2, #1
+#endif
bne 21b @ on r2 flags
40:
next prev parent reply other threads:[~2013-03-12 17:08 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-11 23:31 [PATCH " Roland McGrath
2013-03-12 0:30 ` Joseph S. Myers
2013-03-12 6:09 ` Richard Henderson
2013-03-12 15:58 ` Joseph S. Myers
2013-03-12 17:07 ` [PATCH 1/2 roland/arm-memchr] ARM: Change register allocation in armv6t2 memchr implementation Roland McGrath
2013-03-12 23:20 ` Joseph S. Myers
2013-03-13 0:06 ` Roland McGrath
2013-03-12 17:08 ` Roland McGrath [this message]
2013-03-12 23:21 ` [PATCH 2/2 roland/arm-memchr] ARM: Make armv6t2 memchr implementation usable without Thumb Joseph S. Myers
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