[gcc r11-7872] Daily bump.

[gcc r11-7872] Daily bump.

[GCC Administrator]

https://gcc.gnu.org/g:651684b462f979a4e70a668c4c9767a5fd7d223a

commit r11-7872-g651684b462f979a4e70a668c4c9767a5fd7d223a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Sat Mar 27 00:16:27 2021 +0000

    Daily bump.

Diff:
---
 ChangeLog               |   4 +
 gcc/ChangeLog           | 270 ++++++++++++++++++++++++++++++++++++++++++++++++
 gcc/DATESTAMP           |   2 +-
 gcc/cp/ChangeLog        |  41 ++++++++
 gcc/fortran/ChangeLog   |   6 ++
 gcc/testsuite/ChangeLog |  48 +++++++++
 libphobos/ChangeLog     |  20 ++++
 libstdc++-v3/ChangeLog  |  26 +++++
 8 files changed, 416 insertions(+), 1 deletion(-)

diff --git a/ChangeLog b/ChangeLog
index ba411e22ce5..e55a5e4a2bb 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,7 @@
+2021-03-26  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+	* MAINTAINERS: Add myself as pru port maintainer.
+
 2021-03-23  David Malcolm  <dmalcolm@redhat.com>
 
 	* MAINTAINERS: Add myself as static analyzer maintainer.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cb823ef29f1..d592d55bfbe 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,273 @@
+2021-03-26  David Edelsohn  <dje.gcc@gmail.com>
+
+	* config/rs6000/aix.h (ADJUST_FIELD_ALIGN): Call function.
+	* config/rs6000/rs6000-protos.h (rs6000_special_adjust_field_align):
+	Declare.
+	* config/rs6000/rs6000.c (rs6000_special_adjust_field_align): New.
+	(rs6000_special_round_type_align): Recursively check innermost first
+	field.
+
+2021-03-26  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/99334
+	* dwarf2out.h (struct dw_fde_node): Add rule18 member.
+	* dwarf2cfi.c (dwarf2out_frame_debug_expr): When handling (set hfp sp)
+	assignment with drap_reg active, queue reg save for hfp with offset 0
+	and flush queued reg saves.  When handling a push with rule18,
+	defer queueing reg save for hfp and just assert the offset is 0.
+	(scan_trace): Assert that fde->rule18 is false.
+
+2021-03-26  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR target/99766
+	* ira-costs.c (record_reg_classes): Put case with
+	CT_RELAXED_MEMORY adjacent to one with CT_MEMORY.
+	* ira.c (ira_setup_alts): Ditto.
+	* lra-constraints.c (process_alt_operands): Ditto.
+	* recog.c (asm_operand_ok): Ditto.
+	* reload.c (find_reloads): Ditto.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-protos.h
+	(cpu_addrcost_table::post_modify_ld3_st3): New member variable.
+	(cpu_addrcost_table::post_modify_ld4_st4): Likewise.
+	* config/aarch64/aarch64.c (generic_addrcost_table): Update
+	accordingly, using the same costs as for post_modify.
+	(exynosm1_addrcost_table, xgene1_addrcost_table): Likewise.
+	(thunderx2t99_addrcost_table, thunderx3t110_addrcost_table):
+	(tsv110_addrcost_table, qdf24xx_addrcost_table): Likewise.
+	(a64fx_addrcost_table): Likewise.
+	(neoversev1_addrcost_table): New.
+	(neoversev1_tunings): Use neoversev1_addrcost_table.
+	(aarch64_address_cost): Use the new post_modify costs for CImode
+	and XImode.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.opt
+	(-param=aarch64-loop-vect-issue-rate-niters=): New parameter.
+	* doc/invoke.texi: Document it.
+	* config/aarch64/aarch64-protos.h (aarch64_base_vec_issue_info)
+	(aarch64_scalar_vec_issue_info, aarch64_simd_vec_issue_info)
+	(aarch64_advsimd_vec_issue_info, aarch64_sve_vec_issue_info)
+	(aarch64_vec_issue_info): New structures.
+	(cpu_vector_cost): Write comments above the variables rather
+	than to the side.
+	(cpu_vector_cost::issue_info): New member variable.
+	* config/aarch64/aarch64.c: Include gimple-pretty-print.h
+	and tree-ssa-loop-niter.h.
+	(generic_vector_cost, a64fx_vector_cost, qdf24xx_vector_cost)
+	(thunderx_vector_cost, tsv110_vector_cost, cortexa57_vector_cost)
+	(exynosm1_vector_cost, xgene1_vector_cost, thunderx2t99_vector_cost)
+	(thunderx3t110_vector_cost): Initialize issue_info to null.
+	(neoversev1_scalar_issue_info, neoversev1_advsimd_issue_info)
+	(neoversev1_sve_issue_info, neoversev1_vec_issue_info): New structures.
+	(neoversev1_vector_cost): Use them.
+	(aarch64_vec_op_count, aarch64_sve_op_count): New structures.
+	(aarch64_vector_costs::saw_sve_only_op): New member variable.
+	(aarch64_vector_costs::num_vector_iterations): Likewise.
+	(aarch64_vector_costs::scalar_ops): Likewise.
+	(aarch64_vector_costs::advsimd_ops): Likewise.
+	(aarch64_vector_costs::sve_ops): Likewise.
+	(aarch64_vector_costs::seen_loads): Likewise.
+	(aarch64_simd_vec_costs_for_flags): New function.
+	(aarch64_analyze_loop_vinfo): Initialize num_vector_iterations.
+	Count the number of predicate operations required by SVE WHILE
+	instructions.
+	(aarch64_comparison_type, aarch64_multiply_add_p): New functions.
+	(aarch64_sve_only_stmt_p, aarch64_in_loop_reduction_latency): Likewise.
+	(aarch64_count_ops): Likewise.
+	(aarch64_add_stmt_cost): Record whether see an SVE operation
+	that cannot currently be implementing using Advanced SIMD.
+	Record issue information about the scalar, Advanced SIMD
+	and (where relevant) SVE versions of a loop.
+	(aarch64_vec_op_count::dump): New function.
+	(aarch64_sve_op_count::dump): Likewise.
+	(aarch64_estimate_min_cycles_per_iter): Likewise.
+	(aarch64_adjust_body_cost): If issue information is available,
+	try to compare the issue rates of the various loop implementations
+	and increase or decrease the vector body cost accordingly.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.c (aarch64_detect_vector_stmt_subtype):
+	Assume a zero cost for induction phis.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.c (aarch64_embedded_comparison_type): New
+	function.
+	(aarch64_adjust_stmt_cost): Add the costs of embedded scalar and
+	vector comparisons.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.c (aarch64_detect_scalar_stmt_subtype):
+	New function.
+	(aarch64_add_stmt_cost): Call it.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-tuning-flags.def (matched_vector_throughput):
+	New tuning parameter.
+	* config/aarch64/aarch64.c (neoversev1_tunings): Use it.
+	(aarch64_estimated_sve_vq): New function.
+	(aarch64_vector_costs::analyzed_vinfo): New member variable.
+	(aarch64_vector_costs::is_loop): Likewise.
+	(aarch64_vector_costs::unrolled_advsimd_niters): Likewise.
+	(aarch64_vector_costs::unrolled_advsimd_stmts): Likewise.
+	(aarch64_record_potential_advsimd_unrolling): New function.
+	(aarch64_analyze_loop_vinfo, aarch64_analyze_bb_vinfo): Likewise.
+	(aarch64_add_stmt_cost): Call aarch64_analyze_loop_vinfo or
+	aarch64_analyze_bb_vinfo on the first use of a costs structure.
+	Detect whether we're vectorizing a loop for SVE that might be
+	completely unrolled if it used Advanced SIMD instead.
+	(aarch64_adjust_body_cost_for_latency): New function.
+	(aarch64_finish_cost): Call it.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.c (aarch64_vector_costs): New structure.
+	(aarch64_init_cost): New function.
+	(aarch64_add_stmt_cost): Use aarch64_vector_costs instead of
+	the default unsigned[3].
+	(aarch64_finish_cost, aarch64_destroy_cost_data): New functions.
+	(TARGET_VECTORIZE_INIT_COST): Override.
+	(TARGET_VECTORIZE_FINISH_COST): Likewise.
+	(TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.c (neoversev1_advsimd_vector_cost)
+	(neoversev1_sve_vector_cost): New cost structures.
+	(neoversev1_vector_cost): Likewise.
+	(neoversev1_tunings): Use them.  Enable use_new_vector_costs.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-protos.h
+	(sve_vec_cost::scatter_store_elt_cost): New member variable.
+	* config/aarch64/aarch64.c (generic_sve_vector_cost): Update
+	accordingly, taking the cost from the cost of a scalar_store.
+	(a64fx_sve_vector_cost): Likewise.
+	(aarch64_detect_vector_stmt_subtype): Detect scatter stores.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-protos.h
+	(simd_vec_cost::store_elt_extra_cost): New member variable.
+	* config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
+	accordingly, using the vec_to_scalar cost for the new field.
+	(generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
+	(a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
+	(thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
+	(cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
+	(xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
+	(thunderx3t110_advsimd_vector_cost): Likewise.
+	(aarch64_detect_vector_stmt_subtype): Detect single-element stores.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-protos.h (simd_vec_cost::ld2_st2_permute_cost)
+	(simd_vec_cost::ld3_st3_permute_cost): New member variables.
+	(simd_vec_cost::ld4_st4_permute_cost): Likewise.
+	* config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
+	accordingly, using zero for the new costs.
+	(generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
+	(a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
+	(thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
+	(cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
+	(xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
+	(thunderx3t110_advsimd_vector_cost): Likewise.
+	(aarch64_ld234_st234_vectors): New function.
+	(aarch64_adjust_stmt_cost): Likewise.
+	(aarch64_add_stmt_cost): Call aarch64_adjust_stmt_cost if using
+	the new vector costs.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-protos.h (sve_vec_cost): Turn into a
+	derived class of simd_vec_cost.  Add information about CLAST[AB]
+	and FADDA instructions.
+	* config/aarch64/aarch64.c (generic_sve_vector_cost): Update
+	accordingly, using the vec_to_scalar costs for the new fields.
+	(a64fx_sve_vector_cost): Likewise.
+	(aarch64_reduc_type): New function.
+	(aarch64_sve_in_loop_reduction_latency): Likewise.
+	(aarch64_detect_vector_stmt_subtype): Take a vinfo parameter.
+	Use aarch64_sve_in_loop_reduction_latency to handle SVE reductions
+	that occur in the loop body.
+	(aarch64_add_stmt_cost): Update call accordingly.
+
+2021-03-26  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-tuning-flags.def (use_new_vector_costs):
+	New tuning flag.
+	* config/aarch64/aarch64-protos.h (simd_vec_cost): Put comments
+	above the fields rather than to the right.
+	(simd_vec_cost::reduc_i8_cost): New member variable.
+	(simd_vec_cost::reduc_i16_cost): Likewise.
+	(simd_vec_cost::reduc_i32_cost): Likewise.
+	(simd_vec_cost::reduc_i64_cost): Likewise.
+	(simd_vec_cost::reduc_f16_cost): Likewise.
+	(simd_vec_cost::reduc_f32_cost): Likewise.
+	(simd_vec_cost::reduc_f64_cost): Likewise.
+	* config/aarch64/aarch64.c (generic_advsimd_vector_cost): Update
+	accordingly, using the vec_to_scalar_cost for the new fields.
+	(generic_sve_vector_cost, a64fx_advsimd_vector_cost): Likewise.
+	(a64fx_sve_vector_cost, qdf24xx_advsimd_vector_cost): Likewise.
+	(thunderx_advsimd_vector_cost, tsv110_advsimd_vector_cost): Likewise.
+	(cortexa57_advsimd_vector_cost, exynosm1_advsimd_vector_cost)
+	(xgene1_advsimd_vector_cost, thunderx2t99_advsimd_vector_cost)
+	(thunderx3t110_advsimd_vector_cost): Likewise.
+	(aarch64_use_new_vector_costs_p): New function.
+	(aarch64_simd_vec_costs): New function, split out from...
+	(aarch64_builtin_vectorization_cost): ...here.
+	(aarch64_is_reduction): New function.
+	(aarch64_detect_vector_stmt_subtype): Likewise.
+	(aarch64_add_stmt_cost): Call aarch64_detect_vector_stmt_subtype if
+	using the new vector costs.
+
+2021-03-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR ipa/99466
+	* tree-emutls.c (get_emutls_init_templ_addr): Mark initializer of weak
+	TLS declarations as public.
+
+2021-03-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	* config/aarch64/aarch64-d.c (IN_TARGET_CODE): Define.
+	* config/arm/arm-d.c (IN_TARGET_CODE): Likewise.
+	* config/i386/i386-d.c (IN_TARGET_CODE): Likewise.
+	* config/mips/mips-d.c (IN_TARGET_CODE): Likewise.
+	* config/pa/pa-d.c (IN_TARGET_CODE): Likewise.
+	* config/riscv/riscv-d.c (IN_TARGET_CODE): Likewise.
+	* config/rs6000/rs6000-d.c (IN_TARGET_CODE): Likewise.
+	* config/s390/s390-d.c (IN_TARGET_CODE): Likewise.
+	* config/sparc/sparc-d.c (IN_TARGET_CODE): Likewise.
+
+2021-03-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/91595
+	* config.gcc (*-*-cygwin*): Add winnt-d.o
+	(*-*-mingw*): Likewise.
+	* config/i386/cygwin.h (EXTRA_TARGET_D_OS_VERSIONS): New macro.
+	* config/i386/mingw32.h (EXTRA_TARGET_D_OS_VERSIONS): Likewise.
+	* config/i386/t-cygming: Add winnt-d.o.
+	* config/i386/winnt-d.c: New file.
+
+2021-03-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	* config/freebsd-d.c: Include memmodel.h.
+
+2021-03-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR d/99691
+	* config.gcc (*-*-openbsd*): Add openbsd-d.o.
+	* config/t-openbsd: Add openbsd-d.o.
+	* config/openbsd-d.c: New file.
+
 2021-03-25  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 
 	PR tree-optimization/96974
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 782e9649ba5..71fa6a1d2e3 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20210326
+20210327
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index ba750a264cb..eb482659150 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,44 @@
+2021-03-26  Marek Polacek  <polacek@redhat.com>
+
+	PR c++/98352
+	* method.c (implicitly_declare_fn): Pass &raises to
+	synthesized_method_walk.
+
+2021-03-26  Nathan Sidwell  <nathan@acm.org>
+
+	PR c++/99283
+	* cp-tree.h (DECL_MODULE_CHECK): Ban TEMPLATE_DECL.
+	(SET_TYPE_TEMPLATE_INFO): Restore Alias template setting.
+	* decl.c (duplicate_decls): Remove template_decl module flag
+	propagation.
+	* module.cc (merge_kind_name): Add alias tmpl spec as a thing.
+	(dumper::impl::nested_name): Adjust for template-decl module flag
+	change.
+	(trees_in::assert_definition): Likewise.
+	(trees_in::install_entity): Likewise.
+	(trees_out::decl_value): Likewise.  Remove alias template
+	separation of template and type_decl.
+	(trees_in::decl_value): Likewise.
+	(trees_out::key_mergeable): Likewise,
+	(trees_in::key_mergeable): Likewise.
+	(trees_out::decl_node): Adjust for template-decl module flag
+	change.
+	(depset::hash::make_dependency): Likewise.
+	(get_originating_module, module_may_redeclare): Likewise.
+	(set_instantiating_module, set_defining_module): Likewise.
+	* name-lookup.c (name_lookup::search_adl): Likewise.
+	(do_pushdecl): Likewise.
+	* pt.c (build_template_decl): Likewise.
+	(lookup_template_class_1): Remove special alias_template handling
+	of DECL_TI_TEMPLATE.
+	(tsubst_template_decl): Likewise.
+
+2021-03-26  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/99705
+	* tree.c (bot_manip): Remap artificial automatic temporaries mentioned
+	in DECL_EXPR or in BIND_EXPR_VARS.
+
 2021-03-25  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c++/99672
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 5a7a57a59ba..b3cda939942 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,9 @@
+2021-03-26  Tobias Burnus  <tobias@codesourcery.com>
+
+	PR fortran/99651
+	* intrinsic.c (gfc_intrinsic_func_interface): Set
+	attr.proc = PROC_INTRINSIC if FL_PROCEDURE.
+
 2021-03-24  Tobias Burnus  <tobias@codesourcery.com>
 
 	PR fortran/99369
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 45af4ac44fa..9abcc02447e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,51 @@
+2021-03-26  David Edelsohn  <dje.gcc@gmail.com>
+
+	* gcc.target/powerpc/pr99557.c: New.
+
+2021-03-26  Martin Sebor  <msebor@redhat.com>
+
+	PR tree-optimization/59970
+	* gcc.dg/uninit-pr59970.c: New test.
+
+2021-03-26  Marek Polacek  <polacek@redhat.com>
+
+	PR c++/98352
+	* g++.dg/cpp0x/inh-ctor37.C: Remove dg-error.
+	* g++.dg/cpp0x/nsdmi17.C: New test.
+
+2021-03-26  Nathan Sidwell  <nathan@acm.org>
+
+	PR c++/99283
+	* g++.dg/modules/pr99283-2_a.H: New.
+	* g++.dg/modules/pr99283-2_b.H: New.
+	* g++.dg/modules/pr99283-2_c.H: New.
+	* g++.dg/modules/pr99283-3_a.H: New.
+	* g++.dg/modules/pr99283-3_b.H: New.
+	* g++.dg/modules/pr99283-4.H: New.
+	* g++.dg/modules/tpl-alias-1_a.H: Adjust scans.
+	* g++.dg/modules/tpl-alias-1_b.C: Adjust scans.
+
+2021-03-26  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR target/99766
+	* g++.target/aarch64/sve/pr99766.C: New.
+
+2021-03-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	PR ipa/99466
+	* gcc.dg/tls/pr99466-1.c: New test.
+	* gcc.dg/tls/pr99466-2.c: New test.
+
+2021-03-26  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/99705
+	* g++.dg/cpp0x/new5.C: New test.
+
+2021-03-26  Tobias Burnus  <tobias@codesourcery.com>
+
+	PR fortran/99651
+	* gfortran.dg/null_11.f90: New test.
+
 2021-03-25  Martin Sebor  <msebor@redhat.com>
 
 	PR tree-optimization/55060
diff --git a/libphobos/ChangeLog b/libphobos/ChangeLog
index 235af5b2fd3..e58bd3ce2e1 100644
--- a/libphobos/ChangeLog
+++ b/libphobos/ChangeLog
@@ -1,3 +1,23 @@
+2021-03-26  Iain Buclaw  <ibuclaw@gdcproject.org>
+
+	* Makefile.in: Regenerate.
+	* configure: Regenerate.
+	* configure.ac: Substitute enable_shared, enable_static, and
+	phobos_lt_pic_flag.
+	* libdruntime/Makefile.am (AM_DFLAGS): Replace
+	  phobos_compiler_pic_flag with phobos_lt_pic_flags, and
+	  phobos_compiler_shared_flag.
+	* libdruntime/Makefile.in: Regenerate.
+	* src/Makefile.am (AM_DFLAGS): Replace phobos_compiler_pic_flag
+	  with phobos_lt_pic_flag, and phobos_compiler_shared_flag.
+	* src/Makefile.in: Regenerate.
+	* testsuite/Makefile.in: Regenerate.
+	* testsuite/libphobos.druntime_shared/druntime_shared.exp: Remove
+	-fversion=Shared and -fno-moduleinfo from default extra test flags.
+	* testsuite/libphobos.phobos_shared/phobos_shared.exp: Likewise.
+	* testsuite/testsuite_flags.in: Add phobos_compiler_shared_flag to
+	--gdcflags.
+
 2021-02-04  Iain Buclaw  <ibuclaw@gdcproject.org>
 
 	PR d/98910
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index c9e7bc8fbd6..3f90a883cc9 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,29 @@
+2021-03-26  Jonathan Wakely  <jwakely@redhat.com>
+
+	* src/c++11/random.cc (USE_LCG): Define when a pseudo-random
+	fallback is needed.
+	[USE_LCG] (bad_seed, construct_lcg_at, destroy_lcg_at, __lcg):
+	New helper functions and callback.
+	(random_device::_M_init): Add 'prng' and 'all' enumerators.
+	Replace switch with fallthrough with a series of 'if' statements.
+	[USE_LCG]: Construct an lcg_type engine and use __lcg when cpuid
+	checks fail.
+	(random_device::_M_init_pretr1) [USE_MT19937]: Accept "prng"
+	token.
+	(random_device::_M_getval): Check for callback unconditionally
+	and always pass _M_file pointer.
+	* testsuite/26_numerics/random/random_device/85494.cc: Remove
+	effective-target check. Use new random_device_available helper.
+	* testsuite/26_numerics/random/random_device/94087.cc: Likewise.
+	* testsuite/26_numerics/random/random_device/cons/default-cow.cc:
+	Remove effective-target check.
+	* testsuite/26_numerics/random/random_device/cons/default.cc:
+	Likewise.
+	* testsuite/26_numerics/random/random_device/cons/token.cc: Use
+	new random_device_available helper. Test "prng" token.
+	* testsuite/util/testsuite_random.h (random_device_available):
+	New helper function.
+
 2021-03-25  François Dumont  <fdumont@gcc.gnu.org>
 
 	* include/debug/string