[gcc r12-2289] Daily bump.

[gcc r12-2289] Daily bump.

[GCC Administrator]

https://gcc.gnu.org/g:0e7754560f694b4e702baebdc481f6b0e82f7b14

commit r12-2289-g0e7754560f694b4e702baebdc481f6b0e82f7b14
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Wed Jul 14 00:16:44 2021 +0000

    Daily bump.

Diff:
---
 gcc/ChangeLog           | 186 ++++++++++++++++++++++++++++++++++++++++++++++++
 gcc/DATESTAMP           |   2 +-
 gcc/testsuite/ChangeLog | 157 ++++++++++++++++++++++++++++++++++++++++
 libgomp/ChangeLog       |   7 ++
 libstdc++-v3/ChangeLog  |  11 +++
 5 files changed, 362 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 98570fe405c..ebeb27414ff 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,189 @@
+2021-07-13  Jonathan Wright  <jonathan.wright@arm.com>
+
+	* combine.c (combine_simplify_rtx): Add vec_select -> subreg
+	simplification.
+	* config/aarch64/aarch64.md (*zero_extend<SHORT:mode><GPI:mode>2_aarch64):
+	Add Neon to general purpose register case for zero-extend
+	pattern.
+	* config/arm/vfp.md (*arm_movsi_vfp): Remove "*" from *t -> r
+	case to prevent some cases opting to go through memory.
+	* cse.c (fold_rtx): Add vec_select -> subreg simplification.
+	* rtl.c (rtvec_series_p): Define predicate to determine
+	whether a vector contains a linear series of integers.
+	* rtl.h (rtvec_series_p): Define.
+	* rtlanal.c (vec_series_lowpart_p): Define predicate to
+	determine if a vector selection is equivalent to the low part
+	of the vector.
+	* rtlanal.h (vec_series_lowpart_p): Define.
+	* simplify-rtx.c (simplify_context::simplify_binary_operation_1):
+	Add vec_select -> subreg simplification.
+
+2021-07-13  Paul A. Clarke  <pc@us.ibm.com>
+
+	* config/rs6000/smmintrin.h (_mm_testz_si128, _mm_testc_si128,
+	_mm_testnzc_si128, _mm_test_all_ones, _mm_test_all_zeros,
+	_mm_test_mix_ones_zeros): New.
+
+2021-07-13  Roger Sayle  <roger@nextmovesoftware.com>
+	    Richard Biener  <rguenther@suse.de>
+
+	* gimple.c (gimple_could_trap_p_1):  Make S argument a
+	"const gimple*".  Preserve constness in call to
+	gimple_asm_volatile_p.
+	(gimple_could_trap_p): Make S argument a "const gimple*".
+	* gimple.h (gimple_could_trap_p_1, gimple_could_trap_p):
+	Update function prototypes.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-vectorizer.h (vect_reusable_accumulator): New structure.
+	(_loop_vec_info::main_loop_edge): New field.
+	(_loop_vec_info::skip_main_loop_edge): Likewise.
+	(_loop_vec_info::skip_this_loop_edge): Likewise.
+	(_loop_vec_info::reusable_accumulators): Likewise.
+	(_stmt_vec_info::reduc_scalar_results): Likewise.
+	(_stmt_vec_info::reused_accumulator): Likewise.
+	(vect_get_main_loop_result): Declare.
+	* tree-vectorizer.c (vec_info::new_stmt_vec_info): Initialize
+	reduc_scalar_inputs.
+	(vec_info::free_stmt_vec_info): Free reduc_scalar_inputs.
+	* tree-vect-loop-manip.c (vect_get_main_loop_result): New function.
+	(vect_do_peeling): Fill an epilogue loop's main_loop_edge,
+	skip_main_loop_edge and skip_this_loop_edge fields.
+	* tree-vect-loop.c (INCLUDE_ALGORITHM): Define.
+	(vect_emit_reduction_init_stmts): New function.
+	(get_initial_def_for_reduction): Use it.
+	(get_initial_defs_for_reduction): Likewise.  Change the vinfo
+	parameter to a loop_vec_info.
+	(vect_create_epilog_for_reduction): Store the scalar results
+	in the reduc_info.  If an epilogue loop is reusing an accumulator
+	from the main loop, and if the epilogue loop can also be skipped,
+	try to place the reduction code in the join block.  Record
+	accumulators that could potentially be reused by epilogue loops.
+	(vect_transform_cycle_phi): When vectorizing epilogue loops,
+	try to reuse accumulators from the main loop.  Record the initial
+	value in reduc_info for non-SLP reductions too.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-vect-loop.c (get_initial_def_for_reduction): Remove
+	adjustment handling.  Take the neutral value as an argument,
+	in place of the code argument.
+	(vect_transform_cycle_phi): Update accordingly.  Handle the
+	initial values of cond reductions separately from code reductions.
+	Choose the adjustment here rather than in
+	get_initial_def_for_reduction.  Sink the splat of vec_initial_def.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-vect-loop.c (neutral_op_for_slp_reduction): Replace with...
+	(neutral_op_for_reduction): ...this, providing a more general
+	interface.
+	(vect_create_epilog_for_reduction): Update accordingly.
+	(vectorizable_reduction): Likewise.
+	(vect_transform_cycle_phi): Likewise.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-vect-loop.c (get_initial_def_for_reduction): Take the
+	reduc_info instead of the original stmt_vec_info.
+	(vect_transform_cycle_phi): Update accordingly.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-vect-loop.c (get_initial_defs_for_reduction): Take the
+	reduc_info as an additional parameter.
+	(vect_transform_cycle_phi): Update accordingly.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-vectorizer.h: Include tree-ssa-operands.h.
+	(vect_phi_initial_value): New function.
+	* tree-vect-loop.c (neutral_op_for_slp_reduction): Use it.
+	(get_initial_defs_for_reduction, info_for_reduction): Likewise.
+	(vect_create_epilog_for_reduction, vectorizable_reduction): Likewise.
+	(vect_transform_cycle_phi, vectorizable_induction): Likewise.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-vect-loop.c (vect_create_epilog_for_reduction): Convert
+	the phi results to vectype after creating them.  Remove later
+	conversion code that thus becomes redundant.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-vect-loop.c (vect_create_epilog_for_reduction): Replace
+	the new_phis vector with a reduc_inputs vector.  Combine handling
+	of reduction chains and ncopies > 1.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-vect-loop.c (vect_create_epilog_for_reduction): Truncate
+	scalar_results to group_size elements after reducing down from
+	N*group_size elements.  Construct an array_slice of the live-out
+	stmts and assert that there is one stmt per scalar result.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-vect-loop.c (vect_create_epilog_for_reduction): Remove
+	nested_in_vect_loop and use double_reduc everywhere.  Remove dead
+	assignment to "loop".
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* internal-fn.c (vectorized_internal_fn_supported_p): Handle
+	vector types first.  For scalar types, consider both the preferred
+	vector mode and the alternative vector modes.
+	* optabs-query.c (can_vec_mask_load_store_p): Use the same
+	structure as above, in particular using related_vector_mode
+	for modes provided by autovectorize_vector_modes.
+
+2021-07-13  Jakub Jelinek  <jakub@redhat.com>
+	    Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/101419
+	* tree-pass.h (PROP_objsz): Define.
+	(make_pass_early_object_sizes): Declare.
+	* passes.def (pass_all_early_optimizations): Rename pass_object_sizes
+	there to pass_early_object_sizes, drop parameter.
+	(pass_all_optimizations): Move pass_object_sizes right after pass_ccp,
+	drop parameter, move pass_post_ipa_warn right after that.
+	* tree-object-size.c (pass_object_sizes::execute): Rename to...
+	(object_sizes_execute): ... this.  Add insert_min_max_p argument.
+	(pass_data_object_sizes): Move after object_sizes_execute.
+	(pass_object_sizes): Likewise.  In execute method call
+	object_sizes_execute, drop set_pass_param method and insert_min_max_p
+	non-static data member and its initializer in the ctor.
+	(pass_data_early_object_sizes, pass_early_object_sizes,
+	make_pass_early_object_sizes): New.
+	* tree-ssa-sccvn.c (copy_reference_ops_from_ref): Use
+	(cfun->curr_properties & PROP_objsz) instead of cfun->after_inlining.
+
+2021-07-13  Kito Cheng  <kito.cheng@sifive.com>
+
+	PR target/101275
+	* config/riscv/constraints.md ("S"): Update description and remove
+	@internal.
+	* doc/md.texi (Machine Constraints): Document the 'S' constraints
+	for RISC-V.
+
+2021-07-13  Richard Biener  <rguenther@suse.de>
+
+	Revert:
+	2021-07-12  Richard Biener  <rguenther@suse.de>
+
+	* tree-vect-slp.c (vect_slp_region): Show the number of
+	SLP graph entries in the optimization message.
+
+2021-07-13  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/altivec.md (xxspltiw_v4sf): Change local variable
+	value to to long.
+	* config/rs6000/rs6000-protos.h (rs6000_const_f32_to_i32): Change
+	return type to long.
+	* config/rs6000/rs6000.c (rs6000_const_f32_to_i32): Change return
+	type to long.
+
 2021-07-12  Andrew MacLeod  <amacleod@redhat.com>
 
 	* gimple-range-fold.cc (fold_using_range::range_of_builtin_ubsan_call):
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 12fd5d42259..4b4dbab796b 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20210713
+20210714
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6eacfd028e0..0ed2e934e14 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,160 @@
+2021-07-13  Jonathan Wright  <jonathan.wright@arm.com>
+
+	* gcc.target/aarch64/extract_zero_extend.c: Remove dump scan
+	for RTL pattern match.
+	* gcc.target/aarch64/narrow_high_combine.c: Add new tests.
+	* gcc.target/aarch64/simd/vmulx_laneq_f64_1.c: Update
+	scan-assembler regex to look for a scalar register instead of
+	lane 0 of a vector.
+	* gcc.target/aarch64/simd/vmulxd_laneq_f64_1.c: Likewise.
+	* gcc.target/aarch64/simd/vmulxs_lane_f32_1.c: Likewise.
+	* gcc.target/aarch64/simd/vmulxs_laneq_f32_1.c: Likewise.
+	* gcc.target/aarch64/simd/vqdmlalh_lane_s16.c: Likewise.
+	* gcc.target/aarch64/simd/vqdmlals_lane_s32.c: Likewise.
+	* gcc.target/aarch64/simd/vqdmlslh_lane_s16.c: Likewise.
+	* gcc.target/aarch64/simd/vqdmlsls_lane_s32.c: Likewise.
+	* gcc.target/aarch64/simd/vqdmullh_lane_s16.c: Likewise.
+	* gcc.target/aarch64/simd/vqdmullh_laneq_s16.c: Likewise.
+	* gcc.target/aarch64/simd/vqdmulls_lane_s32.c: Likewise.
+	* gcc.target/aarch64/simd/vqdmulls_laneq_s32.c: Likewise.
+	* gcc.target/aarch64/sve/dup_lane_1.c: Likewise.
+	* gcc.target/aarch64/sve/extract_1.c: Likewise.
+	* gcc.target/aarch64/sve/extract_2.c: Likewise.
+	* gcc.target/aarch64/sve/extract_3.c: Likewise.
+	* gcc.target/aarch64/sve/extract_4.c: Likewise.
+	* gcc.target/aarch64/sve/live_1.c: Update scan-assembler regex
+	cases to look for 'b' and 'h' registers instead of 'w'.
+	* gcc.target/arm/crypto-vsha1cq_u32.c: Update scan-assembler
+	regex to reflect lane 0 vector extractions being simplified
+	to scalar register moves.
+	* gcc.target/arm/crypto-vsha1h_u32.c: Likewise.
+	* gcc.target/arm/crypto-vsha1mq_u32.c: Likewise.
+	* gcc.target/arm/crypto-vsha1pq_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c: Extract
+	lane 1 as the moves for lane 0 now get optimized away.
+	* gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c: Likewise.
+	* gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c: Likewise.
+
+2021-07-13  Paul A. Clarke  <pc@us.ibm.com>
+
+	* gcc.target/powerpc/sse4_1-ptest-1.c: Copy from
+	gcc/testsuite/gcc.target/i386.
+
+2021-07-13  Andrew MacLeod  <amacleod@redhat.com>
+
+	PR tree-optimization/93781
+	* gcc.dg/tree-ssa/pr93781-1.c: Check that call is removed.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sve/reduc_9.c: New test.
+	* gcc.target/aarch64/sve/reduc_9_run.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_10.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_10_run.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_11.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_11_run.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_12.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_12_run.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_13.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_13_run.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_14.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_14_run.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_15.c: Likewise.
+	* gcc.target/aarch64/sve/reduc_15_run.c: Likewise.
+
+2021-07-13  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sve/cond_arith_6.c: New test.
+
+2021-07-13  Jakub Jelinek  <jakub@redhat.com>
+	    Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/101419
+	* gcc.dg/builtin-object-size-10.c: Pass -fdump-tree-early_objsz-details
+	instead of -fdump-tree-objsz1-details in dg-options and adjust names
+	of dump file in scan-tree-dump.
+	* gcc.dg/pr101419.c: New test.
+
+2021-07-13  Richard Biener  <rguenther@suse.de>
+
+	Revert:
+	2021-07-13  Richard Biener  <rguenther@suse.de>
+
+	* g++.dg/vect/slp-pr87105.cc: Adjust.
+	* gcc.dg/vect/bb-slp-pr54400.c: Likewise.
+
+2021-07-13  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR testsuite/100166
+	* gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c: Update
+	insn counts to account for power10 prefixed loads and stores.
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c: Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c: Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c: Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c: Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c: Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_xl-char.c: Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_xl-double.c: Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_xl-float.c: Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_xl-int.c: Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c: Likewise.
+	* gcc.target/powerpc/fold-vec-load-vec_xl-short.c: Likewise.
+	* gcc.target/powerpc/fold-vec-splat-floatdouble.c: Likewise.
+	* gcc.target/powerpc/fold-vec-splat-longlong.c: Likewise.
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c: Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c: Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c: Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c:
+	Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c: Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_xst-char.c: Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_xst-double.c: Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_xst-float.c: Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_xst-int.c: Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c: Likewise.
+	* gcc.target/powerpc/fold-vec-store-vec_xst-short.c: Likewise.
+	* gcc.target/powerpc/lvsl-lvsr.c: Likewise.
+	* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Likewise.
+
+2021-07-13  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/vec-splati-runnable.c: Run test with -O2
+	optimization.  Do not check what XXSPLTIDP generates if the value
+	is undefined.
+
 2021-07-12  Patrick Palka  <ppalka@redhat.com>
 
 	PR c++/79501
diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index df7fb1791ad..beaba0fb75c 100644
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,10 @@
+2021-07-13  Jakub Jelinek  <jakub@redhat.com>
+	    Florian Weimer  <fweimer@redhat.com>
+
+	* config/linux/sem.h: Don't include limits.h.
+	(SEM_WAIT): Define to -__INT_MAX__ - 1 instead of INT_MIN.
+	* config/linux/affinity.c: Include limits.h.
+
 2021-07-01  Jakub Jelinek  <jakub@redhat.com>
 
 	PR middle-end/94366
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index d676ed3b91f..f00ea64569a 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,14 @@
+2021-07-13  Jonathan Wakely  <jwakely@redhat.com>
+
+	PR c++/101361
+	* include/std/string_view (ends_with): Use traits_type::compare
+	directly.
+
+2021-07-13  Jonathan Wakely  <jwakely@redhat.com>
+
+	* include/std/string_view: Only include <bits/ranges_base.h>
+	once, and only for C++20 and later.
+
 2021-07-12  Jonathan Wakely  <jwakely@redhat.com>
 
 	PR libstdc++/101411