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* [gcc r12-6176] Rotate ChangeLog files - part 1 - add ChangeLog-2021.
@ 2022-01-03 9:19 Jakub Jelinek
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From: Jakub Jelinek @ 2022-01-03 9:19 UTC (permalink / raw)
To: gcc-cvs, libstdc++-cvs
https://gcc.gnu.org/g:d04ae83244d346b95c36c2e3d39918548310f142
commit r12-6176-gd04ae83244d346b95c36c2e3d39918548310f142
Author: Jakub Jelinek <jakub@redhat.com>
Date: Mon Jan 3 10:18:16 2022 +0100
Rotate ChangeLog files - part 1 - add ChangeLog-2021.
2022-01-03 Jakub Jelinek <jakub@redhat.com>
gcc/
* ChangeLog-2021: Rotate ChangeLog. New file.
gcc/ada/
* ChangeLog-2021: Rotate ChangeLog. New file.
gcc/cp/
* ChangeLog-2021: Rotate ChangeLog. New file.
gcc/d/
* ChangeLog-2021: Rotate ChangeLog. New file.
gcc/fortran/
* ChangeLog-2021: Rotate ChangeLog. New file.
gcc/testsuite/
* ChangeLog-2021: Rotate ChangeLog. New file.
libgfortran/
* ChangeLog-2021: Rotate ChangeLog. New file.
libstdc++-v3/
* ChangeLog-2021: Rotate ChangeLog. New file.
Diff:
---
gcc/ChangeLog-2021 | 35692 +++++++++++++++++++++++++++++++++++++++++
gcc/ada/ChangeLog-2021 | 12135 ++++++++++++++
gcc/cp/ChangeLog-2021 | 5512 +++++++
gcc/d/ChangeLog-2021 | 1068 ++
gcc/fortran/ChangeLog-2021 | 2563 +++
gcc/testsuite/ChangeLog-2021 | 20646 ++++++++++++++++++++++++
libgfortran/ChangeLog-2021 | 384 +
libstdc++-v3/ChangeLog-2021 | 9013 +++++++++++
8 files changed, 87013 insertions(+)
diff --git a/gcc/ChangeLog-2021 b/gcc/ChangeLog-2021
new file mode 100644
index 00000000000..3d36cb70da3
--- /dev/null
+++ b/gcc/ChangeLog-2021
@@ -0,0 +1,35692 @@
+2021-12-30 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/103756
+ * regrename.c (find_rename_reg): Test noop_move_p on the first
+ non-debug insn in the chain rather than on the first insn.
+
+2021-12-30 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/103808
+ * emit-rtl.c (gen_rtx_REG_offset): Use gen_raw_REG instead of
+ gen_rtx_REG.
+
+2021-12-30 Martin Liska <mliska@suse.cz>
+
+ * doc/cpp.texi: Add missing dash for argument.
+
+2021-12-30 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/103012
+ * config/i386/i386-c.c (ix86_pragma_target_parse): Perform
+ cpp_define/cpp_undef calls with forced token locations
+ BUILTINS_LOCATION.
+ * config/arm/arm-c.c (arm_pragma_target_parse): Likewise.
+ * config/aarch64/aarch64-c.c (aarch64_pragma_target_parse): Likewise.
+ * config/s390/s390-c.c (s390_pragma_target_parse): Likewise.
+
+2021-12-30 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/103860
+ * shrink-wrap.c (try_shrink_wrapping): Make sure can_get_prologue is
+ called on pro even if nothing further is pushed into vec.
+
+2021-12-30 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ * loop-invariant.c (find_invariants_bb): Check profile count
+ before motion.
+ (find_invariants_body): Add argument.
+
+2021-12-29 Ian Lance Taylor <iant@golang.org>
+
+ PR go/103847
+ * godump.c (go_force_record_alignment): Name the alignment
+ field "_".
+
+2021-12-29 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/103742
+ * tree-ssa-dce.c (make_forwarders_with_degenerate_phis): If any phi
+ argument is not CONSTANT_CLASS_P or SSA_NAME and any arguments are
+ equal, change second from hash value to lowest dest_idx from the
+ edges which have equal argument and resort to ensure -fcompare-debug
+ stability.
+
+2021-12-29 Martin Liska <mliska@suse.cz>
+
+ * collect2.c (main): Add ld.mold.
+ * common.opt: Add -fuse-ld=mold.
+ * doc/invoke.texi: Document it.
+ * gcc.c (driver_handle_option): Handle -fuse-ld=mold.
+ * opts.c (common_handle_option): Likewise.
+
+2021-12-29 Uroš Bizjak <ubizjak@gmail.com>
+
+ * config/i386/sse.md (vec_pack<floatprefix>_float_<mode>):
+ Perform gen_avx512dq_float<floatunssuffix>v2div2sf2 into a
+ pseudo and emit move insn into operands[0].
+ (fix<fixunssuffix>_truncv2sfv2di2): Use lowpart_subreg
+ instead of simplify_gen_subreg.
+ (trunc<mode><pmov_dst_3_lower>2): Perform
+ gen_avx512vl_truncate<mode>v<ssescalarnum>qi2 into a
+ pseudo and emit move insn into operands[0].
+ (trunc<mode><pmov_dst_4_lower>2): Perform
+ gen_avx512vl_truncate<mode>v<ssescalarnum>hi2 into a
+ pseudo and emit move insn into operands[0].
+ (truncv2div2si2): Perform gen_avx512vl_truncatev2div2si2 into a
+ pseudo and emit move insn into operands[0].
+ (truncv8div8qi2): Perform gen_avx512f_truncatev8div16qi2 into a
+ pseudo and emit move insn into operands[0].
+ (<any_extend:insn>v8qiv8hi2): Use lowpart_subreg
+ instead of simplify_gen_subreg.
+ (<any_extend:insn>v8qiv8si2): Ditto.
+ (<any_extend:insn>v4qiv4si2): Ditto.
+ (<any_extend:insn>v4hiv4si2): Ditto.
+ (<any_extend:insn>v8qiv8di2): Ditto.
+ (<any_extend:insn>v4qiv4di2): Ditto.
+ (<any_extend:insn>v2qiv2di2): Ditto.
+ (<any_extend:insn>v4hiv4di2): Ditto.
+ (<any_extend:insn>v2hiv2di2): Ditto.
+ (<any_extend:insn>v2siv2di2): Ditto.
+
+2021-12-29 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ PR tree-optimization/103793
+ * tree-ssa-loop-split.c (fix_loop_bb_probability): New function.
+ (split_loop): Use multiply to scale loop1's exit probability.
+ (do_split_loop_on_cond): Call fix_loop_bb_probability.
+
+2021-12-28 Jason Merrill <jason@redhat.com>
+
+ PR c++/99968
+ * tree.c (verify_type): Allow enumerator with BOOLEAN_TYPE.
+
+2021-12-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/103813
+ * fold-const.c (fold_truth_andor_1): Punt of const_binop LSHIFT_EXPR
+ or RSHIFT_EXPR returns NULL. Formatting fix.
+
+2021-12-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/103837
+ * loop-invariant.c (can_move_invariant_reg): Ignore DEBUG_INSNs in
+ the decisions whether to return false or continue and right before
+ returning true reset those debug insns that previously caused
+ returning false.
+
+2021-12-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/103838
+ * optabs.c (expand_doubleword_mod, expand_doubleword_divmod): Only
+ check newly added insns for CALL_P, not the last insn of previous
+ code.
+
+2021-12-28 Martin Liska <mliska@suse.cz>
+
+ PR driver/103465
+ * opts.c (finish_options): More part of diagnostics to ...
+ (diagnose_options): ... here. Call the function from both
+ finish_options and process_options.
+ * opts.h (diagnose_options): Declare.
+ * toplev.c (process_options): Call diagnose_options.
+
+2021-12-28 Martin Liska <mliska@suse.cz>
+
+ * doc/contrib.texi: Replace http:// with https.
+ * doc/contribute.texi: Likewise.
+ * doc/extend.texi: Likewise.
+ * doc/gccint.texi: Likewise.
+ * doc/gnu.texi: Likewise.
+ * doc/implement-c.texi: Likewise.
+ * doc/implement-cxx.texi: Likewise.
+ * doc/include/fdl.texi: Likewise.
+ * doc/include/gpl_v3.texi: Likewise.
+ * doc/install.texi: Likewise.
+ * doc/invoke.texi: Likewise.
+ * doc/passes.texi: Likewise.
+ * doc/service.texi: Likewise.
+ * doc/sourcebuild.texi: Likewise.
+ * doc/standards.texi: Likewise.
+
+2021-12-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/103842
+ * config/i386/mmx.md (divv2sf3): Use force_reg on op1. Always perform
+ divv4sf3 into a pseudo and emit_move_insn into operands[0].
+
+2021-12-27 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa-protos.h: Delete
+ pa_maybe_emit_compare_and_swap_exchange_loop() declaration.
+ * config/pa/pa.c (pa_expand_compare_and_swap_loop): Delete.
+ (pa_maybe_emit_compare_and_swap_exchange_loop): Delete.
+ * config/pa/pa.md (atomic_storeq): Use __sync_lock_test_and_set
+ instead of pa_maybe_emit_compare_and_swap_exchange_loop.
+ (atomic_storehi, atomic_storesi, atomic_storedi): Likewise.
+
+2021-12-27 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/103762
+ * config/i386/constraints.md (BM): New constraint.
+ * config/i386/i386.md (m): New mode attribute.
+ Replace the 'm' constraint on <general_operand> with the '<m>'
+ constraint.
+ Replace the 'm' constraint on x86_64_general_operand with the
+ 'BM' constraint.
+
+2021-12-26 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/103785
+ * config/i386/i386.md: Swap operand order in comments and check
+ AX input in any_mul_highpart peepholes.
+
+2021-12-24 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ PR target/103797
+ * config/i386/mmx.md (divv2sf3): New instruction pattern.
+
+2021-12-24 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.c (darwin_override_options): Make a comment
+ more inclusive.
+
+2021-12-24 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config.gcc: Emit L2_MAX_OFILE_ALIGNMENT with suitable
+ values for the host.
+ * config/darwin.c (darwin_emit_common): Error for alignment
+ values > 32768.
+ * config/darwin.h (MAX_OFILE_ALIGNMENT): Rework to use the
+ configured L2_MAX_OFILE_ALIGNMENT.
+
+2021-12-24 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.c (darwin_override_options): When checking for the
+ flag-reorder-and-partition case, also check that it is set on.
+
+2021-12-24 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.h (OBJECT_FORMAT_MACHO): New.
+
+2021-12-23 Roger Sayle <roger@nextmovesoftware.com>
+ Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/103773
+ * config/i386/i386.md (*mov<mode>_and): New define_insn for
+ writing a zero to memory using AND.
+ (*mov<mode>_or): Extend to allow memory destination and HImode.
+ (*movdi_internal): Remove -Oz push/pop optimization from here.
+ (*movsi_internal): Likewise.
+ (peephole2): Perform -Oz push/pop optimization here, only for
+ register destinations, values other than zero, and in functions
+ that don't used the red zone.
+ (peephole2): With -Oz, convert writes of 0 or -1 to memory into
+ their clobber forms, i.e. *mov<mode>_and and *mov<mode>_or resp.
+
+2021-12-23 konglin1 <lingling.kong@intel.com>
+
+ * config/i386/avx512bf16intrin.h (_mm_cvtsbh_ss): Add new intrinsic.
+ (_mm512_cvtpbh_ps): Likewise.
+ (_mm512_maskz_cvtpbh_ps): Likewise.
+ (_mm512_mask_cvtpbh_ps): Likewise.
+ * config/i386/avx512bf16vlintrin.h (_mm_cvtness_sbh): Likewise.
+ (_mm_cvtpbh_ps): Likewise.
+ (_mm256_cvtpbh_ps): Likewise.
+ (_mm_maskz_cvtpbh_ps): Likewise.
+ (_mm256_maskz_cvtpbh_ps): Likewise.
+ (_mm_mask_cvtpbh_ps): Likewise.
+ (_mm256_mask_cvtpbh_ps): Likewise.
+
+2021-12-23 Feng Xue <fxue@os.amperecomputing.com>
+
+ PR ipa/103786
+ * tree.c (verify_type): Fix typo.
+
+2021-12-23 liuhongt <hongtao.liu@intel.com>
+
+ PR target/103750
+ * config/i386/sse.md
+ (*<avx512>_cmp<V48H_AVX512VL:mode>3_zero_extend<SWI248x:mode>):
+ New pre_reload define_insn_and_split.
+ (*<avx512>_cmp<VI12_AVX512VL:mode>3_zero_extend<SWI248x:mode>):
+ Ditto.
+ (*<avx512>_ucmp<VI12_AVX512VL:mode>3_zero_extend<SWI248x:mode>):
+ Ditto.
+ (*<avx512>_ucmp<VI48_AVX512VL:mode>3_zero_extend<SWI248x:mode>):
+ Ditto.
+ (*<avx512>_cmp<V48H_AVX512VL:mode>3_zero_extend<SWI248x:mode>_2):
+ Ditto.
+ (*<avx512>_cmp<VI12_AVX512VL:mode>3_zero_extend<SWI248x:mode>_2):
+ Ditto.
+ (*<avx512>_ucmp<VI12_AVX512VL:mode>3_zero_extend<SWI248x:mode>_2):
+ Ditto.
+ (*<avx512>_ucmp<VI48_AVX512VL:mode>3_zero_extend<SWI248x:mode>_2):
+ Ditto.
+
+2021-12-22 Murray Steele <murray.steele@arm.com>
+
+ * config.gcc (arm*-*-*): Add arm-mve-builtins.o to extra_objs.
+ * config/arm/arm-c.c (arm_pragma_arm): Handle "#pragma GCC arm".
+ (arm_register_target_pragmas): Register it.
+ * config/arm/arm-protos.h: (arm_mve::arm_handle_mve_types_h): New
+ prototype.
+ * config/arm/arm_mve_types.h: Replace MVE type definitions with
+ new pragma.
+ * config/arm/t-arm: (arm-mve-builtins.o): New target rule.
+ * config/arm/arm-mve-builtins.cc: New file.
+ * config/arm/arm-mve-builtins.def: New file.
+ * config/arm/arm-mve-builtins.h: New file.
+
+2021-12-22 Murray Steele <murray.steele@arm.com>
+
+ * config/arm/arm-builtins.c (enum arm_type_qualifiers): Move to
+ arm_builtins.h.
+ (enum arm_simd_type): Move to arm-builtins.h.
+ (struct arm_simd_type_info): Move to arm-builtins.h.
+ * config/arm/arm-builtins.h (enum arm_simd_type): Move from
+ arm-builtins.c.
+ (enum arm_type_qualifiers): Move from arm-builtins.c.
+ (struct arm_simd_type_info): Move from arm-builtins.c.
+
+2021-12-22 Martin Liska <mliska@suse.cz>
+
+ * doc/extend.texi: Unify all function declarations in examples
+ where some miss trailing ';'.
+
+2021-12-22 Martin Liska <mliska@suse.cz>
+
+ * doc/extend.texi: Unify all function declarations in examples
+ where some miss trailing ';'.
+
+2021-12-22 Martin Liska <mliska@suse.cz>
+
+ * doc/extend.texi: Unify all function declarations in examples
+ where some miss trailing ';'.
+
+2021-12-22 Martin Liska <mliska@suse.cz>
+
+ * doc/extend.texi: Use uppercase letters for SSEx.
+
+2021-12-21 Jiang Haochen <haochen.jiang@intel.com>
+
+ * config/i386/bmiintrin.h (_tzcnt_u16): New intrinsic.
+ (_andn_u32): Ditto.
+ (_andn_u64): Ditto.
+
+2021-12-21 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ * tree-ssa-loop-im.c (bb_colder_than_loop_preheader): New
+ function.
+ (get_coldest_out_loop): New function.
+ (determine_max_movement): Use get_coldest_out_loop.
+ (move_computations_worker): Adjust and fix iteration udpate.
+ (class ref_in_loop_hot_body): New functor.
+ (ref_in_loop_hot_body::operator): New.
+ (can_sm_ref_p): Use for_all_locs_in_loop.
+ (fill_coldest_and_hotter_out_loop): New.
+ (tree_ssa_lim_finalize): Free coldest_outermost_loop and
+ hotter_than_inner_loop.
+ (loop_invariant_motion_in_fun): Call fill_coldest_and_hotter_out_loop.
+
+2021-12-21 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ * tree-ssa-loop-split.c (split_loop): Fix incorrect
+ profile_count and probability.
+ (do_split_loop_on_cond): Likewise.
+
+2021-12-21 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ PR middle-end/103270
+ * predict.c (predict_extra_loop_exits): Add loop parameter.
+ (predict_loops): Call with loop argument.
+
+2021-12-21 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ * config/rs6000/altivec.md (altivec_vaddu<VI_char>s): Replace
+ UNSPEC_VADDU with us_plus.
+ (altivec_vadds<VI_char>s): Replace UNSPEC_VADDS with ss_plus.
+ (altivec_vsubu<VI_char>s): Replace UNSPEC_VSUBU with us_minus.
+ (altivec_vsubs<VI_char>s): Replace UNSPEC_VSUBS with ss_minus.
+ (altivec_abss_<mode>): Likewise.
+
+2021-12-20 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/103772
+ * config/i386/sse.md (<sse2p4_1>_pinsr<ssemodesuffix>): Add
+ earlyclobber to (x,x,x,i) alternative.
+ (<sse2p4_1>_pinsr<ssemodesuffix> peephole2): Remove.
+ (<sse2p4_1>_pinsr<ssemodesuffix> splitter): Use output
+ operand as a temporary register. Split after reload_completed.
+
+2021-12-20 Roger Sayle <roger@nextmovesoftware.com>
+ Uroš Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (any_mul_highpart): New code iterator.
+ (sgnprefix, s): Add attribute support for [su]mul_highpart.
+ (<s>mul<mode>3_highpart): Delete expander.
+ (<s>mul<mode>3_highpart, <s>mulsi32_highpart_zext):
+ New define_insn patterns.
+ (define_peephole2): Tweak the register allocation for the above
+ instructions after reload.
+
+2021-12-20 Joel Sherrill <joel@rtems.org>
+
+ * config.gcc: Obsolete m32c-*-rtems* target.
+
+2021-12-20 Martin Liska <mliska@suse.cz>
+
+ * opts.c (default_options_optimization): Support -Oz in -Ox option hints.
+
+2021-12-20 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103669
+ * ipa-modref.c (modref_eaf_analysis::analyze_ssa_name): Add deferred
+ parameter.
+ (modref_eaf_analysis::propagate): Use it.
+
+2021-12-20 liuhongt <hongtao.liu@intel.com>
+
+ PR target/98468
+ * config/i386/sse.md (*bit_and_float_vector_all_ones): New
+ pre-reload splitter.
+
+2021-12-19 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103766
+ * ipa-modref.c (modref_merge_call_site_flags): Fix early exit condition
+
+2021-12-19 Patrick Palka <ppalka@redhat.com>
+
+ * print-tree.c (print_node) <case tcc_declaration>: Dump
+ DECL_LANG_FLAG_8.
+
+2021-12-19 Andrew Pinski <apinski@marvell.com>
+
+ * tree-ssa-phiopt.c (gimple_simplify_phiopt): Annotate the
+ new sequence with the location of the conditional statement.
+
+2021-12-18 Roger Sayle <roger@nextmovesoftware.com>
+ Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/103611
+ * config/i386/i386.md (any_or_plus): New code iterator.
+ (define_split): Split (HI<<32)|zext(LO) into piece-wise
+ move instructions on !TARGET_64BIT.
+ * config/i386/sse.md (*vec_extractv4si_0_zext_sse4):
+ Restrict to TARGET_64BIT.
+
+2021-12-18 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR target/32803
+ * common.opt (Oz): New command line option.
+ * doc/invoke.texi: Document the new -Oz option.
+ * lto-wrapper.c (merge_and_complain, append_compiler_options):
+ Treat OPT_Oz as synonymous with OPT_Os.
+ * optc-save-gen.awk: Increase maximum value of optimize_size to 2.
+ * opts.c (default_options_optimization) [OPT_Oz]: Handle OPT_Oz
+ just like OPT_Os, except set opt->x_optimize_size to 2.
+ (common_handle_option): Skip OPT_Oz just like OPT_Os.
+ * config/i386/i386.md (*movdi_internal): Use a push/pop sequence
+ for suitable SImode TYPE_IMOV moves when optimize_size > 1.
+ (*movsi_internal): Likewise.
+
+2021-12-18 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ PR tree-optimization/103759
+ * tree-object-size.c (unknown, initval): Remove functions.
+ (size_unknown, size_initval, size_unknown_p): Operate directly
+ on trees.
+
+2021-12-18 François-Xavier Coudert <fxcoudert@gcc.gnu.org>
+
+ * config/darwin-driver.c: Make version code more future-proof.
+ * config.gcc: Homogeneize darwin versions.
+ * configure.ac: Homogeneize darwin versions.
+ * configure: Regenerate.
+
+2021-12-17 Marek Polacek <polacek@redhat.com>
+
+ PR c/103649
+ * attribs.c (handle_ignored_attributes_option): Create the fake
+ attribute with max_length == -2.
+ (attribute_ignored_p): New overloads.
+ * attribs.h (attribute_ignored_p): Declare them.
+ * tree-core.h (struct attribute_spec): Document that max_length
+ can be -2.
+
+2021-12-17 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/103624
+ * config/rs6000/rs6000-builtins.def (__builtin_darn): Expand to
+ darn_64_di. Add {32bit} attribute. Return long.
+ (__builtin_darn_32): Expand to darn_32_di. Add {32bit} attribute.
+ Return long.
+ (__builtin_darn_raw): Expand to darn_raw_di. Add {32bit} attribute.
+ Return long.
+ * config/rs6000/rs6000-call.c (rs6000_expand_builtin): Expand the darn
+ builtins to the _si variants for -m32.
+ * config/rs6000/rs6000.md (UNSPECV_DARN_32, UNSPECV_DARN_RAW): Delete.
+ (UNSPECV_DARN): Update comment.
+ (darn_32, darn_raw, darn): Delete.
+ (darn_32_<mode>, darn_64_<mode>, darn_raw_<mode> for GPR): New.
+ (@darn<mode> for GPR): New.
+
+2021-12-17 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-overload.def (__builtin_vec_promote): Add second
+ argument.
+
+2021-12-17 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/103744
+ * tree-vect-stmts.c (vectorizable_load): Handle multi-vector
+ SLP gather loads.
+
+2021-12-17 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Rename to -fstack-protector.
+
+2021-12-17 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Fix spelling issues.
+
+2021-12-17 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/103741
+ * tree-vect-stmts.c (vectorizable_operation): Check for boolean.
+
+2021-12-17 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin-driver.c (darwin_driver_init): Exit from the
+ option handling early if the command line is definitely enpty.
+ * config/darwin.h (SUBTARGET_DRIVER_SELF_SPECS): Remove
+ setting for the default content of weak_reference_mismatches.
+
+2021-12-17 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/rs6000/darwin.h: Drop trailing _x from the
+ builtin_decls array name.
+
+2021-12-17 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/100738
+ * config/i386/sse.md (*avx_cmp<mode>3_lt, *avx_cmp<mode>3_ltint):
+ Remove MEM_P restriction and add force_reg for operands[2].
+ (*avx_cmp<mode>3_ltint_not): Add new define_insn_and_split.
+
+2021-12-17 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ * builtins.def (BUILT_IN_DYNAMIC_OBJECT_SIZE): New builtin.
+ * tree-object-size.h: Move object size type bits enum from
+ tree-object-size.c and add new value OST_DYNAMIC.
+ * builtins.c (expand_builtin, fold_builtin_2): Handle it.
+ (fold_builtin_object_size): Handle new builtin and adjust for
+ change to compute_builtin_object_size.
+ * tree-object-size.c: Include builtins.h.
+ (compute_builtin_object_size): Adjust.
+ (early_object_sizes_execute_one,
+ dynamic_object_sizes_execute_one): New functions.
+ (object_sizes_execute): Rename insert_min_max_p argument to
+ early. Handle BUILT_IN_DYNAMIC_OBJECT_SIZE and call the new
+ functions.
+ * doc/extend.texi (__builtin_dynamic_object_size): Document new
+ builtin.
+
+2021-12-17 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ * tree-object-size.h (compute_builtin_object_size): Return tree
+ instead of HOST_WIDE_INT.
+ * builtins.c (fold_builtin_object_size): Adjust.
+ * gimple-fold.c (gimple_fold_builtin_strncat): Likewise.
+ * ubsan.c (instrument_object_size): Likewise.
+ * tree-object-size.c (object_size): New structure.
+ (object_sizes): Change type to vec<object_size>.
+ (initval): New function.
+ (unknown): Use it.
+ (size_unknown_p, size_initval, size_unknown): New functions.
+ (object_sizes_unknown_p): Use it.
+ (object_sizes_get): Return tree.
+ (object_sizes_initialize): Rename from object_sizes_set_force
+ and set VAL parameter type as tree. Add new parameter WHOLEVAL.
+ (object_sizes_set): Set VAL parameter type as tree and adjust
+ implementation. Add new parameter WHOLEVAL.
+ (size_for_offset): New function.
+ (decl_init_size): Adjust comment.
+ (addr_object_size): Change PSIZE parameter to tree and adjust
+ implementation. Add new parameter PWHOLESIZE.
+ (alloc_object_size): Return tree.
+ (compute_builtin_object_size): Return tree in PSIZE.
+ (expr_object_size, call_object_size, unknown_object_size):
+ Adjust for object_sizes_set change.
+ (merge_object_sizes): Drop OFFSET parameter and adjust
+ implementation for tree change.
+ (plus_stmt_object_size): Call collect_object_sizes_for directly
+ instead of merge_object_size and call size_for_offset to get net
+ size.
+ (cond_expr_object_size, collect_object_sizes_for,
+ object_sizes_execute): Adjust for change of type from
+ HOST_WIDE_INT to tree.
+ (check_for_plus_in_loops_1): Likewise and skip non-positive
+ offsets.
+
+2021-12-17 Jason Merrill <jason@redhat.com>
+
+ PR c++/103681
+ * common.opt (fabi-version): Add v17.
+
+2021-12-16 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/103571
+ * config/i386/i386.h (VALID_AVX256_REG_MODE): Add V16HFmode.
+ (VALID_AVX256_REG_OR_OI_VHF_MODE): Replace with ...
+ (VALID_AVX256_REG_OR_OI_MODE): ... this. Remove V16HFmode.
+ (VALID_AVX512F_SCALAR_MODE): Remove HImode and HFmode.
+ (VALID_AVX512FP16_SCALAR_MODE): New.
+ (VALID_AVX512F_REG_MODE): Add V32HFmode.
+ (VALID_SSE2_REG_MODE): Add V8HFmode, V4HFmode and V2HFmode.
+ (VALID_SSE2_REG_VHF_MODE): Remove.
+ (VALID_INT_MODE_P): Add V2HFmode.
+ * config/i386/i386.c (function_arg_advance_64):
+ Remove explicit mention of V16HFmode and V32HFmode.
+ (ix86_hard_regno_mode_ok): Remove explicit mention of XImode
+ and V32HFmode, use VALID_AVX512F_REG_OR_XI_MODE instead.
+ Use VALID_AVX512FP_SCALAR_MODE for TARGET_aVX512FP16.
+ Use VALID_AVX256_REG_OR_OI_MODE instead of
+ VALID_AVX256_REG_OR_OI_VHF_MODE and VALID_SSE2_REG_MODE instead
+ of VALID_SSE2_REG_VHF_MODE.
+ (ix86_set_reg_reg_cost): Remove usge of VALID_AVX512FP16_REG_MODE.
+ (ix86_vector_mode_supported): Ditto.
+
+2021-12-16 Martin Liska <mliska@suse.cz>
+
+ PR c++/103696
+ * attribs.c (decl_attributes): Check if
+ target_option_current_node is changed.
+
+2021-12-16 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Add missing dash.
+
+2021-12-16 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-c.c (resolution): New enum.
+ (resolve_vec_mul): New function.
+ (resolve_vec_cmpne): Likewise.
+ (resolve_vec_adde_sube): Likewise.
+ (resolve_vec_addec_subec): Likewise.
+ (resolve_vec_splats): Likewise.
+ (resolve_vec_extract): Likewise.
+ (resolve_vec_insert): Likewise.
+ (resolve_vec_step): Likewise.
+ (find_instance): Likewise.
+ (altivec_resolve_overloaded_builtin): Many cleanups. Call factored-out
+ functions. Move variable declarations closer to uses. Add commentary.
+ Remove unnecessary levels of braces. Avoid use of gotos. Change
+ misleading variable names. Use switches over if-else-if chains.
+
+2021-12-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ PR target/103729
+ * config/aarch64/aarch64-simd.md (aarch64_movv8di): Allow big endian
+ targets to move V8DI.
+
+2021-12-16 Tobias Burnus <tobias@codesourcery.com>
+
+ PR driver/103644
+ * gcc.c (check_offload_target_name): Add 'default' and 'disable'
+ to the candidate list.
+
+2021-12-15 Iain Sandoe <iain@sandoe.co.uk>
+
+ * configure: Regenerate.
+
+2021-12-15 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/nvptx/nvptx-opts.h (ptx_isa): PTX_ISA_SM75 and PTX_ISA_SM80
+ ISA levels.
+ * config/nvptx/nvptx.opt: Add sm_75 and sm_80 to -misa.
+ * config/nvptx/nvptx.h (TARGET_SM75, TARGET_SM80):
+ New helper macros to conditionalize functionality on target ISA.
+ * config/nvptx/nvptx-c.c (nvptx_cpu_cpp_builtins): Add __PTX_SM__
+ support for the new ISA levels.
+ * config/nvptx/nvptx.c (nvptx_file_start): Add support for TARGET_SM75
+ and TARGET_SM80.
+ * config/nvptx/nvptx.md (define_c_enum "unspec"): New UNSPEC_TANH.
+ (define_mode_iterator HSFM): New iterator for HFmode and SFmode.
+ (exp2hf2): New define_insn controlled by TARGET_SM75.
+ (tanh<mode>2): New define_insn controlled by TARGET_SM75.
+ (sminhf3, smaxhf3): New define_isnns controlled by TARGET_SM80.
+
+2021-12-15 Tom de Vries <tdevries@suse.de>
+
+ * config/nvptx/nvptx-opts.h (enum ptx_version): Add PTX_VERSION_7_0.
+ * config/nvptx/nvptx.c (nvptx_file_start): Handle TARGET_PTX_7_0.
+ * config/nvptx/nvptx.h (TARGET_PTX_7_0): New macro.
+ * config/nvptx/nvptx.opt (ptx_version): Add 7.0.
+
+2021-12-15 Richard Sandiford <richard.sandiford@arm.com>
+ Tamar Christina <tamar.christina@arm.com>
+
+ PR target/103094
+ * config/aarch64/aarch64.c (aarch64_short_vector_p): Return false
+ for structure modes, rather than ignoring the type in that case.
+
+2021-12-15 Tamar Christina <tamar.christina@arm.com>
+
+ PR rtl-optimization/103350
+ * ree.c (add_removable_extension): Don't stop at first definition but
+ inspect all.
+
+2021-12-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/103619
+ * dwarf2cfi.c (dwf_cfa_reg): Remove gcc_assert.
+ (operator==, operator!=): New overloaded operators.
+ (dwarf2out_frame_debug_adjust_cfa, dwarf2out_frame_debug_cfa_offset,
+ dwarf2out_frame_debug_expr): Compare vars with cfa_reg type directly
+ with REG rtxes rather than with dwf_cfa_reg results on those REGs.
+ (create_cie_data): Use stack_pointer_rtx instead of
+ gen_rtx_REG (Pmode, STACK_POINTER_REGNUM).
+ (execute_dwarf2_frame): Use hard_frame_pointer_rtx instead of
+ gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM).
+
+2021-12-15 Martin Liska <mliska@suse.cz>
+
+ PR target/103661
+ * config/i386/i386-builtins.c (fold_builtin_cpu): Compare to 0
+ as API expects that non-zero values are returned (do that
+ it mask == 31).
+ For "avx512vbmi2" argument, we return now 1 << 31, which is a
+ negative integer value.
+
+2021-12-15 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/101796
+ * config/i386/predicates.md (const_vector_operand):
+ Add new predicate.
+ * config/i386/sse.md(<insn><mode>3<mask_name>):
+ Add new define_split below.
+
+2021-12-15 Michael Meissner <meissner@the-meissners.org>
+
+ * config/rs6000/rs6000.md (UNSPEC_XXSPLTIDP_CONST): New unspec.
+ (UNSPEC_XXSPLTIW_CONST): New unspec.
+ (movsf_hardfloat): Add support for generating XXSPLTIDP.
+ (mov<mode>_hardfloat32): Likewise.
+ (mov<mode>_hardfloat64): Likewise.
+ (xxspltidp_<mode>_internal): New insns.
+ (xxspltiw_<mode>_internal): New insns.
+ (splitters for SF/DFmode): Add new splitters for XXSPLTIDP.
+
+2021-12-15 Michael Meissner <meissner@the-meissners.org>
+
+ * config/rs6000/predicates.md (easy_fp_constant): Add support for
+ generating XXSPLTIDP.
+ (vsx_prefixed_constant): Likewise.
+ (easy_vector_constant): Likewise.
+ * config/rs6000/rs6000-protos.h (constant_generates_xxspltidp):
+ New declaration.
+ * config/rs6000/rs6000.c (output_vec_const_move): Add support for
+ generating XXSPLTIDP.
+ (prefixed_xxsplti_p): Likewise.
+ (constant_generates_xxspltidp): New function.
+ * config/rs6000/rs6000.opt (-msplat-float-constant): New debug option.
+
+2021-12-15 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/constraints.md (eP): Update comment.
+ * config/rs6000/predicates.md (easy_fp_constant): Add support for
+ generating XXSPLTIW.
+ (vsx_prefixed_constant): New predicate.
+ (easy_vector_constant): Add support for
+ generating XXSPLTIW.
+ * config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
+ declaration.
+ (constant_generates_xxspltiw): Likewise.
+ * config/rs6000/rs6000.c (xxspltib_constant_p): Generate XXSPLTIW
+ if possible instead of XXSPLTIB and sign extending the constant.
+ (output_vec_const_move): Add support for XXSPLTIW.
+ (prefixed_xxsplti_p): New function.
+ (constant_generates_xxspltiw): New function.
+ * config/rs6000/rs6000.md (prefixed attribute): Add support to
+ mark XXSPLTI* instructions as being prefixed.
+ * config/rs6000/rs6000.opt (-msplat-word-constant): New debug
+ switch.
+ * config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
+ generating XXSPLTIW or XXSPLTIDP.
+ (vsx_mov<mode>_32bit): Likewise.
+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
+ eP constraint.
+
+2021-12-15 Michael Meissner <meissner@the-meissners.org>
+
+ * config/rs6000/constraints.md (eQ): New constraint.
+ * config/rs6000/predicates.md (easy_fp_constant): Add support for
+ generating the LXVKQ instruction.
+ (easy_vector_constant_ieee128): New predicate.
+ (easy_vector_constant): Add support for generating the LXVKQ
+ instruction.
+ * config/rs6000/rs6000-protos.h (constant_generates_lxvkq): New
+ declaration.
+ * config/rs6000/rs6000.c (output_vec_const_move): Add support for
+ generating LXVKQ.
+ (constant_generates_lxvkq): New function.
+ * config/rs6000/rs6000.opt (-mieee128-constant): New debug
+ option.
+ * config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
+ generating LXVKQ.
+ (vsx_mov<mode>_32bit): Likewise.
+ * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
+ eQ constraint.
+
+2021-12-15 Michael Meissner <meissner@the-meissners.org>
+
+ * config/rs6000/rs6000-protos.h (VECTOR_128BIT_BITS): New macro.
+ (VECTOR_128BIT_BYTES): Likewise.
+ (VECTOR_128BIT_HALF_WORDS): Likewise.
+ (VECTOR_128BIT_WORDS): Likewise.
+ (VECTOR_128BIT_DOUBLE_WORDS): Likewise.
+ (vec_const_128bit_type): New structure type.
+ (vec_const_128bit_to_bytes): New declaration.
+ * config/rs6000/rs6000.c (constant_int_to_128bit_vector): New
+ helper function.
+ (constant_fp_to_128bit_vector): New helper function.
+ (vec_const_128bit_to_bytes): New function.
+
+2021-12-15 Alexandre Oliva <oliva@adacore.com>
+
+ PR target/100518
+ * builtins.c (try_store_by_multiple_pieces): Drop address
+ conversion to ptr_mode.
+
+2021-12-15 Alexandre Oliva <oliva@adacore.com>
+
+ PR middle-end/100843
+ * builtins.c (try_store_by_multiple_pieces): Fail if min_len
+ is greater than max_len.
+
+2021-12-14 liuhongt <hongtao.liu@intel.com>
+
+ PR target/103682
+ * tree-ssa-ccp.c (optimize_atomic_bit_test_and): Check
+ is_gimple_assign before gimple_assign_rhs_code.
+
+2021-12-14 Sören Tempel <soeren@soeren-tempel.net>
+
+ * ginclude/stddef.h (__DEFINED_ptrdiff_t): Add support for musl
+ libc typedef macro guard.
+ (__DEFINED_size_t): Ditto.
+ (__DEFINED_wchar_t): Ditto.
+
+2021-12-14 JoJo R <rjiejie@linux.alibaba.com>
+
+ * regrename.c (find_rename_reg): Return satisfied regno
+ if instruction is noop move.
+
+2021-12-14 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Rename
+ rs6000_builtin_decls_x to rs6000_builtin_decls.
+ (altivec_resolve_overloaded_builtin): Likewise. Also rename
+ rs6000_builtin_info_x to rs6000_builtin_info.
+ * config/rs6000/rs6000-call.c (rs6000_invalid_builtin): Rename
+ rs6000_builtin_info_x to rs6000_builtin_info.
+ (rs6000_builtin_is_supported): Likewise.
+ (rs6000_gimple_fold_mma_builtin): Likewise. Also rename
+ rs6000_builtin_decls_x to rs6000_builtin_decls.
+ (rs6000_gimple_fold_builtin): Rename rs6000_builtin_info_x to
+ rs6000_builtin_info.
+ (cpu_expand_builtin): Likewise.
+ (rs6000_expand_builtin): Likewise.
+ (rs6000_init_builtins): Likewise. Also rename rs6000_builtin_decls_x
+ to rs6000_builtin_decls.
+ (rs6000_builtin_decl): Rename rs6000_builtin_decls_x to
+ rs6000_builtin_decls.
+ * config/rs6000/rs6000-gen-builtins.c (write_decls): In generated code,
+ rename rs6000_builtin_decls_x to rs6000_builtin_decls, and rename
+ rs6000_builtin_info_x to rs6000_builtin_info.
+ (write_bif_static_init): In generated code, rename
+ rs6000_builtin_info_x to rs6000_builtin_info.
+ (write_init_bif_table): In generated code, rename
+ rs6000_builtin_decls_x to rs6000_builtin_decls, and rename
+ rs6000_builtin_info_x to rs6000_builtin_info.
+ (write_init_ovld_table): In generated code, rename
+ rs6000_builtin_decls_x to rs6000_builtin_decls.
+ (write_init_file): Likewise.
+ * config/rs6000/rs6000.c (rs6000_builtin_vectorized_function):
+ Likewise.
+ (rs6000_builtin_md_vectorized_function): Likewise.
+ (rs6000_builtin_reciprocal): Likewise.
+ (add_condition_to_bb): Likewise.
+ (rs6000_atomic_assign_expand_fenv): Likewise.
+
+2021-12-14 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-c.c (altivec_resolve_new_overloaded_builtin):
+ Remove forward declaration.
+ (rs6000_new_builtin_type_compatible): Rename to
+ rs6000_builtin_type_compatible.
+ (rs6000_builtin_type_compatible): Remove.
+ (altivec_resolve_overloaded_builtin): Remove.
+ (altivec_build_new_resolved_builtin): Rename to
+ altivec_build_resolved_builtin.
+ (altivec_resolve_new_overloaded_builtin): Rename to
+ altivec_resolve_overloaded_builtin. Remove static keyword. Adjust
+ called function names.
+ * config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): Remove
+ forward declaration.
+ (rs6000_gimple_fold_new_builtin): Likewise.
+ (rs6000_invalid_new_builtin): Rename to rs6000_invalid_builtin.
+ (rs6000_gimple_fold_builtin): Remove.
+ (rs6000_new_builtin_valid_without_lhs): Rename to
+ rs6000_builtin_valid_without_lhs.
+ (rs6000_new_builtin_is_supported): Rename to
+ rs6000_builtin_is_supported.
+ (rs6000_gimple_fold_new_mma_builtin): Rename to
+ rs6000_gimple_fold_mma_builtin.
+ (rs6000_gimple_fold_new_builtin): Rename to
+ rs6000_gimple_fold_builtin. Remove static keyword. Adjust called
+ function names.
+ (rs6000_expand_builtin): Remove.
+ (new_cpu_expand_builtin): Rename to cpu_expand_builtin.
+ (new_mma_expand_builtin): Rename to mma_expand_builtin.
+ (new_htm_spr_num): Rename to htm_spr_num.
+ (new_htm_expand_builtin): Rename to htm_expand_builtin. Change name
+ of called function.
+ (rs6000_expand_new_builtin): Rename to rs6000_expand_builtin. Remove
+ static keyword. Adjust called function names.
+ (rs6000_new_builtin_decl): Rename to rs6000_builtin_decl. Remove
+ static keyword.
+ (rs6000_builtin_decl): Remove.
+ * config/rs6000/rs6000-gen-builtins.c (write_decls): In gnerated code,
+ rename rs6000_new_builtin_is_supported to rs6000_builtin_is_supported.
+ * config/rs6000/rs6000-internal.h (rs6000_invalid_new_builtin): Rename
+ to rs6000_invalid_builtin.
+ * config/rs6000/rs6000.c (rs6000_new_builtin_vectorized_function):
+ Rename to rs6000_builtin_vectorized_function.
+ (rs6000_new_builtin_md_vectorized_function): Rename to
+ rs6000_builtin_md_vectorized_function.
+ (rs6000_builtin_vectorized_function): Remove.
+ (rs6000_builtin_md_vectorized_function): Remove.
+
+2021-12-14 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-builtin.def: Delete.
+ * config/rs6000/rs6000-call.c (builtin_compatibility): Delete.
+ (builtin_description): Delete.
+ (builtin_hash_struct): Delete.
+ (builtin_hasher): Delete.
+ (builtin_hash_table): Delete.
+ (builtin_hasher::hash): Delete.
+ (builtin_hasher::equal): Delete.
+ (rs6000_builtin_info_type): Delete.
+ (rs6000_builtin_info): Delete.
+ (bdesc_compat): Delete.
+ (bdesc_3arg): Delete.
+ (bdesc_4arg): Delete.
+ (bdesc_dst): Delete.
+ (bdesc_2arg): Delete.
+ (bdesc_altivec_preds): Delete.
+ (bdesc_abs): Delete.
+ (bdesc_1arg): Delete.
+ (bdesc_0arg): Delete.
+ (bdesc_htm): Delete.
+ (bdesc_mma): Delete.
+ (rs6000_overloaded_builtin_p): Delete.
+ (rs6000_overloaded_builtin_name): Delete.
+ (htm_spr_num): Delete.
+ (rs6000_builtin_is_supported_p): Delete.
+ (rs6000_gimple_fold_mma_builtin): Delete.
+ (gt-rs6000-call.h): Remove include directive.
+ * config/rs6000/rs6000-protos.h (rs6000_overloaded_builtin_p): Delete.
+ (rs6000_builtin_is_supported_p): Delete.
+ (rs6000_overloaded_builtin_name): Delete.
+ * config/rs6000/rs6000.c (rs6000_builtin_decls): Delete.
+ (rs6000_debug_reg_global): Remove reference to RS6000_BUILTIN_COUNT.
+ * config/rs6000/rs6000.h (rs6000_builtins): Delete.
+ (altivec_builtin_types): Delete.
+ (rs6000_builtin_decls): Delete.
+ * config/rs6000/t-rs6000 (TM_H): Don't add rs6000-builtin.def.
+
+2021-12-14 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-builtin-new.def: Rename to...
+ * config/rs6000/rs6000-builtins.def: ...this.
+ * config/rs6000/rs6000-gen-builtins.c: Adjust header commentary.
+ * config/rs6000/t-rs6000 (EXTRA_GTYPE_DEPS): Rename
+ rs6000-builtin-new.def to rs6000-builtins.def.
+ (rs6000-builtins.c): Likewise.
+
+2021-12-14 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Remove.
+ * config/rs6000/rs6000.h (altivec_overloaded_builtins): Remove.
+
+2021-12-14 Peter Bergner <bergner@linux.ibm.com>
+
+ PR target/103548
+ * config/rs6000/mma.md (UNSPEC_MMA_ASSEMBLE): Rename unspec from this...
+ (UNSPEC_VSX_ASSEMBLE): ...to this.
+ (UNSPECV_MMA_ASSEMBLE): New unspecv.
+ (vsx_assemble_pair): Use UNSPEC_VSX_ASSEMBLE.
+ (*vsx_assemble_pair): Likewise.
+ (mma_assemble_acc): Use UNSPECV_MMA_ASSEMBLE.
+ (*mma_assemble_acc): Likewise.
+ * config/rs6000/rs6000.c (rs6000_split_multireg_move): Handle
+ UNSPEC_VOLATILE. Use UNSPEC_VSX_ASSEMBLE and UNSPECV_MMA_ASSEMBLE.
+
+2021-12-14 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/103571
+ * config/i386/i386-expand.c (ix86_expand_vector_init_duplicate)
+ <case E_V8HFmode>: Implement for TARGET_SSE2.
+ <case E_V16HFmode>: Implement for TARGET_AVX.
+ <case E_V32HFmode>: Implement for TARGET_AVX512F.
+ (ix86_expand_vector_set_var): Handle V32HFmode
+ without TARGET_AVX512BW.
+ (ix86_expand_vector_extract)
+ <case E_V8HFmode>: Implement for TARGET_SSE2.
+ <case E_V16HFmode>: Implement for TARGET_AVX.
+ <case E_V32HFmode>: Implement for TARGET_AVX512BW.
+ (expand_vec_perm_broadcast_1) <case E_V8HFmode>: New.
+ * config/i386/sse.md (VI12HF_AVX512VL): Remove
+ TARGET_AVX512FP16 condition.
+ (V): Ditto.
+ (V_256_512): Ditto.
+ (avx_vbroadcastf128_<mode>): Use V_256H mode iterator.
+
+2021-12-14 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/darwin.h (SUBTARGET_INIT_BUILTINS): Remove
+ test for new_builtins_are_live and simplify.
+ * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Remove
+ dead function.
+ (altivec_resolve_overloaded_builtin): Remove test for
+ new_builtins_are_live and simplify.
+ * config/rs6000/rs6000-call.c (altivec_init_builtins): Remove forward
+ declaration.
+ (builtin_function_type): Likewise.
+ (rs6000_common_init_builtins): Likewise.
+ (htm_init_builtins): Likewise.
+ (mma_init_builtins): Likewise.
+ (def_builtin): Remove dead function.
+ (rs6000_expand_zeroop_builtin): Likewise.
+ (rs6000_expand_mtfsf_builtin): Likewise.
+ (rs6000_expand_mtfsb_builtin): Likewise.
+ (rs6000_expand_set_fpscr_rn_builtin): Likewise.
+ (rs6000_expand_set_fpscr_drn_builtin): Likewise.
+ (rs6000_expand_unop_builtin): Likewise.
+ (altivec_expand_abs_builtin): Likewise.
+ (rs6000_expand_binop_builtin): Likewise.
+ (altivec_expand_lxvr_builtin): Likewise.
+ (altivec_expand_lv_builtin): Likewise.
+ (altivec_expand_stxvl_builtin): Likewise.
+ (altivec_expand_stv_builtin): Likewise.
+ (mma_expand_builtin): Likewise.
+ (htm_expand_builtin): Likewise.
+ (cpu_expand_builtin): Likewise.
+ (rs6000_expand_quaternop_builtin): Likewise.
+ (rs6000_expand_ternop_builtin): Likewise.
+ (altivec_expand_dst_builtin): Likewise.
+ (altivec_expand_vec_sel_builtin): Likewise.
+ (altivec_expand_builtin): Likewise.
+ (rs6000_invalid_builtin): Likewise.
+ (rs6000_builtin_valid_without_lhs): Likewise.
+ (rs6000_gimple_fold_builtin): Remove test for new_builtins_are_live and
+ simplify.
+ (rs6000_expand_builtin): Likewise.
+ (rs6000_init_builtins): Remove tests for new_builtins_are_live and
+ simplify.
+ (rs6000_builtin_decl): Likewise.
+ (altivec_init_builtins): Remove dead function.
+ (mma_init_builtins): Likewise.
+ (htm_init_builtins): Likewise.
+ (builtin_quaternary_function_type): Likewise.
+ (builtin_function_type): Likewise.
+ (rs6000_common_init_builtins): Likewise.
+ * config/rs6000/rs6000-gen-builtins.c (write_header_file): Don't
+ declare new_builtins_are_live.
+ (write_init_bif_table): In generated code, remove test for
+ new_builtins_are_live and simplify.
+ (write_init_ovld_table): Likewise.
+ (write_init_file): Don't initialize new_builtins_are_live.
+ * config/rs6000/rs6000.c (rs6000_builtin_vectorized_function): Remove
+ test for new_builtins_are_live and simplify.
+ (rs6000_builtin_md_vectorized_function): Likewise.
+ (rs6000_builtin_reciprocal): Likewise.
+ (add_condition_to_bb): Likewise.
+ (rs6000_atomic_assign_expand_fenv): Likewise.
+
+2021-12-14 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ PR target/103625
+ * config/rs6000/rs6000-builtin-new.def (__builtin_altivec_vcmpequd):
+ Move to power8-vector stanza.
+ (__builtin_altivec_vcmpequd_p): Likewise.
+ (__builtin_altivec_vcmpgtsd): Likewise.
+ (__builtin_altivec_vcmpgtsd_p): Likewise.
+ (__builtin_altivec_vcmpgtud): Likewise.
+ (__builtin_altivec_vcmpgtud_p): Likewise.
+
+2021-12-14 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ PR target/103623
+ * config/rs6000/rs6000-builtin-new.def (__builtin_pack_longdouble): Add
+ ibmld attribute.
+ (__builtin_unpack_longdouble): Likewise.
+ * config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): Add special
+ handling for ibmld attribute.
+ * config/rs6000/rs6000-gen-builtins.c (attrinfo): Add isibmld.
+ (parse_bif_attrs): Handle ibmld.
+ (write_decls): Likewise.
+ (write_bif_static_init): Likewise.
+
+2021-12-14 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103585
+ * ipa-modref-tree.c (modref_access_node::range_info_useful_p): Handle
+ MODREF_GLOBAL_MEMORY_PARM.
+ (modref_access_node::dump): Likewise.
+ (modref_access_node::get_call_arg): Likewise.
+ * ipa-modref-tree.h (enum modref_special_parms): Add
+ MODREF_GLOBAL_MEMORY_PARM.
+ (modref_access_node::useful_for_kill): Handle
+ MODREF_GLOBAL_MEMORY_PARM.
+ (modref:tree::merge): Add promote_unknown_to_global.
+ * ipa-modref.c (verify_arg):New function.
+ (may_access_nonescaping_parm_p): New function.
+ (modref_access_analysis::record_global_memory_load): New member
+ function.
+ (modref_access_analysis::record_global_memory_store): Likewise.
+ (modref_access_analysis::process_fnspec): Distingush global and local
+ memory.
+ (modref_access_analysis::analyze_call): Likewise.
+ * tree-ssa-alias.c (ref_may_access_global_memory_p): New function.
+ (modref_may_conflict): Use it.
+
+2021-12-14 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/aarch64/aarch64-builtins.c (enum aarch64_builtins):
+ Define AARCH64_LS64_BUILTIN_LD64B, AARCH64_LS64_BUILTIN_ST64B,
+ AARCH64_LS64_BUILTIN_ST64BV, AARCH64_LS64_BUILTIN_ST64BV0.
+ (aarch64_init_ls64_builtin_decl): Helper function.
+ (aarch64_init_ls64_builtins): Helper function.
+ (aarch64_init_ls64_builtins_types): Helper function.
+ (aarch64_general_init_builtins): Init LS64 intrisics for
+ TARGET_LS64.
+ (aarch64_expand_builtin_ls64): LS64 intrinsics expander.
+ (aarch64_general_expand_builtin): Handle aarch64_expand_builtin_ls64.
+ (ls64_builtins_data): New helper struct.
+ (v8di_UP): New define.
+ * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
+ __ARM_FEATURE_LS64.
+ * config/aarch64/aarch64.c (aarch64_classify_address): Enforce the
+ V8DI range (7-bit signed scaled) for both ends of the range.
+ * config/aarch64/aarch64-simd.md (movv8di): New pattern.
+ (aarch64_movv8di): New pattern.
+ * config/aarch64/aarch64.h (AARCH64_ISA_LS64): New define.
+ (TARGET_LS64): New define.
+ * config/aarch64/aarch64.md: Add UNSPEC_LD64B, UNSPEC_ST64B,
+ UNSPEC_ST64BV and UNSPEC_ST64BV0.
+ (ld64b): New define_insn.
+ (st64b): New define_insn.
+ (st64bv): New define_insn.
+ (st64bv0): New define_insn.
+ * config/aarch64/arm_acle.h (data512_t): New type derived from
+ __arm_data512_t.
+ (__arm_data512_t): New internal type.
+ (__arm_ld64b): New intrinsic.
+ (__arm_st64b): New intrinsic.
+ (__arm_st64bv): New intrinsic.
+ (__arm_st64bv0): New intrinsic.
+ * config/arm/types.md: Add new type ls64.
+
+2021-12-14 Olivier Hainque <hainque@adacore.com>
+
+ * config/i386/t-vxworks: Drop the fPIC multilibs.
+
+2021-12-14 Fred Konrad <konrad@adacore.com>
+
+ * config/rs6000/t-vxworks: Drop the fPIC multilib.
+
+2021-12-13 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR target/99531
+ * ira-costs.c (record_operand_costs): Do not take pseudo class
+ calculated on the 1st iteration into account when processing move
+ involving the pseudo and a hard register.
+
+2021-12-13 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/i386/i386.md (define_split any_or:SWI248 -> orb %?h):
+ Optimize the case where the integer constant operand is zero.
+
+2021-12-13 Doug Rupp <rupp@adacore.com>
+ Olivier Hainque <hainque@adacore.com>
+
+ * config/vxworks.h (VXWORKS_LINK_OS_SPEC): New spec.
+ (VXWORKS_BASE_LINK_SPEC): New spec, using the former.
+ (VXWORKS_EXTRA_LINK_SPEC): New spec for old and new VxWorks.
+ (VXWORKS_LINK_SPEC): Combo of BASE and EXTRA specs.
+ * config/rs6000/vxworks.h (VXWORKS_LINK_OS_SPEC): Empty.
+ (LINK_OS_EXTRA_SPEC32): Use VXWORKS_LINK_SPEC.
+ (LINK_OS_EXTRA_SPEC64): Likewise.
+
+2021-12-13 Fred Konrad <konrad@adacore.com>
+ Olivier Hainque <hainque@adacore.com>
+
+ * config/vxworks.h (VXWORKS_BASE_LIBS_RTP): Guard -lc_internal
+ on !shared+!non-static and document.
+ (VXWORKS_LIB_SPEC): Remove the bits intended to drag the
+ init/fini functions from libc_internal in the shared lib case.
+ (VX_CRTBEGIN_SPEC/VX_CRTEND_SPEC): Use vxcrtstuff objects also in
+ configurations with shared lib and INITFINI_ARRAY support.
+
+2021-12-13 Fred Konrad <konrad@adacore.com>
+ Olivier Hainque <hainque@adacore.com>
+
+ * config/vx-common.h: Define REAL_LIBGCC_SPEC since the
+ '-non-static' option is not standard.
+ * config/vxworks.h (VXWORKS_LIBGCC_SPEC): Implement the LIBGCC_SPEC
+ since REAL_LIBGCC_SPEC is used now.
+ (STARTFILE_PREFIX_SPEC): Use the PIC VSB when building shared libraries
+ or non-static binaries.
+
+2021-12-13 Jan Hubicka <hubicka@ucw.cz>
+
+ * common.opt: Add -fipa-strict-aliasing.
+ * doc/invoke.texi: Document -fipa-strict-aliasing.
+ * ipa-modref.c (modref_access_analysis::record_access): Honor
+ -fipa-strict-aliasing.
+ (modref_access_analysis::record_access_lto): Likewise.
+
+2021-12-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64-arches.def (armv8.8-a): Define.
+ * config/aarch64/aarch64.h (AARCH64_FL_V8_8): Define.
+ (AARCH64_FL_FOR_ARCH8_8): Define.
+ * doc/invoke.texi: Document -march=armv8.8-a.
+
+2021-12-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_expand_setmem_mops): Define.
+ (aarch64_expand_setmem): Adjust for TARGET_MOPS.
+ * config/aarch64/aarch64.h (CLEAR_RATIO): Adjust for TARGET_MOPS.
+ (SET_RATIO): Likewise.
+ * config/aarch64/aarch64.md ("unspec"): Add UNSPEC_SETMEM.
+ (aarch64_setmemdi): Define.
+ (setmemdi): Adjust for TARGET_MOPS.
+ * config/aarch64/aarch64.opt (aarch64-mops-memset-size-threshold):
+ New param.
+
+2021-12-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64.md (aarch64_movmemdi): Define.
+ (movmemdi): Define.
+ (unspec): Add UNSPEC_MOVMEM.
+ * config/aarch64/aarch64.opt (aarch64-mops-memmove-size-threshold):
+ New param.
+
+2021-12-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64-option-extensions.def (mops): Define.
+ * config/aarch64/aarch64.c (aarch64_expand_cpymem_mops): Define.
+ (aarch64_expand_cpymem): Define.
+ * config/aarch64/aarch64.h (AARCH64_FL_MOPS): Define.
+ (AARCH64_ISA_MOPS): Define.
+ (TARGET_MOPS): Define.
+ (MOVE_RATIO): Adjust for TARGET_MOPS.
+ * config/aarch64/aarch64.md ("unspec"): Add UNSPEC_CPYMEM.
+ (aarch64_cpymemdi): New pattern.
+ (cpymemdi): Adjust for TARGET_MOPS.
+ * config/aarch64/aarch64.opt (aarch64-mops-memcpy-size-threshol):
+ New param.
+ * doc/invoke.texi (AArch64 Options): Document +mops.
+
+2021-12-13 Martin Liska <mliska@suse.cz>
+
+ PR ipa/103636
+ * ipa-inline.c (can_inline_edge_p): Move logic checking
+ no_profile_instrument_function logic to ...
+ (can_early_inline_edge_p): ... here.
+
+2021-12-13 Olivier Hainque <hainque@adacore.com>
+
+ * config/vxworks/_yvals.h: #include yvals.h also if
+ defined(__RTP__).
+
+2021-12-13 Olivier Hainque <hainque@adacore.com>
+
+ * config/vxworks.h (VXWORKS_OS_CPP_BUILTINS): Define
+ _C99 for C++.
+
+2021-12-13 Olivier Hainque <hainque@adacore.com>
+
+ * config/t-vxworks: Clear NATIVE_SYSTEM_HEADER_DIR.
+ * config/vxworks.h (SYSROOT_HEADERS_SUFFIX_SPEC): Define, for
+ VxWorks 7 and earlier.
+ (VXWORKS_ADDITIONAL_CPP_SPEC): Simplify accordingly.
+ (STARTFILE_PREFIX_SPEC): Adjust accordingly.
+ * config/rs6000/vxworks.h (STARTFILE_PREFIX_SPEC): Adjust.
+
+2021-12-13 Martin Liska <mliska@suse.cz>
+
+ * doc/extend.texi: Use @item for the first @itemx entry.
+
+2021-12-13 Jakub Jelinek <jakub@redhat.com>
+
+ * machmode.h (gt_pch_nx): Use gt_pointer_operator as type of second
+ argument instead of equivalent void (*) (void *, void *, void *).
+ * poly-int.h (gt_pch_nx): Likewise.
+ * wide-int.h (gt_pch_nx): Likewise.
+ * config/aarch64/aarch64-sve-builtins.cc (gt_pch_nx): Likewise.
+
+2021-12-13 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103513
+ * ipa-fnsummary.c (evaluate_conditions_for_known_args): Do not ICE
+ on ternary expression.
+
+2021-12-13 Kewen Lin <linkw@linux.ibm.com>
+
+ PR target/103515
+ * attribs.c (decl_attributes): Check if target options change and
+ create one node if so.
+
+2021-12-12 Jonathan Wakely <jwakely@redhat.com>
+
+ * Makefile.in: Remove unique-ptr-tests.o.
+ * selftest-run-tests.c (selftest::run_tests): Remove
+ unique_ptr_tests_cc_tests.
+ * selftest.h (unique_ptr_tests_cc_tests): Remove.
+ * system.h: Check INCLUDE_MEMORY instead of INCLUDE_UNIQUE_PTR
+ and include <memory> instead of "unique-ptr.h".
+ * unique-ptr-tests.cc: Removed.
+
+2021-12-12 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/nvptx/nvptx-opts.h (ptx_isa): Add PTX_ISA_SM53 ISA level
+ to enumeration.
+ * config/nvptx/nvptx.opt: Add sm_53 to -misa.
+ * config/nvptx/nvptx-modes.def: Add support for HFmode.
+ * config/nvptx/nvptx.h (TARGET_SM53):
+ New helper macro to conditionalize functionality on target ISA.
+ * config/nvptx/nvptx-c.c (nvptx_cpu_cpp_builtins): Add __PTX_SM__
+ support for the new ISA levels.
+ * config/nvptx/nvptx.c (nvtx_ptx_type_from_mode): Support new HFmode
+ with the ".f16" suffix/qualifier.
+ (nvptx_file_start): Add support for TARGET_SM53.
+ (nvptx_omp_device_kind_arch_isa): Add support for TARGET_SM53
+ and tweak TARGET_SM35.
+ (nvptx_scalar_mode_supported_p): Target hook with conditional
+ HFmode support on TARGET_SM53 and higher.
+ (nvptx_libgcc_floating_mode_supported_p): Likewise.
+ (TARGET_SCALAR_MODE_SUPPORTED_P): Use nvptx_scalar_mode_supported_p.
+ (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Likewise, use new hook.
+ * config/nvptx/nvptx.md (*movhf_insn): New define_insn.
+ (movhf): New define_expand for HFmode moves.
+ (addhf3, subhf3, mulhf, extendhf<mode>2, trunc<mode>hf2): New
+ instructions conditional on TARGET_SM53 (i.e. -misa=sm_53).
+
+2021-12-12 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103665
+ * ipa-modref.c (modref_access_analysis::analyze): Terminate BB
+ analysis on NULL memory access.
+ * ipa-pure-const.c (analyze_function): Likewise.
+
+2021-12-11 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-profile.c (ipa_profile): Do not update hot bb threshold.
+
+2021-12-11 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c (get_modref_function_summary): Use ultimate_alias_target.
+ (ignore_edge): Likewise.
+ (compute_parm_map): Likewise.
+ (modref_propagate_in_scc): Likewise.
+ (modref_propagate_flags_in_scc): Likewise.
+
+2021-12-10 Jason Merrill <jason@redhat.com>
+
+ * symtab.c (symtab_node::equal_address_to): Fix comment typo.
+
+2021-12-10 Doug Rupp <rupp@adacore.com>
+
+ * config/vxworks.h (LINK_SPEC): Remove %(link_target).
+ Change %{v:-v} to %{v:-V}.
+
+2021-12-10 Olivier Hainque <hainque@adacore.com>
+
+ * config/t-vxworks: Remove assignment to STMP_FIXINC.
+
+2021-12-10 Martin Liska <mliska@suse.cz>
+
+ * params.opt: Add missing dot.
+
+2021-12-10 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR ipa/103601
+ * ipa-modref-tree.h (useful_for_kill_p): Zero width accesses aren't
+ useful for kill tracking.
+
+2021-12-10 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/mkoffload.c (process_asm): Process the variable table
+ completely differently.
+ (process_obj): Encode the varaible data differently.
+
+2021-12-10 Joel Hutton <joel.hutton@arm.com>
+
+ PR tree-optimization/103523
+ * tree-vect-loop.c (vectorizable_induction): Check for
+ PLUS_EXPR/MINUS_EXPR support.
+
+2021-12-10 Cui,Lili <lili.cui@intel.com>
+
+ * config/i386/i386.c (ix86_vector_costs::add_stmt_cost): Remove Tremont.
+
+2021-12-09 Jan Hubicka <hubicka@ucw.cz>
+
+ * doc/invoke.texi (max-inline-functions-called-once-loop-depth,
+ max-inline-functions-called-once-insns): New parameters.
+ * ipa-inline.c (check_callers): Handle
+ param_inline_functions_called_once_loop_depth and
+ param_inline_functions_called_once_insns.
+ (edge_badness): Fix linebreaks.
+ * params.opt (param=max-inline-functions-called-once-loop-depth,
+ param=max-inline-functions-called-once-insn): New params.
+
+2021-12-09 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/103215
+ * pointer-query.cc (access_ref::merge_ref): Extend the offset and
+ size of the merged object instead of using the larger.
+
+2021-12-09 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/101751
+ * doc/extend.texi (attribute access): Adjust.
+ * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
+ Treat access mode none on a void* argument as expecting as few as
+ zero bytes.
+
+2021-12-09 Jakub Jelinek <jakub@redhat.com>
+
+ PR pch/71934
+ * config/aarch64/aarch64-sve-builtins.cc (gt_pch_nx): Change type of
+ second argument from function with 2 pointer arguments to function
+ with 3 pointer arguments.
+
+2021-12-09 Olivier Hainque <hainque@adacore.com>
+
+ * config/aarch64/aarch64-vxworks.h (TARGET_OS_CPP_BUILTINS):
+ Use VX_CPU_PREFIX in CPU definitions.
+
+2021-12-09 Martin Sebor <msebor@redhat.com>
+
+ * pointer-query.cc (access_ref::dump): Define new function
+ (pointer_query::dump): Call it.
+ * pointer-query.h (access_ref::dump): Declare new function.
+
+2021-12-09 Martin Sebor <msebor@redhat.com>
+
+ * pointer-query.cc (compute_objsize_r): Add an argument.
+ (gimple_call_return_array): Pass a new argument to compute_objsize_r.
+ (access_ref::merge_ref): Same.
+ (access_ref::inform_access): Add an argument and use it.
+ (access_data::access_data): Initialize new member.
+ (handle_min_max_size): Pass a new argument to compute_objsize_r.
+ (handle_decl): New function.
+ (handle_array_ref): Pass a new argument to compute_objsize_r.
+ Avoid incrementing deref.
+ (set_component_ref_size): New function.
+ (handle_component_ref): New function.
+ (handle_mem_ref): Pass a new argument to compute_objsize_r.
+ Only increment deref after successfully computing object size.
+ (handle_ssa_name): New function.
+ (compute_objsize_r): Move code into helpers and call them.
+ (compute_objsize): Pass a new argument to compute_objsize_r.
+ * pointer-query.h (access_ref::inform_access): Add an argument.
+ (access_data::ostype): New member.
+
+2021-12-09 Martin Sebor <msebor@redhat.com>
+
+ * pointer-query.cc (access_ref::merge_ref): Define new function.
+ (access_ref::get_ref): Move code into merge_ref and call it.
+ * pointer-query.h (access_ref::merge_ref): Declare new function.
+
+2021-12-09 Martin Sebor <msebor@redhat.com>
+
+ * gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Pass
+ GIMPLE statement to compute_objsize.
+ * pointer-query.cc (compute_objsize): Add a statement argument.
+ * pointer-query.h (compute_objsize): Define a new overload.
+
+2021-12-09 Martin Sebor <msebor@redhat.com>
+
+ * gimple-ssa-warn-access.cc (check_access): Adjust to member name
+ change.
+ (pass_waccess::check_strncmp): Same.
+ * pointer-query.cc (access_ref::access_ref): Remove arguments.
+ Simpilfy.
+ (access_data::access_data): Define new ctors.
+ (access_data::set_bound): Define new member function.
+ (compute_objsize_r): Remove unnecessary code.
+ * pointer-query.h (struct access_ref): Remove ctor arguments.
+ (struct access_data): Declare ctor overloads.
+ (access_data::dst_bndrng): New member.
+ (access_data::src_bndrng): New member.
+
+2021-12-09 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/103143
+ * pointer-query.cc (gimple_call_return_array): Call compute_objsize_r.
+
+2021-12-09 Olivier Hainque <hainque@adacore.com>
+ Rasmus Villemoes <rv@rasmusvillemoes.dk>
+
+ * Makefile.in (T_STDINT_GCC_H): New variable, path to
+ stdint-gcc.h that a target configuration may override when
+ use_gcc_stdint is "provide".
+ (stmp-int-hdrs): Depend on it and copy that for
+ USE_GCC_INT=provide.
+ * config.gcc (vxworks): Revert to use_gcc_stdint=provide.
+ * config/t-vxworks (T_STDINT_GCC_H): Define, as vxw-stdint-gcc.h.
+ (vxw-stdint-gcc.h): New target, produced from the original
+ stdint-gcc.h.
+ (vxw-glimits.h): Use an automatic variable to designate the
+ first and only prerequisite.
+ * config/vxworks/stdint.h: Remove.
+
+2021-12-09 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR pch/71934
+ * config/host-darwin.c (SAFE_ALLOC_SIZE): Remove.
+ (darwin_gt_pch_get_address): Rework for relocatable PCH.
+ (darwin_gt_pch_use_address): Likewise.
+
+2021-12-09 Jakub Jelinek <jakub@redhat.com>
+
+ PR pch/71934
+ * config/host-darwin.c (darwin_gt_pch_use_address): When reading
+ manually the file into mapped area, update mapped_addr as
+ an automatic variable rather than addr which is a reference parameter.
+ * config/host-hpux.c (hpux_gt_pch_use_address): When reading
+ manually the file into mapped area, update addr as
+ an automatic variable rather than base which is a reference parameter.
+
+2021-12-09 Jakub Jelinek <jakub@redhat.com>
+
+ PR pch/71934
+ * coretypes.h (gt_pointer_operator): Use 3 pointer arguments instead
+ of two.
+ * gengtype.c (struct walk_type_data): Add in_nested_ptr argument.
+ (walk_type): Temporarily set d->in_nested_ptr around nested_ptr
+ handling.
+ (write_types_local_user_process_field): Pass a new middle pointer
+ to gt_pointer_operator op calls, if d->in_nested_ptr pass there
+ address of d->prev_val[2], otherwise NULL.
+ (write_types_local_process_field): Likewise.
+ * ggc-common.c (relocate_ptrs): Add real_ptr_p argument. If equal
+ to ptr_p, do nothing, otherwise if NULL remember ptr_p's
+ or if non-NULL real_ptr_p's corresponding new address in
+ reloc_addrs_vec.
+ (reloc_addrs_vec): New variable.
+ (compare_ptr, read_uleb128, write_uleb128): New functions.
+ (gt_pch_save): When iterating over objects through relocate_ptrs,
+ save current i into state.ptrs_i. Sort reloc_addrs_vec and emit
+ it as uleb128 of differences between pointer addresses into the
+ PCH file.
+ (gt_pch_restore): Allow restoring of PCH to a different address
+ than the preferred one, in that case adjust global pointers by bias
+ and also adjust by bias addresses read from the relocation table
+ as uleb128 differences. Otherwise fseek over it. Perform
+ gt_pch_restore_stringpool only after adjusting callbacks and for
+ callback adjustments also take into account the bias.
+ (default_gt_pch_use_address): Change type of first argument from
+ void * to void *&.
+ (mmap_gt_pch_use_address): Likewise.
+ * ggc-tests.c (gt_pch_nx): Pass NULL as new middle argument to op.
+ * hash-map.h (hash_map::pch_nx_helper): Likewise.
+ (gt_pch_nx): Likewise.
+ * hash-set.h (gt_pch_nx): Likewise.
+ * hash-table.h (gt_pch_nx): Likewise.
+ * hash-traits.h (ggc_remove::pch_nx): Likewise.
+ * hosthooks-def.h (default_gt_pch_use_address): Change type of first
+ argument from void * to void *&.
+ (mmap_gt_pch_use_address): Likewise.
+ * hosthooks.h (struct host_hooks): Change type of first argument of
+ gt_pch_use_address hook from void * to void *&.
+ * machmode.h (gt_pch_nx): Expect a callback with 3 pointers instead of
+ two in the middle argument.
+ * poly-int.h (gt_pch_nx): Likewise.
+ * stringpool.c (gt_pch_nx): Pass NULL as new middle argument to op.
+ * tree-cfg.c (gt_pch_nx): Likewise, except for LOCATION_BLOCK pass
+ the same &(block) twice.
+ * value-range.h (gt_pch_nx): Pass NULL as new middle argument to op.
+ * vec.h (gt_pch_nx): Likewise.
+ * wide-int.h (gt_pch_nx): Likewise.
+ * config/host-darwin.c (darwin_gt_pch_use_address): Change type of
+ first argument from void * to void *&.
+ * config/host-darwin.h (darwin_gt_pch_use_address): Likewise.
+ * config/host-hpux.c (hpux_gt_pch_use_address): Likewise.
+ * config/host-linux.c (linux_gt_pch_use_address): Likewise. If
+ it couldn't succeed to mmap at the preferred location, set base
+ to the actual one. Update addr in the manual reading loop instead of
+ base.
+ * config/host-netbsd.c (netbsd_gt_pch_use_address): Change type of
+ first argument from void * to void *&.
+ * config/host-openbsd.c (openbsd_gt_pch_use_address): Likewise.
+ * config/host-solaris.c (sol_gt_pch_use_address): Likewise.
+ * config/i386/host-mingw32.c (mingw32_gt_pch_use_address): Likewise.
+ * config/rs6000/rs6000-gen-builtins.c (write_init_file): Pass NULL
+ as new middle argument to op in the generated code.
+ * doc/gty.texi: Adjust samples for the addition of middle pointer
+ to gt_pointer_operator callback.
+
+2021-12-09 Alexandre Oliva <oliva@adacore.com>
+
+ PR target/103097
+ * reg-stack.c (convert_regs_1): Move any_malformed_asm
+ resetting...
+ (reg_to_stack): ... here.
+
+2021-12-09 Alexandre Oliva <oliva@adacore.com>
+
+ PR target/103302
+ * expr.c (emit_move_multi_word): Skip clobber during lra.
+
+2021-12-09 Alexandre Oliva <oliva@adacore.com>
+
+ PR tree-optimization/103024
+ PR middle-end/103530
+ * gimple-harden-conditionals.cc (non_eh_succ_edge): New.
+ (pass_harden_compares::execute): Accept 1-bit integral types,
+ and cope with throwing compares.
+
+2021-12-08 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.h (DARWIN_PIE_SPEC): Add -no_pie when
+ linking mdynamic-no-pic code on macOS > 10.7.
+
+2021-12-08 Dimitar Dimitrov <dimitar@dinux.eu>
+
+ * config/pru/pru.c (pru_section_type_flags): New function.
+ (TARGET_SECTION_TYPE_FLAGS): Wire it.
+
+2021-12-08 David Faust <david.faust@oracle.com>
+
+ * config/bpf/bpf.c (handle_attr_preserve): Avoid calling
+ is_gimple_assign with a NULL pointer.
+
+2021-12-08 Martin Liska <mliska@suse.cz>
+
+ * profile-count.c (profile_count::dump): Add function
+ that can dump to a provided buffer.
+ (profile_probability::dump): Likewise.
+ * profile-count.h: Likewise.
+ * tree-ssa-loop-unswitch.c (tree_unswitch_single_loop):
+ Use dump_printf_loc infrastructure.
+ (tree_unswitch_outer_loop): Likewise.
+ (find_loop_guard): Likewise.
+ (hoist_guard): Likewise.
+
+2021-12-08 Chung-Lin Tang <cltang@codesourcery.com>
+
+ * gimplify.c (extract_base_bit_offset): Add 'tree *offsetp' parameter,
+ accomodate case where 'offset' return of get_inner_reference is
+ non-NULL.
+ (is_or_contains_p): Further robustify conditions.
+ (omp_target_reorder_clauses): In alloc/to/from sorting phase, also
+ move following GOMP_MAP_ALWAYS_POINTER maps along. Add new sorting
+ phase where we make sure pointers with an attach/detach map are ordered
+ correctly.
+ (gimplify_scan_omp_clauses): Add modifications to avoid creating
+ GOMP_MAP_STRUCT and associated alloc map for attach/detach maps.
+
+2021-12-08 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/nvptx/nvptx.md (*extend_trunc_<mode>2_qi,
+ *extend_trunc_<mode>2_hi, *extend_trunc_di2_si): New insns.
+ Use cvt to perform sign-extension of truncation in one step.
+
+2021-12-08 Chung-Lin Tang <cltang@codesourcery.com>
+
+ PR middle-end/92120
+ * gimplify.c ("tree-hash-traits.h"): Add include.
+ (gimplify_scan_omp_clauses): Change struct_map_to_clause to type
+ hash_map<tree_operand, tree> *. Adjust struct map handling to handle
+ cases of *A and A->B expressions. Under !DECL_P case of
+ GOMP_CLAUSE_MAP handling, add STRIP_NOPS for indir_p case, add to
+ struct_deref_set for map(*ptr_to_struct) cases. Add MEM_REF case when
+ handling component_ref_p case. Add unshare_expr and gimplification
+ when created GOMP_MAP_STRUCT is not a DECL. Add code to add
+ firstprivate pointer for *pointer-to-struct case.
+ (gimplify_adjust_omp_clauses): Move GOMP_MAP_STRUCT removal code for
+ exit data directives code to earlier position.
+ * omp-low.c (lower_omp_target):
+ Handle GOMP_MAP_ATTACH_ZERO_LENGTH_ARRAY_SECTION, and
+ GOMP_MAP_POINTER_TO_ZERO_LENGTH_ARRAY_SECTION map kinds.
+ * tree-pretty-print.c (dump_omp_clause): Likewise.
+
+2021-12-08 Andrew Stubbs <ams@codesourcery.com>
+ Hafiz Abid Qadeer <abidh@codesourcery.com>
+
+ * dwarf2cfi.c (dw_stack_pointer_regnum): Change type to struct cfa_reg.
+ (dw_frame_pointer_regnum): Likewise.
+ (new_cfi_row): Use set_by_dwreg.
+ (get_cfa_from_loc_descr): Use set_by_dwreg. Support register spans.
+ handle DW_OP_bregx with DW_OP_breg{0-31}. Support DW_OP_lit*,
+ DW_OP_const*, DW_OP_minus, DW_OP_shl and DW_OP_plus.
+ (lookup_cfa_1): Use set_by_dwreg.
+ (def_cfa_0): Update for cfa_reg and support register spans.
+ (reg_save): Change sreg parameter to struct cfa_reg. Support register
+ spans.
+ (dwf_cfa_reg): New function.
+ (dwarf2out_flush_queued_reg_saves): Use dwf_cfa_reg instead of
+ dwf_regno.
+ (dwarf2out_frame_debug_def_cfa): Likewise.
+ (dwarf2out_frame_debug_adjust_cfa): Likewise.
+ (dwarf2out_frame_debug_cfa_offset): Likewise. Update reg_save usage.
+ (dwarf2out_frame_debug_cfa_register): Likewise.
+ (dwarf2out_frame_debug_expr): Likewise.
+ (create_pseudo_cfg): Use set_by_dwreg.
+ (initial_return_save): Use set_by_dwreg and dwf_cfa_reg,
+ (create_cie_data): Use dwf_cfa_reg.
+ (execute_dwarf2_frame): Use dwf_cfa_reg.
+ (dump_cfi_row): Use set_by_dwreg.
+ * dwarf2out.c (build_span_loc, build_breg_loc): New function.
+ (build_cfa_loc): Support register spans.
+ (build_cfa_aligned_loc): Update cfa_reg usage.
+ (convert_cfa_to_fb_loc_list): Use set_by_dwreg.
+ * dwarf2out.h (struct cfa_reg): New type.
+ (struct dw_cfa_location): Use struct cfa_reg.
+ (build_span_loc): New prototype.
+
+2021-12-08 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/100738
+ * config/i386/sse.md
+ (*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_not_ltint):
+ Add new define_insn_and_split.
+
+2021-12-08 Alexandre Oliva <oliva@adacore.com>
+
+ PR middle-end/103149
+ * gimple-harden-conditionals.cc (detach_value): Use memory if
+ general regs won't do.
+
+2021-12-07 Martin Liska <mliska@suse.cz>
+
+ PR middle-end/103438
+ * config/s390/s390.c (s390_valid_target_attribute_inner_p):
+ Use new enum CLVC_INTEGER.
+ * opt-functions.awk: Use new CLVC_INTEGER.
+ * opts-common.c (set_option): Likewise.
+ (option_enabled): Return -1,0,1 for CLVC_INTEGER.
+ (get_option_state): Use new CLVC_INTEGER.
+ (control_warning_option): Likewise.
+ * opts.h (enum cl_var_type): Likewise.
+
+2021-12-07 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/103594
+ * config/i386/i386.c (ix86_call_use_plt_p): Check FUNCTION_DECL
+ before calling cgraph_node::get.
+
+2021-12-07 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103596
+ * tree-ssa-sccvn.c (eliminate_dom_walker::eliminate_stmt):
+ Note we are not propagating into a PHI argument to may_propagate_copy.
+ * tree-ssa-propagate.h (may_propagate_copy): Add
+ argument specifying whether we propagate into a PHI arg.
+ * tree-ssa-propagate.c (may_propagate_copy): Likewise.
+ When not doing so we can replace an abnormal with
+ something else.
+ (may_propagate_into_stmt): Update may_propagate_copy calls.
+ (replace_exp_1): Move propagation checking code to
+ propagate_value and rename to ...
+ (replace_exp): ... this and elide previous wrapper.
+ (propagate_value): Perform checking with adjusted
+ may_propagate_copy call and dispatch to replace_exp.
+
+2021-12-07 Matthias Kretz <m.kretz@gsi.de>
+
+ * hash-map.h (hash_map::traverse): Let both overloads behave the
+ same.
+ * predict.c (assert_is_empty): Return true, thus not changing
+ behavior.
+
+2021-12-07 YunQiang Su <yunqiang.su@cipunited.com>
+
+ * config/mips/mips.h (ISA_HAS_UNALIGNED_ACCESS, STRICT_ALIGNMENT):
+ R6 can unaligned access.
+ * config/mips/mips.md (movmisalign<mode>): Likewise.
+ * config/mips/mips.opt: add -m(no-)unaligned-access
+ * doc/invoke.texi: Likewise.
+
+2021-12-07 Eugene Rozenfeld <erozen@microsoft.com>
+
+ * auto-profile.c (afdo_propagate_edge): Improve count propagation algorithm.
+
+2021-12-06 Paul A. Clarke <pc@us.ibm.com>
+
+ PR target/103545
+ * config/rs6000/xmmintrin.h (_mm_movemask_ps): Replace "vector" with
+ "__vector".
+
+2021-12-06 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/bpf/bpf.c (bpf_handle_preserve_access_index_attribute):
+ Mark arguments `args' and flags' as unused.
+ (bpf_core_newdecl): Remove unused local `newdecl'.
+ (bpf_core_newdecl): Remove unused argument `loc'.
+ (ctfc_debuginfo_early_finish_p): Remove unused function.
+ (TARGET_CTFC_DEBUGINFO_EARLY_FINISH_P): Remove definition.
+ (bpf_core_walk): Do not pass a location to bpf_core_newdecl.
+
+2021-12-06 Richard Sandiford <richard.sandiford@arm.com>
+
+ * gimple-range-edge.cc (gimple_outgoing_range::edge_range_p): Add
+ a shortcut for blocks with single successors.
+ * gimple-range-gori.cc (gori_map::calculate_gori): Likewise.
+
+2021-12-06 Richard Sandiford <richard.sandiford@arm.com>
+
+ * value-range.cc (irange::irange_union): Use quick_push rather
+ than safe_push. Use widest_int rather than wide_int. Avoid
+ assigning wi::to_* results to wide*_int temporaries.
+
+2021-12-06 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-cache.cc (ranger_cache::fill_block_cache): Check for
+ a range from dominators before filling the cache.
+ (ranger_cache::range_from_dom): New.
+ * gimple-range-cache.h (ranger_cache::range_from_dom): Add prototype.
+
+2021-12-06 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-gori.h (class gori_compute):: Add prototypes.
+ * gimple-range-gori.cc (gori_compute::has_edge_range_p): Add alternate
+ API for basic block. Call for edge alterantive.
+ (gori_compute::may_recompute_p): Ditto.
+
+2021-12-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103581
+ * tree-vect-stmts.c (vect_build_gather_load_calls): Properly
+ guard all the AVX512 mask cases.
+
+2021-12-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103544
+ * tree-vect-slp.c (vect_analyze_slp): Only add a SLP reduction
+ opportunity if the stmt in question is the reduction root.
+ (dot_slp_tree): Add missing check for NULL child.
+
+2021-12-06 Jakub Jelinek <jakub@redhat.com>
+
+ PR pch/71934
+ * config/avr/avr.c (avr_output_data_section_asm_op,
+ avr_output_bss_section_asm_op): Change argument type from const void *
+ to const char *.
+
+2021-12-06 Tamar Christina <tamar.christina@arm.com>
+
+ PR rtl-optimization/103404
+ * cse.c (find_sets_in_insn): Don't select elements out of a V1 mode
+ subreg.
+
+2021-12-06 Hongtao Liu <Hongtao.liu@intel.com>
+ Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95740
+ * config/i386/i386.c (ix86_preferred_reload_class): Allow
+ integer regs when moves between register units are cheap.
+ * config/i386/i386.h (INT_SSE_CLASS_P): New.
+
+2021-12-05 David Edelsohn <dje.gcc@gmail.com>
+
+ * config/rs6000/rs6000-call.c (rs6000_init_builtins): Move
+ AIX math builtin initialization before new_builtins_are_live.
+
+2021-12-04 Jakub Jelinek <jakub@redhat.com>
+
+ * config/i386/x86-tune.def (X86_TUNE_PARTIAL_REG_DEPENDENCY): Fix
+ comment typo, Preffer -> prefer.
+ * ipa-modref-tree.c (modref_access_node::closer_pair_p): Likewise.
+
+2021-12-04 Alexandre Oliva <oliva@adacore.com>
+
+ PR rtl-optimization/103028
+ * ifcvt.c (find_cond_trap): Validate new insns more strictly
+ after reload.
+
+2021-12-03 Martin Liska <mliska@suse.cz>
+ Peter Bergner <bergner@linux.ibm.com>
+
+ PR target/101324
+ * config/rs6000/rs6000.c (rs6000_option_override_internal): Move the
+ disabling of shrink-wrapping when using -mrop-protect from here...
+ (rs6000_override_options_after_change): ...to here.
+
+2021-12-03 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/103269
+ * config/i386/i386-expand.c (ix86_expand_builtin): Pass PVW_NONE
+ and PVW_NONE to ix86_target_string.
+ * config/i386/i386-options.c (ix86_target_string): Add arguments
+ for move_max and store_max.
+ (ix86_target_string::add_vector_width): New lambda.
+ (ix86_debug_options): Pass ix86_move_max and ix86_store_max to
+ ix86_target_string.
+ (ix86_function_specific_print): Pass ptr->x_ix86_move_max and
+ ptr->x_ix86_store_max to ix86_target_string.
+ (ix86_valid_target_attribute_tree): Handle x_ix86_move_max and
+ x_ix86_store_max.
+ (ix86_option_override_internal): Set the default x_ix86_move_max
+ and x_ix86_store_max.
+ * config/i386/i386-options.h (ix86_target_string): Add
+ prefer_vector_width and prefer_vector_width.
+ * config/i386/i386.h (TARGET_AVX256_MOVE_BY_PIECES): Removed.
+ (TARGET_AVX256_STORE_BY_PIECES): Likewise.
+ (MOVE_MAX): Use 64 if ix86_move_max or ix86_store_max ==
+ PVW_AVX512. Use 32 if ix86_move_max or ix86_store_max >=
+ PVW_AVX256.
+ (STORE_MAX_PIECES): Use 64 if ix86_store_max == PVW_AVX512.
+ Use 32 if ix86_store_max >= PVW_AVX256.
+ * config/i386/i386.opt: Add -mmove-max=bits and -mstore-max=bits.
+ * config/i386/x86-tune.def (X86_TUNE_AVX512_MOVE_BY_PIECES): New.
+ (X86_TUNE_AVX512_STORE_BY_PIECES): Likewise.
+ * doc/invoke.texi: Document -mmove-max=bits and -mstore-max=bits.
+
+2021-12-03 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000.c (rs6000_builtin_reciprocal): Fix builtin
+ identifiers.
+
+2021-12-03 SiYu Wu <siyu@isrc.iscas.ac.cn>
+
+ * common/config/riscv/riscv-common.c (riscv_implied_info):
+ Add K-ext related entry.
+ (riscv_supported_std_ext): Add 'k'.
+ * config/riscv/arch-canonicalize (CANONICAL_ORDER): Add 'k'.
+ (IMPLIED_EXT): Add K-ext related entry.
+
+2021-12-03 SiYu Wu <siyu@isrc.iscas.ac.cn>
+
+ * common/config/riscv/riscv-common.c (riscv_ext_version_table):
+ Add zbk* and zk*.
+ * config/riscv/riscv-opts.h (MASK_ZBKB): New.
+ (MASK_ZBKC): Ditto.
+ (MASK_ZBKX): Ditto.
+ (MASK_ZKNE): Ditto.
+ (MASK_ZKND): Ditto.
+ (MASK_ZKNH): Ditto.
+ (MASK_ZKR): Ditto.
+ (MASK_ZKSED): Ditto.
+ (MASK_ZKSH): Ditto.
+ (MASK_ZKT): Ditto.
+ (TARGET_ZBKB): Ditto.
+ (TARGET_ZBKC): Ditto.
+ (TARGET_ZBKX): Ditto.
+ (TARGET_ZKNE): Ditto.
+ (TARGET_ZKND): Ditto.
+ (TARGET_ZKNH): Ditto.
+ (TARGET_ZKR): Ditto.
+ (TARGET_ZKSED): Ditto.
+ (TARGET_ZKSH): Ditto.
+ (TARGET_ZKT): Ditto.
+ * config/riscv/riscv.opt (riscv_zk_subext): New.
+
+2021-12-03 Tamar Christina <tamar.christina@arm.com>
+
+ * tree-vect-stmts.c (prepare_load_store_mask): Rename to...
+ (prepare_vec_mask): ...This and record operations that have already been
+ masked.
+ (vectorizable_call): Use it.
+ (vectorizable_operation): Likewise.
+ (vectorizable_store): Likewise.
+ (vectorizable_load): Likewise.
+ * tree-vectorizer.h (class _loop_vec_info): Add vec_cond_masked_set.
+ (vec_cond_masked_set_type, tree_cond_mask_hash): New.
+
+2021-12-03 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/51469
+ PR target/83782
+ * target.def (ifunc_ref_local_ok): Add a target hook.
+ * varasm.c (default_binds_local_p_3): Force indirect function
+ resolver non-local only if targetm.ifunc_ref_local_ok returns
+ false.
+ * config/i386/i386-expand.c (ix86_expand_call): Call
+ ix86_call_use_plt_p to check if PLT should be used.
+ * config/i386/i386-protos.h (ix86_call_use_plt_p): New.
+ * config/i386/i386.c (output_pic_addr_const): Call
+ ix86_call_use_plt_p to check if "@PLT" is needed.
+ (ix86_call_use_plt_p): New.
+ (TARGET_IFUNC_REF_LOCAL_OK): New.
+ * doc/tm.texi.in: Add TARGET_IFUNC_REF_LOCAL_OK.
+ * doc/tm.texi: Regenerated.
+
+2021-12-03 Jakub Jelinek <jakub@redhat.com>
+
+ * attribs.h (simple_cst_list_equal): Declare.
+ * attribs.c (simple_cst_list_equal): No longer static.
+ * config/i386/i386-options.c (target_attribute_cache): New variable.
+ (ix86_valid_target_attribute_p): Cache DECL_FUNCTION_SPECIFIC_TARGET
+ and DECL_FUNCTION_SPECIFIC_OPTIMIZATION based on args.
+
+2021-12-03 Jakub Jelinek <jakub@redhat.com>
+
+ PR pch/71934
+ * ggc.h (gt_pch_note_callback): Declare.
+ * gengtype.h (enum typekind): Add TYPE_CALLBACK.
+ (callback_type): Declare.
+ * gengtype.c (dbgprint_count_type_at): Handle TYPE_CALLBACK.
+ (callback_type): New variable.
+ (process_gc_options): Add CALLBACK argument, handle callback
+ option.
+ (set_gc_used_type): Adjust process_gc_options caller, if callback,
+ set type to &callback_type.
+ (output_mangled_typename): Handle TYPE_CALLBACK.
+ (walk_type): Likewise. Handle callback option.
+ (write_types_process_field): Handle TYPE_CALLBACK.
+ (write_types_local_user_process_field): Likewise.
+ (write_types_local_process_field): Likewise.
+ (write_root): Likewise.
+ (dump_typekind): Likewise.
+ (dump_type): Likewise.
+ * gengtype-state.c (type_lineloc): Handle TYPE_CALLBACK.
+ (state_writer::write_state_callback_type): New method.
+ (state_writer::write_state_type): Handle TYPE_CALLBACK.
+ (read_state_callback_type): New function.
+ (read_state_type): Handle TYPE_CALLBACK.
+ * ggc-common.c (callback_vec): New variable.
+ (gt_pch_note_callback): New function.
+ (gt_pch_save): Stream out gt_pch_save function address and relocation
+ table.
+ (gt_pch_restore): Stream in saved gt_pch_save function address and
+ relocation table and apply relocations if needed.
+ * doc/gty.texi (callback): Document new GTY option.
+ * varasm.c (get_unnamed_section): Change callback argument's type and
+ last argument's type from const void * to const char *.
+ (output_section_asm_op): Change argument's type from const void *
+ to const char *, remove unnecessary cast.
+ * tree-core.h (struct tree_translation_unit_decl): Drop GTY((skip))
+ from language member.
+ * output.h (unnamed_section_callback): Change argument type from
+ const void * to const char *.
+ (struct unnamed_section): Use GTY((callback)) instead of GTY((skip))
+ for callback member. Change data member type from const void *
+ to const char *.
+ (struct noswitch_section): Use GTY((callback)) instead of GTY((skip))
+ for callback member.
+ (get_unnamed_section): Change callback argument's type and
+ last argument's type from const void * to const char *.
+ (output_section_asm_op): Change argument's type from const void *
+ to const char *.
+ * config/avr/avr.c (avr_output_progmem_section_asm_op): Likewise.
+ Remove unneeded cast.
+ * config/darwin.c (output_objc_section_asm_op): Change argument's type
+ from const void * to const char *.
+ * config/pa/pa.c (som_output_text_section_asm_op): Likewise.
+ (som_output_comdat_data_section_asm_op): Likewise.
+ * config/rs6000/rs6000.c (rs6000_elf_output_toc_section_asm_op):
+ Likewise.
+ (rs6000_xcoff_output_readonly_section_asm_op): Likewise. Instead
+ of dereferencing directive hardcode variable names and decide based on
+ whether directive is NULL or not.
+ (rs6000_xcoff_output_readwrite_section_asm_op): Change argument's type
+ from const void * to const char *.
+ (rs6000_xcoff_output_tls_section_asm_op): Likewise. Instead
+ of dereferencing directive hardcode variable names and decide based on
+ whether directive is NULL or not.
+ (rs6000_xcoff_output_toc_section_asm_op): Change argument's type
+ from const void * to const char *.
+ (rs6000_xcoff_asm_init_sections): Adjust get_unnamed_section callers.
+
+2021-12-03 Richard Purdie <richard.purdie@linuxfoundation.org>
+
+ * Makefile.in: Fix "argument list too long" from install-plugins.
+
+2021-12-03 Matt Jacobson <mhjacobson@me.com>
+
+ * config.gcc: For the AVR target, populate TM_MULTILIB_CONFIG.
+ * config/avr/genmultilib.awk: Add ability to filter generated multilib
+ list.
+ * config/avr/t-avr: Pass TM_MULTILIB_CONFIG to genmultilib.awk.
+ * configure.ac: Update help string for --with-multilib-list.
+ * configure: Regenerate.
+
+2021-12-02 Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
+
+ * configure: Regenerate.
+ * configure.ac: Define TARGET_LIBC_GNUSTACK on musl.
+
+2021-12-02 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR target/55610
+ * config/host-darwin.c (TRY_EMPTY_VM_SPACE,
+ SAFE_ALLOC_SIZE): New.
+ (darwin_gt_pch_get_address): Rewrite to use nominated
+ memory segments rather than part of the compiler __DATA
+ segment.
+ (darwin_gt_pch_use_address): Likewise.
+
+2021-12-02 Gerald Pfeifer <gerald@pfeifer.com>
+
+ * doc/install.texi (*-*-freebsd*): Remove references to
+ FreeBSD 1 and FreeBSD 2.
+
+2021-12-02 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR rtl-optimization/103437
+ * ira-color.c (setup_allocno_priorities): Switch off backup code
+ for overflow if compiler has __builtin_smul_overflow. Use <
+ for comparison with -INT_MAX.
+
+2021-12-02 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/altivec.h: Delete a number of #defines that are now
+ superfluous. Alphabetize. Include rs6000-vecdefines.h. Include some
+ synonyms.
+ * config/rs6000/rs6000-builtin-new.def (CMPB): Flag as no32bit.
+ (BPERMD): Flag as 32bit (needing special handling for 32-bit).
+ (UNPACK_TD): Return unsigned long long instead of unsigned long.
+ (GET_TEXASR): Return unsigned long instead of unsigned long long.
+ (GET_TEXASRU): Likewise.
+ (GET_TFHAR): Likewise.
+ (GET_TFIAR): Likewise.
+ (SET_TEXASR): Pass unsigned long instead of unsigned long long.
+ (SET_TEXASRU): Likewise.
+ (SET_TFHAR): Likewise.
+ (SET_TFIAR): Likewise.
+ (TABORTDC): Likewise.
+ (TABORTDCI): Likewise.
+ * config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): Fix error
+ handling for no32bit. Add 32bit handling for RS6000_BIF_BPERMD.
+ * config/rs6000/rs6000-gen-builtins.c (write_init_file): Initialize
+ new_builtins_are_live to 1.
+
+2021-12-02 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR rtl-optimization/103437
+ * ira-color.c (setup_allocno_priorities): Use long long
+ multiplication as backup for overflow processing.
+
+2021-12-02 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-protos.h (aarch64_gen_shareable_zero): New.
+ * config/aarch64/aarch64-simd.md (aarch64_rshrn<mode>,
+ aarch64_rshrn2<mode>): Generate rounding half-ing add when appropriate.
+ * config/aarch64/aarch64.c (aarch64_gen_shareable_zero): New.
+
+2021-12-02 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR rtl-optimization/103437
+ * ira-color.c (setup_allocno_priorities): Process multiplication
+ overflow.
+
+2021-12-02 Martin Liska <mliska@suse.cz>
+
+ PR gcov-profile/96092
+ * common.opt: New option.
+ * coverage.c (coverage_begin_function): Emit filename with
+ remap_profile_filename.
+ * doc/invoke.texi: Document the new option.
+ * file-prefix-map.c (add_profile_prefix_map): New.
+ (remap_profile_filename): Likewise.
+ * file-prefix-map.h (add_profile_prefix_map): Likewise.
+ (remap_profile_filename): Likewise.
+ * lto-opts.c (lto_write_options): Handle
+ OPT_fprofile_prefix_map_.
+ * opts-global.c (handle_common_deferred_options): Likewise.
+ * opts.c (common_handle_option): Likewise.
+ (gen_command_line_string): Likewise.
+ * profile.c (output_location): Emit filename with
+ remap_profile_filename.
+
+2021-12-02 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/103271
+ * internal-fn.c (expand_DEFERRED_INIT): When the base
+ of the LHS is a decl with matching constant size use
+ that as the initialization target instead of an
+ eventual VLA typed one.
+
+2021-12-02 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103527
+ * tree-vect-stmts.c (vect_build_gather_load_calls): Always
+ use a truth type for building the vector mask.
+
+2021-12-02 Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+
+ * config/vxworks.h (LTO_PLUGIN_SPEC): Adapt to corrected
+ spelling of -linker-output-auto-nolto-rel.
+
+2021-12-01 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/102811
+ * config/i386/sse.md (VI2F): Remove mode iterator.
+ (VI2F_256_512): New mode iterator.
+ (vec_set<V8_128:mode>_0): New insn pattern.
+ (vec_set<VI2F_256_512:mode>_0>): Rename from vec_set<VI2F:mode>mode.
+ Use VI2F_256_512 mode iterator instead of VI2F.
+ (*axv512fp16_movsh): Remove.
+ (<sse2p4_1>_pinsr<ssemodesuffix>): Add (x,x,x) AVX2 alternative.
+ Do not disable V8HF mode insn on AVX2 targets.
+ (pinsrw -> pbroadcast + pblendw peephole2): New peephole.
+ (pinsrw -> pbroadcast + pblendw splitter): New post-reload splitter.
+ * config/i386/i386.md (extendhfsf): Call gen_vec_setv8hf_0.
+ * config/i386/i386-expand.c (ix86_expand_vector_set)
+ <case E_V8HFmode>: Use vec_merge path for TARGET_AVX2.
+
+2021-12-01 Roger Sayle <roger@nextmovesoftware.com>
+ Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-loop-niter.c (number_of_iterations_until_wrap):
+ Check if simplify_using_initial_conditions allows us to
+ simplify the expression for may_be_zero.
+ * match.pd (X != C ? -X : -C -> -X): New transform.
+ (X != C ? ~X : ~C -> ~X): Likewise.
+ ((X+1) > Y ? -X : 1 -> X >= Y ? -X : 1): Likewise.
+
+2021-12-01 Peter Bergner <bergner@linux.ibm.com>
+
+ PR middle-end/103127
+ * gimplify.c (is_var_need_auto_init): Handle opaque types.
+
+2021-12-01 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ * common.opt (static-libphobos): Add option.
+ * config/darwin.h (LINK_SPEC): Substitute -lgphobos with libgphobos.a
+ when linking statically.
+ * gcc.c (driver_handle_option): Set -static-libphobos as always valid.
+
+2021-12-01 Jason Merrill <jason@redhat.com>
+
+ PR c++/103310
+ * fold-const.c (maybe_nonzero_address): Use get_create or get
+ depending on folding_initializer.
+ (fold_binary_initializer_loc): New.
+ * fold-const.h (fold_binary_initializer_loc): Declare.
+ * varasm.c (mark_weak): Don't use the decl location.
+ * doc/invoke.texi: Document -fconstexpr-fp-except.
+
+2021-12-01 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ PR target/102347
+ * config/rs6000/rs6000-c.c (rs6000-builtins.h): Stop including.
+ (rs6000-internal.h): Include.
+ (altivec_resolve_new_overloaded_builtin): Move call to
+ rs6000_invalid_new_builtin here from rs6000_new_builtin_decl.
+ * config/rs6000/rs6000-call.c (rs6000-builtins.h): Stop including.
+ (rs6000_invalid_new_builtin): Remove static qualifier.
+ (rs6000_new_builtin_decl): Remove test for supported builtin.
+ * config/rs6000/rs6000-internal.h (rs6000-builtins.h): Include.
+ (rs6000_invalid_new_builtin): Declare.
+ * config/rs6000/rs6000.c (rs6000-builtins.h): Don't include.
+
+2021-12-01 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/103409
+ * gimple-range-path.cc (path_range_query::compute_ranges_in_phis):
+ Do all the work with just one ssa_global_cache.
+ * gimple-range-path.h: Remove m_tmp_phi_cache.
+
+2021-12-01 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/103517
+ * tree-vect-slp.c (vect_build_slp_tree_1): When allowing two
+ different component references, check the codes of both them,
+ rather than just the first.
+
+2021-12-01 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/103464
+ * gimple-range.cc (gimple_ranger::prefill_name): Process phis also.
+ (gimple_ranger::prefill_stmt_dependencies): Ditto.
+
+2021-12-01 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ * doc/install.texi (Prerequisites): Add note that D front end now
+ requires GDC installed in order to bootstrap.
+ (Building): Add D compiler section, referencing prerequisites.
+
+2021-12-01 Jakub Jelinek <jakub@redhat.com>
+
+ * config/i386/x86-tune.def (X86_TUNE_SCHEDULE,
+ X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY,
+ X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Formatting fixes.
+ (X86_TUNE_USE_GATHER): Put m_GENERIC last for consistency.
+
+2021-12-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/102356
+ * rtl.h (simplify_context): Add assoc_count member and
+ max_assoc_count static member.
+ * simplify-rtx.c (simplify_associative_operation): Don't reassociate
+ more than max_assoc_count times within one outermost simplify_* call.
+ * dwarf2out.c (mem_loc_descriptor): Optimize binary operation
+ with both operands the same using DW_OP_dup.
+
+2021-12-01 Tamar Christina <tamar.christina@arm.com>
+
+ * match.pd: Move below pattern that rewrites to EQ, NE.
+ * tree.c (bitmask_inv_cst_vector_p): Correct do .. while indentation.
+
+2021-12-01 Siddhesh Poyarekar <siddhesh@gotplt.org>
+ Martin Liška <mliska@suse.cz>
+
+ PR tree-optimization/103456
+ * tree-object-size.c (merge_object_sizes): Update osi->changed
+ only if object_sizes_set succeeded.
+
+2021-11-30 liuhongt <hongtao.liu@intel.com>
+
+ PR target/103463
+ PR target/103484
+ * config/i386/i386.md (*x86_64_shld_1): Set_attr
+ length_immediate to 1.
+ (*x86_shld_1): Ditto.
+ (*x86_64_shrd_1): Ditto.
+ (*x86_shrd_1): Ditto.
+
+2021-11-30 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
+ Clarify diagnostic.
+ (altivec_resolve_new_overloaded_builtin): Likewise.
+
+2021-11-30 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/103267
+ * ipa-sra.c (scan_function): Also check ECF_LOOPING_CONST_OR_PURE flag.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/103494
+ * tree-vect-stmts.c (vect_get_gather_scatter_ops): Remove ncopies
+ argument and calculate ncopies from gs_info->offset_vectype
+ where necessary.
+ (vectorizable_store, vectorizable_load): Update accordingly.
+
+2021-11-30 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ * Makefile.in (GDC): New variable.
+ (GDCFLAGS): New variable.
+ * configure: Regenerate.
+ * configure.ac: Add call to ACX_PROG_GDC. Substitute GDCFLAGS.
+
+2021-11-30 Martin Liska <mliska@suse.cz>
+ Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/103449
+ * ipa-param-manipulation.c
+ (ipa_param_body_adjustments::prepare_debug_expressions): Be
+ careful about hash_map reallocating itself. Simpify a return
+ which always returns true.
+
+2021-11-30 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/103440
+ * gimple-range-fold.cc (fold_using_range::range_of_phi): Continue
+ normal param processing for equiv params.
+
+2021-11-30 Richard Biener <rguenther@suse.de>
+
+ * config/i386/i386.c (ix86_shift_rotate_cost): Remove
+ unreachable return.
+ * tree-chrec.c (evolution_function_is_invariant_rec_p):
+ Likewise.
+ * tree-if-conv.c (if_convertible_stmt_p): Likewise.
+ * tree-ssa-pre.c (fully_constant_expression): Likewise.
+ * tree-vrp.c (operand_less_p): Likewise.
+ * reload.c (reg_overlap_mentioned_for_reload_p): Remove
+ unreachable gcc_unreachable ().
+ * sel-sched-ir.h (bb_next_bb): Likewise.
+ * varasm.c (compare_constant): Likewise.
+
+2021-11-30 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103489
+ * tree-vect-loop.c (vectorizable_phi): Verify argument
+ vector type compatibility to mitigate bool pattern recog
+ bug.
+
+2021-11-30 Thomas Schwinge <thomas@codesourcery.com>
+
+ * omp-offload.c (oacc_loop_auto_partitions): Remove erroneous
+ "Orphan reductions cannot have gang partitioning" handling.
+
+2021-11-30 Thomas Schwinge <thomas@codesourcery.com>
+
+ * omp-offload.c (oacc_loop_process): Implement "gang reduction on
+ an orphan loop" checking.
+
+2021-11-30 Cesar Philippidis <cesar@codesourcery.com>
+ Thomas Schwinge <thomas@codesourcery.com>
+
+ * omp-general.h (enum oacc_loop_flags): Add OLF_REDUCTION enum.
+ * omp-low.c (lower_oacc_head_mark): Use it to mark OpenACC
+ reductions.
+ * omp-offload.c (oacc_loop_auto_partitions): Don't assign gang
+ level parallelism to orphan reductions.
+
+2021-11-30 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/103451
+ * range-op.cc (operator_div::wi_fold): Remove
+ can_throw_non_call_exceptions special case.
+ * tree-ssa-sink.c (sink_code_in_bb): Same.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vect-slp.c (arg1_arg4_map): New variable.
+ (vect_get_operand_map): Handle IFN_MASK_GATHER_LOAD.
+ (vect_build_slp_tree_1): Likewise.
+ (vect_build_slp_tree_2): Likewise.
+ * tree-vect-stmts.c (vectorizable_load): Expect the mask to be
+ the last SLP child node rather than the first.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-if-conv.c: Include tree-eh.h.
+ (predicate_statements): Remove pe argument. Don't hoist
+ statements here.
+ (combine_blocks): Remove pe argument.
+ (ifcvt_available_on_edge_p, ifcvt_can_hoist): New functions.
+ (ifcvt_hoist_invariants): Likewise.
+ (tree_if_conversion): Update call to combine_blocks. Call
+ ifcvt_hoist_invariants after VN.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/102467
+ * doc/sourcebuild.texi (vect_gather_load_ifn): Document.
+ * tree-vect-data-refs.c (vect_analyze_data_ref_dependence):
+ Commonize safelen handling. Punt for anything involving
+ gathers and scatters unless safelen says otherwise.
+ * tree-vect-slp.c (arg1_map): New variable.
+ (vect_get_operand_map): Handle IFN_GATHER_LOAD.
+ (vect_build_slp_tree_1): Likewise.
+ (vect_build_slp_tree_2): Likewise.
+ (compatible_calls_p): If vect_get_operand_map returns nonnull,
+ check that any skipped arguments are equal.
+ (vect_slp_analyze_node_operations_1): Tighten reduction check.
+ * tree-vect-stmts.c (check_load_store_for_partial_vectors): Take
+ an ncopies argument.
+ (vect_get_gather_scatter_ops): Take slp_node and ncopies arguments.
+ Handle SLP nodes.
+ (vectorizable_store, vectorizable_load): Adjust accordingly.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * gimple.h (gimple_num_args, gimple_arg, gimple_arg_ptr): New
+ functions.
+ * tree-vect-slp.c (cond_expr_maps, arg2_map): New variables.
+ (vect_get_operand_map): New function.
+ (vect_get_and_check_slp_defs): Fix outdated comment.
+ Use vect_get_operand_map and new gimple argument accessors.
+ (vect_build_slp_tree_2): Likewise.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vect-slp.c (vect_build_slp_tree_1): Use code_helper
+ to record the operations performed by statements, only using
+ CALL_EXPR for things that don't map to built-in or internal
+ functions. For shifts, require all shift amounts to be equal
+ if optab_vector is not supported but optab_scalar is.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vect-data-refs.c (vect_check_gather_scatter): Continue
+ processing conversions if the current offset is a pointer.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vectorizer.h (vect_is_reduction): Use STMT_VINFO_REDUC_IDX.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genopinit.c (main): Turn supports_vec_gather_load and
+ supports_vec_scatter_store into signed char arrays and remove
+ supports_vec_gather_load_cached and supports_vec_scatter_store_cached.
+ * optabs-query.c (supports_vec_convert_optab_p): Add a mode parameter.
+ If the mode is not VOIDmode, test only for that mode.
+ (supports_vec_gather_load_p): Likewise.
+ (supports_vec_scatter_store_p): Likewise.
+ * optabs-query.h (supports_vec_gather_load_p): Likewise.
+ (supports_vec_scatter_store_p): Likewise.
+ * tree-vect-data-refs.c (vect_check_gather_scatter): Pass the
+ vector mode to supports_vec_gather_load_p and
+ supports_vec_scatter_store_p.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * internal-fn.c (commutative_binary_fn_p): Handle IFN_ADD_OVERFLOW
+ and IFN_MUL_OVERFLOW.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * internal-fn.c (commutative_binary_fn_p): Handle IFN_UBSAN_CHECK_ADD
+ and IFN_UBSAN_CHECK_MUL.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * internal-fn.c (commutative_binary_fn_p): Handle IFN_COMPLEX_MUL.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * gimple-fold.c: Include internal-fn.h.
+ (fold_stmt_1): If a function maps to an internal one, use
+ first_commutative_argument to canonicalize the order of
+ commutative arguments.
+ * gimple-match-head.c (gimple_resimplify2, gimple_resimplify3)
+ (gimple_resimplify4, gimple_resimplify5): Extend commutativity
+ checks to functions.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * doc/md.texi (reduc_fmin_scal_@var{m}): Document.
+ (reduc_fmax_scal_@var{m}): Likewise.
+ * optabs.def (reduc_fmax_scal_optab): New optab.
+ (reduc_fmin_scal_optab): Likewise
+ * internal-fn.def (REDUC_FMAX, REDUC_FMIN): New functions.
+ * tree-vect-loop.c (reduction_fn_for_scalar_code): Handle
+ CASE_CFN_FMAX and CASE_CFN_FMIN.
+ (neutral_op_for_reduction): Likewise.
+ (needs_fold_left_reduction_p): Likewise.
+ * config/aarch64/iterators.md (FMAXMINV): New iterator.
+ (fmaxmin): Handle UNSPEC_FMAXNMV and UNSPEC_FMINNMV.
+ * config/aarch64/aarch64-simd.md (reduc_<optab>_scal_<mode>): Fix
+ unspec mode.
+ (reduc_<fmaxmin>_scal_<mode>): New pattern.
+ * config/aarch64/aarch64-sve.md (reduc_<fmaxmin>_scal_<mode>):
+ Likewise.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * builtins.h (associated_internal_fn): Declare overload that
+ takes a (combined_cfn, return type) pair.
+ * builtins.c (associated_internal_fn): Split new overload out
+ of original fndecl version. Also provide an overload that takes
+ a (combined_cfn, return type) pair.
+ * internal-fn.h (commutative_binary_fn_p): Declare.
+ (commutative_ternary_fn_p): Likewise.
+ (associative_binary_fn_p): Likewise.
+ * internal-fn.c (commutative_binary_fn_p, commutative_ternary_fn_p):
+ New functions, split out from...
+ (first_commutative_argument): ...here.
+ (associative_binary_fn_p): New function.
+ * gimple-match.h (code_helper): Add a constructor that takes
+ internal functions.
+ (commutative_binary_op_p): Declare.
+ (commutative_ternary_op_p): Likewise.
+ (first_commutative_argument): Likewise.
+ (associative_binary_op_p): Likewise.
+ (canonicalize_code): Likewise.
+ (directly_supported_p): Likewise.
+ (get_conditional_internal_fn): Likewise.
+ (gimple_build): New overloads that takes a code_helper.
+ * gimple-fold.c (gimple_build): Likewise.
+ * gimple-match-head.c (commutative_binary_op_p): New function.
+ (commutative_ternary_op_p): Likewise.
+ (first_commutative_argument): Likewise.
+ (associative_binary_op_p): Likewise.
+ (canonicalize_code): Likewise.
+ (directly_supported_p): Likewise.
+ (get_conditional_internal_fn): Likewise.
+ * tree-vectorizer.h: Include gimple-match.h.
+ (neutral_op_for_reduction): Take a code_helper instead of a tree_code.
+ (needs_fold_left_reduction_p): Likewise.
+ (reduction_fn_for_scalar_code): Likewise.
+ (vect_can_vectorize_without_simd_p): Declare a nNew overload that takes
+ a code_helper.
+ * tree-vect-loop.c: Include case-cfn-macros.h.
+ (fold_left_reduction_fn): Take a code_helper instead of a tree_code.
+ (reduction_fn_for_scalar_code): Likewise.
+ (neutral_op_for_reduction): Likewise.
+ (needs_fold_left_reduction_p): Likewise.
+ (use_mask_by_cond_expr_p): Likewise.
+ (build_vect_cond_expr): Likewise.
+ (vect_create_partial_epilog): Likewise. Use gimple_build rather
+ than gimple_build_assign.
+ (check_reduction_path): Handle calls and operate on code_helpers
+ rather than tree_codes.
+ (vect_is_simple_reduction): Likewise.
+ (vect_model_reduction_cost): Likewise.
+ (vect_find_reusable_accumulator): Likewise.
+ (vect_create_epilog_for_reduction): Likewise.
+ (vect_transform_cycle_phi): Likewise.
+ (vectorizable_reduction): Likewise. Make more use of
+ lane_reduc_code_p.
+ (vect_transform_reduction): Use gimple_extract_op but expect
+ a tree_code for now.
+ (vect_can_vectorize_without_simd_p): New overload that takes
+ a code_helper.
+ * tree-vect-stmts.c (vectorizable_call): Handle reductions in
+ fully-masked loops.
+ * tree-vect-patterns.c (vect_mark_pattern_stmts): Use
+ gimple_extract_op when updating STMT_VINFO_REDUC_IDX.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * gimple-match.h (code_helper): Provide == and != overloads.
+ (code_helper::operator tree_code): Make explicit.
+ (code_helper::operator combined_fn): Likewise.
+ * gimple-match-head.c (convert_conditional_op): Use explicit
+ conversions where necessary.
+ (gimple_resimplify1, gimple_resimplify2, gimple_resimplify3): Likewise.
+ (maybe_push_res_to_seq, gimple_simplify): Likewise.
+ * gimple-fold.c (replace_stmt_with_simplification): Likewise.
+
+2021-11-30 Richard Sandiford <richard.sandiford@arm.com>
+
+ * gimple-match.h (code_helper): Add functions for querying whether
+ the code represents an internal_fn or a built_in_function.
+ Provide explicit conversion operators for both cases.
+ (gimple_extract_op): Declare.
+ * gimple-match-head.c (gimple_extract): New function, extracted from...
+ (gimple_simplify): ...here.
+ (gimple_extract_op): New function.
+
+2021-11-30 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR target/103274
+ * config/i386/i386.c (ix86_output_call_insn): Beef up comment about
+ nops emitted with SEH.
+ * config/i386/winnt.c (i386_pe_seh_unwind_emit): When switching to
+ the cold section, emit a nop before the directive if the previous
+ active instruction is a call.
+
+2021-11-30 Roger Sayle <roger@nextmovesoftware.com>
+ Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/100711
+ * config/i386/sse.md (define_split): New splitters to simplify
+ not;vec_duplicate;and as vec_duplicate;andn.
+
+2021-11-30 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/103485
+ * match.pd (-((int)x >> (prec - 1)) to (unsigned)x >> (prec - 1)):
+ Use VIEW_CONVERT_EXPR for vectors.
+
+2021-11-30 Richard Biener <rguenther@suse.de>
+
+ * cfgrtl.c (skip_insns_after_block): Refactor code to
+ be more easily readable.
+ * expr.c (op_by_pieces_d::run): Remove unreachable
+ assert.
+ * sched-deps.c (sched_analyze): Remove unreachable
+ gcc_unreachable.
+ * sel-sched-ir.c (in_same_ebb_p): Likewise.
+ * tree-ssa-alias.c (nonoverlapping_refs_since_match_p):
+ Remove unreachable code.
+ * tree-vect-slp.c (vectorize_slp_instance_root_stmt):
+ Refactor to avoid unreachable loop iteration.
+ * tree.c (walk_tree_1): Remove unreachable break.
+ * vec-perm-indices.c (vec_perm_indices::series_p): Remove
+ unreachable return.
+
+2021-11-30 Kewen Lin <linkw@linux.ibm.com>
+
+ PR target/102347
+ * config/rs6000/rs6000-call.c (rs6000_builtin_decl): Remove builtin mask
+ check.
+
+2021-11-30 Kewen Lin <linkw@linux.ibm.com>
+
+ * config/rs6000/rs6000.c
+ (rs6000_cost_data::update_target_cost_per_stmt): Adjust the way to
+ compute extra penalized cost. Remove useless parameter.
+ (rs6000_cost_data::rs6000_add_stmt_cost): Adjust the call to function
+ update_target_cost_per_stmt.
+
+2021-11-30 Kewen Lin <linkw@linux.ibm.com>
+
+ Revert:
+ 2021-11-17 Kewen Lin <linkw@linux.ibm.com>
+
+ * config/visium/visium.md (*add<mode>3_insn, *addsi3_insn, *addi3_insn,
+ *sub<mode>3_insn, *subsi3_insn, *subdi3_insn, *neg<mode>2_insn,
+ *negdi2_insn, *and<mode>3_insn, *ior<mode>3_insn, *xor<mode>3_insn,
+ *one_cmpl<mode>2_insn, *ashl<mode>3_insn, *ashr<mode>3_insn,
+ *lshr<mode>3_insn, *trunchiqi2_insn, *truncsihi2_insn,
+ *truncdisi2_insn, *extendqihi2_insn, *extendqisi2_insn,
+ *extendhisi2_insn, *extendsidi2_insn, *zero_extendqihi2_insn,
+ *zero_extendqisi2_insn, *zero_extendsidi2_insn): Fix split condition.
+
+2021-11-30 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/103467
+ * gimple-range-gori.cc (range_def_chain::register_dependency): Don't
+ use an object reference after a potential resize.
+
+2021-11-29 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/102811
+ * config/i386/i386.md (*movhi_internal): Introduce (*v,C) alternative.
+ Do not allocate non-GPR registers. Optimize xmm->xmm moves when
+ optimizing for size. Fix vpinsrw insn template.
+ (*movhf_internal): Fix pinsrw and pextrw insn templates for
+ AVX targets. Use sselog1 type instead of sselog. Optimize GPR moves.
+ Optimize xmm->xmm moves for TARGET_SSE_PARTIAL_REG_DEPENDENCY
+ and TARGET_SSE_SPLIT_REGS targets.
+
+2021-11-29 Eric Gallager <egallager@gcc.gnu.org>
+
+ * configure: Re-regenerate.
+
+2021-11-29 Eric Gallager <egallager@gcc.gnu.org>
+
+ PR other/103021
+ * Makefile.in: Substitute CTAGS, ETAGS, and CSCOPE
+ variables. Use ETAGS variable in TAGS target.
+ * configure: Regenerate.
+ * configure.ac: Allow CTAGS, ETAGS, and CSCOPE
+ variables to be overridden.
+
+2021-11-29 Paul A. Clarke <pc@us.ibm.com>
+
+ * config/rs6000/xmmintrin.h (_mm_movemask_ps): Use vec_extractm
+ when _ARCH_PWR10.
+ * config/rs6000/emmintrin.h (_mm_movemask_pd): Likewise.
+ (_mm_movemask_epi8): Likewise.
+
+2021-11-29 Richard Biener <rguenther@suse.de>
+
+ * read-rtl-function.c (function_reader::read_rtx_operand):
+ Return only after resetting m_in_call_function_usage.
+
+2021-11-29 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/i386/i386-expand.c (ix86_expand_v1ti_to_ti): Perform the
+ conversion via V2DImode using vec_extractv2didi on TARGET_SSE2.
+ * config/i386/sse.md (rotlv1ti3, rotrv1ti3): Change constraint
+ on QImode shift amounts from const_int_operand to general_operand.
+
+2021-11-29 Richard Biener <rguenther@suse.de>
+
+ * tree.h (reverse_storage_order_for_component_p): Remove
+ spurious gcc_unreachable.
+ * cfganal.c (dfs_find_deadend): Likewise.
+ * fold-const-call.c (fold_const_logb): Likewise.
+ (fold_const_significand): Likewise.
+ * gimple-ssa-store-merging.c (lhs_valid_for_store_merging_p):
+ Likewise.
+
+2021-11-29 Richard Biener <rguenther@suse.de>
+
+ * vec.c (qsort_chk): Do not return the void return value
+ from the noreturn qsort_chk_error.
+ * ccmp.c (expand_ccmp_expr_1): Remove unreachable return.
+ * df-scan.c (df_ref_equal_p): Likewise.
+ * dwarf2out.c (is_base_type): Likewise.
+ (add_const_value_attribute): Likewise.
+ * fixed-value.c (fixed_arithmetic): Likewise.
+ * gimple-fold.c (gimple_fold_builtin_fputs): Likewise.
+ * gimple-ssa-strength-reduction.c (stmt_cost): Likewise.
+ * graphite-isl-ast-to-gimple.c
+ (gcc_expression_from_isl_expr_op): Likewise.
+ (gcc_expression_from_isl_expression): Likewise.
+ * ipa-fnsummary.c (will_be_nonconstant_expr_predicate):
+ Likewise.
+ * lto-streamer-in.c (lto_input_mode_table): Likewise.
+
+2021-11-29 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102811
+ * config/i386/i386.c (inline_secondary_memory_needed): HImode
+ move between GPR and SSE registers is supported under
+ TARGET_SSE2 and above.
+ * config/i386/i386.md (extendhfsf2): Optimize expander.
+ (truncsfhf2): Ditto.
+ * config/i386/sse.md (sse2p4_1): Adjust attr for V8HFmode to
+ align with V8HImode.
+
+2021-11-29 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102811
+ PR target/103463
+ * config/i386/i386.c (ix86_secondary_reload): Without
+ TARGET_SSE4_1, General register is needed to move HImode from
+ sse register to memory.
+ * config/i386/sse.md (*vec_extrachf): Use %vpextrw instead of
+ pextrw in output templates.
+ * config/i386/i386.md (movhi_internal): Ditto, also fix typo of
+ MEM_P (operands[1]) and adjust mode/prefix/type attribute for
+ alternatives related to sse register.
+
+2021-11-29 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103458
+ * tree-ssa-dce.c (make_forwarders_with_degenerate_phis): Do not
+ create forwarders for blocks with abnormal predecessors.
+
+2021-11-29 Richard Biener <rguenther@suse.de>
+
+ * gimple-predicate-analysis.cc (can_be_invalidated_p):
+ Restore semantics to the one before the split from
+ tree-ssa-uninit.c.
+
+2021-11-28 Jan Hubicka <hubicka@ucw.cz>
+
+ * profile.c: Include sreal.h
+ (struct bb_stats): New.
+ (cmp_stats): New function.
+ (compute_branch_probabilities): Output bb stats.
+
+2021-11-28 Jan Hubicka <hubicka@ucw.cz>
+
+ * cfghooks.c: Include sreal.h, profile.h.
+ (profile_record_check_consistency): Fix checking of count counsistency;
+ record also dynamic mismatches.
+ * cfgrtl.c (rtl_account_profile_record): Similarly.
+ * tree-cfg.c (gimple_account_profile_record): Likewise.
+ * cfghooks.h (struct profile_record): Remove num_mismatched_freq_in,
+ num_mismatched_freq_out, turn time to double, add
+ dyn_mismatched_prob_out, dyn_mismatched_count_in,
+ num_mismatched_prob_out; remove num_mismatched_count_out.
+ * passes.c (account_profile_1): New function.
+ (account_profile_in_list): New function.
+ (pass_manager::dump_profile_report): Rewrite.
+ (execute_one_ipa_transform_pass): Check profile consistency after
+ running all passes.
+ (execute_all_ipa_transforms): Remove cfun test; record all transform
+ methods.
+ (execute_one_pass): Fix collecting of profile stats.
+
+2021-11-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/103431
+ * config/i386/i386.md (x86_64_shld, x86_shld, x86_64_shrd, x86_shrd):
+ Change insn pattern to accurately describe the instructions.
+ (*x86_64_shld_1, *x86_shld_1, *x86_64_shrd_1, *x86_shrd_1): New
+ define_insn patterns.
+ (*x86_64_shld_2, *x86_shld_2, *x86_64_shrd_2, *x86_shrd_2): New
+ define_insn_and_split patterns.
+ (*ashl<dwi>3_doubleword_mask, *ashl<dwi>3_doubleword_mask_1,
+ *<insn><dwi>3_doubleword_mask, *<insn><dwi>3_doubleword_mask_1,
+ ix86_rotl<dwi>3_doubleword, ix86_rotr<dwi>3_doubleword): Adjust
+ splitters for x86_{,64_}sh{l,r}d pattern changes.
+
+2021-11-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/103435
+ * gimple-ssa-store-merging.c (find_bswap_or_nop_finalize): Avoid UB if
+ n->range - rsize == 8, just clear both *cmpnop and *cmpxchg in that
+ case.
+
+2021-11-27 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/103441
+ * ipa-prop.c (ipcp_transform_function): Call
+ delete_unreachable_blocks_update_callgraph instead of returning
+ TODO_cleanup_cfg.
+
+2021-11-26 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ * tree-object-size.c (object_sizes_grow, object_sizes_release,
+ object_sizes_unknown_p, object_sizes_get, object_size_set_force,
+ object_sizes_set): New functions.
+ (addr_object_size, compute_builtin_object_size,
+ expr_object_size, call_object_size, unknown_object_size,
+ merge_object_sizes, plus_stmt_object_size,
+ cond_expr_object_size, collect_object_sizes_for,
+ check_for_plus_in_loops_1, init_object_sizes,
+ fini_object_sizes): Adjust.
+
+2021-11-26 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ * tree-object-size.c: New enum.
+ (object_sizes, computed, addr_object_size,
+ compute_builtin_object_size, expr_object_size, call_object_size,
+ merge_object_sizes, plus_stmt_object_size,
+ collect_object_sizes_for, init_object_sizes, fini_object_sizes,
+ object_sizes_execute): Replace magic numbers with enums.
+
+2021-11-26 Roger Sayle <roger@nextmovesoftware.com>
+
+ * tree-ssa-loop-ivopts.c (cand_value_at): Take a class
+ tree_niter_desc* argument instead of just a tree for NITER.
+ If we require the iv candidate value at the end of the final
+ loop iteration, try using the original loop bound as the
+ NITER for sufficiently simple loops.
+ (may_eliminate_iv): Update (only) call to cand_value_at.
+
+2021-11-26 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c (analyze_function): Drop parameter F and dump
+ cgraph node name rather than cfun name.
+ (modref_generate): Update.
+ (modref_summaries::insert):Update.
+ (modref_summaries_lto::insert):Update.
+ (pass_modref::execute):Update.
+ (ipa_merge_modref_summary_after_inlining): Improve combining of
+ ECF_FLAGS.
+
+2021-11-26 Jan Hubicka <jh@suse.cz>
+
+ PR ipa/102943
+ * ipa-modref.c (update_escape_summary_1): Fix handling of min_flags.
+
+2021-11-26 konglin1 <lingling.kong@intel.com>
+
+ PR target/102811
+ * config/i386/i386.c (ix86_can_change_mode_class): Allow 16 bit data in XMM register
+ for TARGET_SSE2.
+ * config/i386/i386.md (extendhfsf2): Add extenndhfsf2 for TARGET_F16C.
+ (extendhfdf2): Restrict extendhfdf for TARGET_AVX512FP16 only.
+ (*extendhf<mode>2): Rename from extendhf<mode>2.
+ (truncsfhf2): Likewise.
+ (truncdfhf2): Likewise.
+ (*trunc<mode>2): Likewise.
+
+2021-11-26 liuhongt <hongtao.liu@intel.com>
+
+ PR middle-end/103419
+ * match.pd: Fix typo, use the type of second parameter, not
+ first one.
+
+2021-11-25 Jan Hubicka <jh@suse.cz>
+
+ * ipa-cp.c (ipa_value_range_from_jfunc): Remove forgotten early return.
+
+2021-11-25 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR middle-end/103406
+ * match.pd (minus @0 @0): Check tree_expr_maybe_infinite_p.
+
+2021-11-25 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/103227
+ * ipa-prop.h (ipa_get_param): New overload. Move bits of the existing
+ one to the new one.
+ * ipa-param-manipulation.h (ipa_param_adjustments): New member
+ function get_updated_index_or_split.
+ * ipa-param-manipulation.c
+ (ipa_param_adjustments::get_updated_index_or_split): New function.
+ * ipa-prop.c (adjust_agg_replacement_values): Reimplement, add
+ capability to identify scalarized parameters and perform substitution
+ on them.
+ (ipcp_transform_function): Create descriptors earlier, handle new
+ return values of adjust_agg_replacement_values.
+
+2021-11-25 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::compute_ranges_defined): Remove.
+ (path_range_query::compute_ranges_in_block): Revert to bitmap order.
+ * gimple-range-path.h: Remove compute_ranges_defined.
+
+2021-11-25 Andrew Stubbs <ams@codesourcery.com>
+
+ PR target/103396
+ * config/gcn/gcn.c (move_callee_saved_registers): Ensure that the
+ number of spilled registers is counted correctly.
+
+2021-11-25 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-prop.h (ipa_node_params::ipa_node_params): Initialize
+ node_is_self_scc.
+
+2021-11-25 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/103359
+ * gimple-range-fold.cc (fold_using_range::range_of_phi): If arg is
+ equivalent to def, don't initially include it's range.
+
+2021-11-25 Jan Hubicka <hubicka@ucw.cz>
+
+ * tree-ssa-alias.c (ref_maybe_used_by_call_p_1): Do not check
+ gimple_static_chain.
+
+2021-11-25 Richard Biener <rguenther@suse.de>
+
+ * cgraphunit.c (symbol_table::output_weakrefs): Remove
+ unreachable init.
+ (get_alias_symbol): Remove now unused function.
+
+2021-11-25 Richard Biener <rguenther@suse.de>
+
+ * cfgrtl.c (rtl_verify_fallthru): Do not stop verifying
+ with fatal_insn.
+ (skip_insns_after_block): Remove unreachable break and continue.
+
+2021-11-25 Richard Biener <rguenther@suse.de>
+
+ * cfgexpand.c (label_rtx_for_bb): Remove dead loop construct.
+
+2021-11-25 Richard Biener <rguenther@suse.de>
+
+ * regset.h (REG_SET_EMPTY_P): New macro.
+ * cfgcleanup.c (thread_jump): Use REG_SET_EMPTY_P.
+
+2021-11-25 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Use @option for -Wuninitialized.
+
+2021-11-25 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/103254
+ * gimple-range-path.cc (path_range_query::compute_ranges): Move
+ exported boolean code...
+ (path_range_query::compute_imports): ...here.
+
+2021-11-25 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/103254
+ * gimple-range-path.cc (path_range_query::compute_ranges_defined): New
+ (path_range_query::compute_ranges_in_block): Move to
+ compute_ranges_defined.
+ * gimple-range-path.h (compute_ranges_defined): New.
+
+2021-11-25 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/103417
+ * match.pd ((X & Y) CMP 0): Only handle eq and ne. Commonalize
+ common tests.
+
+2021-11-25 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/103376
+ * gimple-ssa-store-merging.c (perform_symbolic_merge): For
+ BIT_IOR_EXPR, if masked1 && masked2 && masked1 != masked2, don't
+ punt, but set the corresponding result byte to MARKER_BYTE_UNKNOWN.
+ For BIT_XOR_EXPR similarly and if masked1 == masked2 and the
+ byte isn't MARKER_BYTE_UNKNOWN, set the corresponding result byte to
+ 0.
+
+2021-11-25 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/102611
+ * doc/invoke.texi (-Wcomma-subscript): Document that for
+ -std=c++20 the option isn't enabled by default with -Wno-deprecated
+ but for -std=c++23 it is.
+
+2021-11-24 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c (implicit_eaf_flags_for_edge_and_arg): Break out from...
+ (modref_merge_call_site_flags): ... here.
+ (ipa_merge_modref_summary_after_inlining): Use it.
+
+2021-11-24 Thomas Schwinge <thomas@codesourcery.com>
+
+ * cfgloop.c (verify_loop_structure): Reduce scope of
+ 'class loop *loop' variable.
+ * ipa-fnsummary.c (analyze_function_body): Likewise.
+ * loop-init.c (fix_loop_structure): Likewise.
+ * loop-invariant.c (calculate_loop_reg_pressure): Likewise.
+ * predict.c (predict_loops): Likewise.
+ * tree-loop-distribution.c (loop_distribution::execute): Likewise.
+ * tree-vectorizer.c (pass_vectorize::execute): Likewise.
+
+2021-11-24 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/103231
+ * gimple-range.cc (gimple_ranger::gimple_ranger): Create stmt stack.
+ (gimple_ranger::gimple_ranger): Delete stmt stack.
+ (gimple_ranger::range_of_stmt): Process depenedencies if they have no
+ global cache entry.
+ (gimple_ranger::prefill_name): New.
+ (gimple_ranger::prefill_stmt_dependencies): New.
+ * gimple-range.h (class gimple_ranger): Add prototypes.
+
+2021-11-24 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-cache.cc (ranger_cache::get_global_range): Always
+ return a range, return if it came from the cache or not.
+ (get_non_stale_global_range): Rename to get_global_range, and return
+ the temporal state in a flag.
+ * gimple-range-cache.h (get_non_stale_global_range): Rename and adjust.
+ * gimple-range.cc (gimple_ranger::range_of_expr): No need to query
+ get_global_range.
+ (gimple_ranger::range_of_stmt): Adjust for global cache temporal state
+ returned in a flag.
+
+2021-11-24 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range.cc (gimple_ranger::range_on_edge): Call trailer when
+ a constant is encountered to terminate the trace.
+
+2021-11-24 Maciej W. Rozycki <macro@embecosm.com>
+
+ PR middle-end/103059
+ * reload.c (find_reloads_address_1): Also accept the ASHIFT form
+ of indexed addressing.
+ (find_reloads): Adjust accordingly.
+
+2021-11-24 Richard Biener <rguenther@suse.de>
+ Jan Hubicka <jh@suse.cz>
+
+ PR tree-optimization/103168
+ * ipa-modref.h (struct modref_summary): Add load_accesses.
+ * ipa-modref.c (modref_summary::finalize): Initialize load_accesses.
+ * tree-ssa-sccvn.c (visit_reference_op_call): Use modref
+ info to walk the virtual use->def chain to CSE const/pure
+ function calls possibly reading from memory.
+
+2021-11-24 Thomas Schwinge <thomas@codesourcery.com>
+
+ PR middle-end/103244
+ * gimplify.c (gimplify_adjust_omp_clauses): Restore previous
+ OpenACC behavior.
+
+2021-11-24 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/103193
+ * match.pd: Avoid canonicalizing (le/ge @0 @0) to (eq @0 @0)
+ with NaNs and -ftrapping-math.
+
+2021-11-24 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/103384
+ * omp-general.c (omp_context_selector_matches): For ACCEL_COMPILER,
+ return 0 for kind(host) and continue for kind(nohost).
+
+2021-11-24 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/103365
+ * attribs.h (lookup_attribute): Allow attr_name to start with
+ underscore, as long as canonicalize_attr_name returns false.
+ (lookup_attribute_by_prefix): Don't call get_attribute_name twice.
+ * attribs.c (extract_attribute_substring): Reimplement using
+ canonicalize_attr_name.
+ (register_scoped_attribute): Change gcc_assert into
+ gcc_checking_assert, verify !canonicalize_attr_name rather than
+ that str.str doesn't start with '_'.
+
+2021-11-24 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/103376
+ * gimple-ssa-store-merging.c (perform_symbolic_merge): Add CODE
+ argument. If CODE is not BIT_IOR_EXPR, ensure that one of masked1
+ or masked2 is 0.
+ (find_bswap_or_nop_1, find_bswap_or_nop,
+ imm_store_chain_info::try_coalesce_bswap): Adjust
+ perform_symbolic_merge callers.
+
+2021-11-24 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-loop-ivopts.c (find_givs): Take loop body as
+ argument instead of re-computing it.
+ (find_interesting_uses): Likewise.
+ (find_induction_variables): Pass through loop body.
+ (tree_ssa_iv_optimize_loop): Pass down loop body.
+
+2021-11-24 Tamar Christina <tamar.christina@arm.com>
+
+ * tree-ssa-phiopt.c (spaceship_replacement): Handle new canonical
+ codegen.
+
+2021-11-24 Tamar Christina <tamar.christina@arm.com>
+
+ * tree.c (bitmask_inv_cst_vector_p): New.
+ * tree.h (bitmask_inv_cst_vector_p): New.
+ * match.pd: Use it in new bitmask compare pattern.
+
+2021-11-24 Jason Merrill <jason@redhat.com>
+
+ * timevar.h (class auto_cond_timevar): New.
+
+2021-11-24 Hongtao Liu <hongtao.liu@intel.com>
+ H.J. Lu <hongjiu.lu@intel.com>
+
+ PR tree-optimization/103194
+ * match.pd (gimple_nop_atomic_bit_test_and_p): Extended to
+ match truncation.
+ * tree-ssa-ccp.c (gimple_nop_convert): Declare.
+ (optimize_atomic_bit_test_and): Enhance
+ optimize_atomic_bit_test_and to handle truncation.
+
+2021-11-23 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/88232
+ * Makefile.in (OBJS): Add gimple-warn-recursion.o.
+ * common.opt: Add -Winfinite-recursion.
+ * doc/invoke.texi (-Winfinite-recursion): Document.
+ * passes.def (pass_warn_recursion): Schedule a new pass.
+ * tree-pass.h (make_pass_warn_recursion): Declare.
+ * gimple-warn-recursion.c: New file.
+
+2021-11-23 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-call.c (rs6000_invalid_new_builtin): Change
+ error messages for ENB_P8V and ENB_P9V.
+
+2021-11-23 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-builtin-new.def: Add power6-64 stanza. Move
+ CMPB to power6-64 stanza.
+ * config/rs6000/rs6000-call.c (rs6000_invalid_new_builtin): Handle
+ ENB_P6_64 case.
+ (rs6000_new_builtin_is_supported): Likewise.
+ (rs6000_expand_new_builtin): Likewise. Clean up formatting.
+ (rs6000_init_builtins): Handle ENB_P6_64 case.
+ * config/rs6000/rs6000-gen-builtins.c (bif_stanza): Add BSTZ_P6_64.
+ (stanza_map): Add entry mapping power6-64 to BSTZ_P6_64.
+ (enable_string): Add "ENB_P6_64".
+ (write_decls): Add ENB_P6_64 to bif_enable enum.
+
+2021-11-23 Jan Hubicka <jh@suse.cz>
+
+ * ipa-modref-tree.h (struct modref_tree): Remove max_bases, max_refs
+ and max_accesses.
+ (modref_tree::modref_tree): Remove parametr.
+ (modref_tree::insert_base): Add max_bases parameter.
+ (modref_tree::insert): Add max_bases, max_refs, max_accesses
+ parameters.
+ (modref_tree::insert): New member function.
+ (modref_tree::merge): Add max_bases, max_refs, max_accesses
+ parameters.
+ (modref_tree::insert): New member function.
+ * ipa-modref-tree.c (test_insert_search_collapse): Update.
+ (test_merge): Update.
+ * ipa-modref.c (dump_records): Don't dump max_refs and max_bases.
+ (dump_lto_records): Likewise.
+ (modref_summary::finalize): Fix whitespace.
+ (get_modref_function_summary): Likewise.
+ (modref_access_analysis::record_access): Update.
+ (modref_access_analysis::record_access_lto): Update.
+ (modref_access_analysis::process_fnspec): Update.
+ (analyze_function): Update.
+ (modref_summaries::duplicate): Update.
+ (modref_summaries_lto::duplicate): Update.
+ (write_modref_records): Update.
+ (read_modref_records): Update.
+ (read_section): Update.
+ (propagate_unknown_call): Update.
+ (modref_propagate_in_scc): Update.
+ (ipa_merge_modref_summary_after_inlining): Update.
+
+2021-11-23 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Remove 2 more duplicite param descriptions.
+
+2021-11-23 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103361
+ * gimple-loop-jam.c (adjust_unroll_factor): Use lambda_int
+ for the dependence distance.
+ * tree-data-ref.c (print_lambda_vector): Properly print a lambda_int.
+
+2021-11-23 Jakub Jelinek <jakub@redhat.com>
+
+ * tree-inline.h (struct copy_body_data): Remove
+ transform_lang_insert_block member.
+ * tree-inline.c (remap_block): Don't call
+ id->transform_lang_insert_block.
+ (optimize_inline_calls, copy_gimple_seq_and_replace_locals,
+ tree_function_versioning, maybe_inline_call_in_expr,
+ copy_fn): Don't initialize id.transform_lang_insert_block.
+ * gimplify.c (gimplify_omp_loop): Likewise.
+
+2021-11-23 Jan Hubicka <hubicka@ucw.cz>
+
+ PR tree-optimization/103335
+ * tree-ssa-dse.c (valid_ao_ref_for_dse): Rename to ...
+ (valid_ao_ref_kill_for_dse): ... this; do not check that boundaries
+ are divisible by BITS_PER_UNIT.
+ (get_byte_aligned_range_containing_ref): New function.
+ (get_byte_aligned_range_contained_in_ref): New function.
+ (normalize_ref): Rename to ...
+ (get_byte_range): ... this one; handle accesses not aligned to byte
+ boundary; return range in bytes rater than updating ao_ref.
+ (clear_live_bytes_for_ref): Take write ref by reference; simplify using
+ get_byte_access.
+ (setup_live_bytes_from_ref): Likewise.
+ (clear_bytes_written_by): Update.
+ (live_bytes_read): Update.
+ (dse_classify_store): Simplify tech before live_bytes_read checks.
+
+2021-11-23 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/102216
+ * gimple-fold.c (fold_stmt_1): Add canonicalization
+ of "&MEM[ssa_n, CST]" to "ssa_n p+ CST", note this
+ can only be done if !in_place.
+
+2021-11-23 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/102431
+ * gimplify.c (replace_reduction_placeholders): Remove.
+ (note_no_context_vars): New function.
+ (gimplify_omp_loop): For OMP_PARALLEL's BIND_EXPR create a new
+ BLOCK. Use copy_tree_body_r with walk_tree instead of unshare_expr
+ and replace_reduction_placeholders for duplication of
+ OMP_CLAUSE_REDUCTION_{INIT,MERGE} expressions. Ensure all mentioned
+ automatic vars have DECL_CONTEXT set to non-NULL before doing so
+ and reset it afterwards for those vars and their corresponding
+ vars.
+
+2021-11-23 Haochen Gui <guihaoc@gcc.gnu.org>
+
+ PR target/100868
+ * config/rs6000/altivec.md (altivec_vreve<mode>2 for VEC_K): Use
+ xxbrq for v16qi, xxbrq + xxbrh for v8hi and xxbrq + xxbrw for v4si
+ or v4sf when p9_vector is set.
+ (altivec_vreve<mode>2 for VEC_64): Defined. Implemented by xxswapd.
+
+2021-11-23 Navid Rahimi <navidrahimi@microsoft.com>
+
+ PR tree-optimization/102232
+ * match.pd (x * (1 + y / x) - y) -> (x - y % x): New optimization.
+
+2021-11-23 Navid Rahimi <navidrahimi@microsoft.com>
+
+ PR tree-optimization/96779
+ * match.pd (-x == x) -> (x == 0): New optimization.
+
+2021-11-22 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR tree-optimization/98953
+ PR tree-optimization/103345
+ * gimple-ssa-store-merging.c (find_bswap_or_nop_1): Handle
+ BIT_XOR_EXPR and PLUS_EXPR the same as BIT_IOR_EXPR.
+ (pass_optimize_bswap::execute): Likewise.
+
+2021-11-22 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Remove duplicate documentation for 3 params.
+
+2021-11-22 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103351
+ * tree-ssa-dce.c (sort_phi_args): Sort after e->dest_idx as
+ second key.
+
+2021-11-22 liuhongt <hongtao.liu@intel.com>
+
+ PR target/103275
+ * config/i386/constraints.md (Bk): New
+ define_memory_constraint.
+ * config/i386/i386-protos.h (ix86_gpr_tls_address_pattern_p):
+ Declare.
+ * config/i386/i386.c (ix86_gpr_tls_address_pattern_p): New
+ function.
+ * config/i386/i386.md (*movsi_internal): Don't allow
+ mask/sse/mmx move in TLS code sequences.
+ (*movdi_internal): Ditto.
+
+2021-11-22 Kewen Lin <linkw@linux.ibm.com>
+
+ * config/xtensa/xtensa.md (movdi_internal, movdf_internal): Fix split
+ condition.
+
+2021-11-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/101180
+ * config/i386/i386-options.c (ix86_valid_target_attribute_p): If
+ fndecl already has DECL_FUNCTION_SPECIFIC_TARGET, use that as base
+ instead of target_option_default_node.
+
+2021-11-21 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103227
+ * ipa-modref.c (parm_map_for_arg): Rename to ...
+ (parm_map_for_ptr): .. this one; handle static chain and calls to
+ malloc functions.
+ (modref_access_analysis::get_access): Use parm_map_for_ptr.
+ (modref_access_analysis::process_fnspec): Update.
+ (modref_access_analysis::analyze_load): Update.
+ (modref_access_analysis::analyze_store): Update.
+
+2021-11-21 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c (ignore_nondeterminism_p): Move earlier in source
+ code.
+ (ignore_retval_p): Likewise.
+ (ignore_stores_p): Likewise.
+ (parm_map_for_arg): Likewise.
+ (class modref_access_analysis): New class.
+ (modref_access_analysis::set_side_effects): New member function.
+ (modref_access_analysis::set_nondeterministic): New member function.
+ (get_access): Turn to ...
+ (modref_access_analysis::get_access): ... this one.
+ (record_access): Turn to ...
+ (modref_access_analysis::record_access): ... this one.
+ (record_access_lto): Turn to ...
+ (modref_access_analysis::record_access_lto): ... This one.
+ (record_access_p): Turn to ...
+ (modref_access_analysis::record_access_p): ... This one
+ (modref_access_analysis::record_unknown_load): New member function.
+ (modref_access_analysis::record_unknown_store): New member function.
+ (get_access_for_fnspec): Turn to ...
+ (modref_access_analysis::get_access_for_fnspec): ... this one.
+ (merge_call_side_effects): Turn to ...
+ (moderf_access_analysis::merge_call_side_effects): Turn to ...
+ (collapse_loads): Move later in source code.
+ (collapse_stores): Move later in source code.
+ (process_fnspec): Turn to ...
+ (modref_access_analysis::process_fnspec): ... this one.
+ (analyze_call): Turn to ...
+ (modref_access_analysis::analyze_call): ... this one.
+ (struct summary_ptrs): Remove.
+ (analyze_load): Turn to ...
+ (modref_access_analysis::analyze_load): ... this one.
+ (analyze_store): Turn to ...
+ (modref_access_analysis::analyze_store): ... this one.
+ (analyze_stmt): Turn to ...
+ (modref_access_analysis::analyze_stmt): ... This one.
+ (remove_summary): Remove.
+ (modref_access_analysis::propagate): Break out from ...
+ (modref_access_analysis::analyze): Break out from ...
+ (analyze_function): ... here.
+
+2021-11-21 Roger Sayle <roger@nextmovesoftware.com>
+ Robin Dapp <rdapp@linux.ibm.com>
+
+ PR target/102117
+ * tree-ssa-math-opts.c (convert_mult_to_widen): Recognize
+ signed WIDEN_MULT_EXPR if the target supports umul_widen_optab.
+
+2021-11-20 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103052
+ * ipa-modref.c (ignore_nondeterminism_p): Allow looping pure/cont.
+ (merge_call_side_effects): Improve debug output.
+
+2021-11-20 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103052
+ * ipa-pure-const.c (propagate_pure_const): Fix merging of loping flag.
+
+2021-11-20 Jeff Law <jeffreyalaw@gmail.com>
+
+ PR tree-optimization/103226
+ * config/bfin/bfin.md (doloop pattern, splitter and expander): Clobber
+ CC.
+
+2021-11-20 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/103220
+ * match.pd ((type) X bitop CST): Don't check if CST
+ fits into the type if only the sign changes.
+
+2021-11-20 Alexandre Oliva <oliva@adacore.com>
+
+ PR tree-optimization/102988
+ * gimple-harden-conditionals.cc (detach_value): Copy SSA_NAME
+ without decl sharing.
+
+2021-11-19 Iain Sandoe <iain@sandoe.co.uk>
+
+ * doc/invoke.texi: Remove whitespace after an @option.
+
+2021-11-19 Paul A. Clarke <pc@us.ibm.com>
+
+ * config/rs6000/emmintrin.h (_mm_sad_epu8): Use vec_absd when
+ _ARCH_PWR9, optimize vec_sum2s when LE.
+
+2021-11-19 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR target/80556
+ * config/darwin-driver.c (darwin_driver_init): Handle exported
+ symbols and symbol lists (suppress automatic export of the TLS
+ symbols).
+ * config/darwin.c (darwin_rename_builtins): Remove workaround.
+ * config/darwin.h (LINK_GCC_C_SEQUENCE_SPEC): Likewise.
+ (REAL_LIBGCC_SPEC): Handle revised library uses.
+ * config/darwin.opt (nodefaultexport): New.
+ * config/i386/darwin.h (PR80556_WORKAROUND): Remove.
+ * config/i386/darwin32-biarch.h (PR80556_WORKAROUND): Likewise.
+ * config/i386/darwin64-biarch.h (PR80556_WORKAROUND): Likewise.
+
+2021-11-19 Martin Jambor <mjambor@suse.cz>
+
+ * opts.c (default_options_table): Switch off
+ flag_semantic_interposition at Ofast.
+ * doc/invoke.texi (Optimize Options): Document that Ofast switches off
+ -fsemantic-interposition.
+
+2021-11-19 Jan Hubicka <hubicka@ucw.cz>
+
+ * tree-ssa-alias.c (ref_maybe_used_by_call_p_1): Do not guard modref
+ by !gimple_call_chain.
+
+2021-11-19 Martin Sebor <msebor@redhat.com>
+
+ PR c++/33925
+ PR c/102867
+ * doc/invoke.texi (-Waddress): Update.
+
+2021-11-19 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/103254
+ * gimple-range-gori.cc (range_def_chain::get_def_chain): Limit the
+ depth for all statements with multple ssa names.
+
+2021-11-19 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * config/s390/s390.md (define_peephole2): Variable insn points
+ to the first matched insn. Use peep2_next_insn(1) to refer to
+ the second matched insn.
+
+2021-11-19 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/103311
+ PR target/103330
+ * tree-vect-slp-patterns.c (vect_validate_multiplication): Fix CONJ
+ test to new codegen.
+ (complex_mul_pattern::matches): Move check downwards.
+
+2021-11-19 Martin Liska <mliska@suse.cz>
+
+ Revert:
+ 2021-11-19 Martin Liska <mliska@suse.cz>
+
+ * cfgexpand.c (pass_expand::execute): Use option directly.
+ * function.c (allocate_struct_function): Likewise.
+ * gimple-low.c (lower_function_body): Likewise.
+ (lower_stmt): Likewise.
+ * gimple-ssa-backprop.c (backprop::prepare_change): Likewise.
+ * ipa-param-manipulation.c (ipa_param_adjustments::modify_call): Likewise.
+ * ipa-split.c (split_function): Likewise.
+ * lto-streamer-in.c (input_function): Likewise.
+ * sese.c (sese_insert_phis_for_liveouts): Likewise.
+ * ssa-iterators.h (num_imm_uses): Likewise.
+ * tree-cfg.c (make_blocks): Likewise.
+ (gimple_merge_blocks): Likewise.
+ * tree-inline.c (tree_function_versioning): Likewise.
+ * tree-loop-distribution.c (generate_loops_for_partition): Likewise.
+ * tree-sra.c (analyze_access_subtree): Likewise.
+ * tree-ssa-dce.c (remove_dead_stmt): Likewise.
+ * tree-ssa-loop-ivopts.c (remove_unused_ivs): Likewise.
+ * tree-ssa-phiopt.c (spaceship_replacement): Likewise.
+ * tree-ssa-reassoc.c (reassoc_remove_stmt): Likewise.
+ * tree-ssa-tail-merge.c (tail_merge_optimize): Likewise.
+ * tree-ssa-threadedge.c (propagate_threaded_block_debug_into): Likewise.
+ * tree-ssa.c (gimple_replace_ssa_lhs): Likewise.
+ (target_for_debug_bind): Likewise.
+ (insert_debug_temp_for_var_def): Likewise.
+ (insert_debug_temps_for_defs): Likewise.
+ (reset_debug_uses): Likewise.
+ * tree-ssanames.c (release_ssa_name_fn): Likewise.
+ * tree-vect-loop-manip.c (adjust_vec_debug_stmts): Likewise.
+ (adjust_debug_stmts): Likewise.
+ (adjust_phi_and_debug_stmts): Likewise.
+ (vect_do_peeling): Likewise.
+ * tree-vect-loop.c (vect_transform_loop_stmt): Likewise.
+ (vect_transform_loop): Likewise.
+ * tree.h (MAY_HAVE_DEBUG_MARKER_STMTS): Remove
+ (MAY_HAVE_DEBUG_BIND_STMTS): Remove.
+ (MAY_HAVE_DEBUG_STMTS): Use options directly.
+
+2021-11-19 Giuliano Belinassi <gbelinassi@suse.de>
+
+ * gcc.c (process_command): Skip dumpdir override if file is a
+ not_actual_file_p.
+ * doc/invoke.texi: Update -dumpdir documentation.
+
+2021-11-19 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/103314
+ * match.pd ((type) X op CST): Restrict the equal
+ TYPE_PRECISION case to GIMPLE only.
+
+2021-11-19 Martin Liska <mliska@suse.cz>
+
+ PR ipa/103230
+ * ipa-modref-tree.h (struct modref_parm_map): Add default
+ constructor.
+ * ipa-modref.c (ipa_merge_modref_summary_after_inlining): Use it.
+
+2021-11-19 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/103248
+ * tree-eh.c (operation_could_trap_helper_p): Properly handle
+ fixed-point RDIV_EXPR.
+
+2021-11-19 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102436
+ * tree-ssa-loop-im.c (execute_sm_if_changed): Add mode
+ to just create the if structure and return the then block.
+ (execute_sm): Add flag to indicate the var will re-use
+ another flag var.
+ (hoist_memory_references): Support a single conditional
+ block with all stores as special case.
+
+2021-11-19 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/103317
+ * tree-ssa-phiopt.c (minmax_replacement): For the non empty
+ middle bb case, check to make sure it has a single predecessor.
+
+2021-11-19 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/103257
+ * match.pd
+ ((m1 >/</>=/<= m2) * d -> (m1 >/</>=/<= m2) ? d : 0):
+ Disable until !canonicalize_math_p ().
+
+2021-11-19 Marek Polacek <polacek@redhat.com>
+
+ PR c++/19808
+ PR c++/96121
+ * doc/invoke.texi: Update documentation for -Wuninitialized.
+ * tree.c (stabilize_reference): Set location.
+
+2021-11-19 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102543
+ * config/i386/x86-tune-costs.h (skylake_cost): Reduce cost of
+ storing 256/512-bit SSE register to be equal to cost of
+ unaligned store to avoid odd alignment peeling.
+ (icelake_cost): Ditto.
+
+2021-11-18 David Edelsohn <dje.gcc@gmail.com>
+
+ * config/rs6000/predicates.md (current_file_function_operand):
+ Add flag_semantic_interposition to call of decl_replaceable_p.
+
+2021-11-18 Martin Liska <mliska@suse.cz>
+
+ * ipa-modref.c (analyze_function): Do not execute the code
+ only if dump_file != NULL.
+
+2021-11-18 Martin Liska <mliska@suse.cz>
+
+ * ipa-modref.c (analyze_function): Use fnode instead of repeated
+ cgraph_node::get (current_function_decl).
+
+2021-11-18 Jan Hubicka <hubicka@ucw.cz>
+
+ * cgraph.c (cgraph_node::get_availability): Update call of
+ decl_replaceable_p.
+ (cgraph_node::verify_node): Verify that semantic_interposition flag
+ is set correclty.
+ * cgraph.h: (symtab_node): Add semantic_interposition flag.
+ * cgraphclones.c (set_new_clone_decl_and_node_flags): Clear
+ semantic_interposition flag.
+ * cgraphunit.c (cgraph_node::finalize_function): Set
+ semantic_interposition flag.
+ (cgraph_node::add_new_function): Likewise.
+ (varpool_node::finalize_decl): Likewise.
+ (cgraph_node::create_wrapper): Likewise.
+ * common.opt (fsemantic-interposition): Turn to optimization node.
+ * lto-cgraph.c (lto_output_node): Stream semantic_interposition.
+ (lto_output_varpool_node): Likewise.
+ (input_overwrite_node): Likewise.
+ (input_varpool_node): Likewise.
+ * symtab.c (symtab_node::dump_base): Dump new flag.
+ * varasm.c (decl_replaceable_p): Add semantic_interposition_p
+ parameter.
+ * varasm.h (decl_replaceable_p): Update declaration.
+ * varpool.c (varpool_node::ctor_useable_for_folding_p):
+ Use semantic_interposition flag.
+ (varpool_node::get_availability): Likewise.
+ (varpool_node::create_alias): Copy semantic_interposition flag.
+
+2021-11-18 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103266
+ * ipa-modref.c (modref_eaf_analysis::merge_call_lhs_flags): Unused
+ parameter may still be returned.
+ (modref_eaf_analysis::analyze_ssa_name): Call merge_call_lhs_flags
+ even for unused function args.
+
+2021-11-18 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/103311
+ * tree-vect-slp-patterns.c (complex_mul_pattern::matches,
+ complex_fms_pattern::matches): Check for multiplications.
+
+2021-11-18 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/102952
+ * config/i386/i386.c (ix86_output_jmp_thunk_or_indirect): Emit
+ CS prefix for -mindirect-branch-cs-prefix.
+ (ix86_output_indirect_branch_via_reg): Likewise.
+ * config/i386/i386.opt: Add -mindirect-branch-cs-prefix.
+ * doc/invoke.texi: Document -mindirect-branch-cs-prefix.
+
+2021-11-18 David Edelsohn <dje.gcc@gmail.com>
+
+ * config/rs6000/driver-rs6000.c (detect_processor_aix): Add
+ power10.
+
+2021-11-18 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/103253
+ * tree-ssa-math-opts.c (convert_mult_to_fma): Check for LHS.
+
+2021-11-18 Matthias Kretz <m.kretz@gsi.de>
+
+ * doc/extend.texi: Document __builtin_assoc_barrier.
+
+2021-11-18 Martin Liska <mliska@suse.cz>
+
+ * cfgexpand.c (pass_expand::execute): Use option directly.
+ * function.c (allocate_struct_function): Likewise.
+ * gimple-low.c (lower_function_body): Likewise.
+ (lower_stmt): Likewise.
+ * gimple-ssa-backprop.c (backprop::prepare_change): Likewise.
+ * ipa-param-manipulation.c (ipa_param_adjustments::modify_call): Likewise.
+ * ipa-split.c (split_function): Likewise.
+ * lto-streamer-in.c (input_function): Likewise.
+ * sese.c (sese_insert_phis_for_liveouts): Likewise.
+ * ssa-iterators.h (num_imm_uses): Likewise.
+ * tree-cfg.c (make_blocks): Likewise.
+ (gimple_merge_blocks): Likewise.
+ * tree-inline.c (tree_function_versioning): Likewise.
+ * tree-loop-distribution.c (generate_loops_for_partition): Likewise.
+ * tree-sra.c (analyze_access_subtree): Likewise.
+ * tree-ssa-dce.c (remove_dead_stmt): Likewise.
+ * tree-ssa-loop-ivopts.c (remove_unused_ivs): Likewise.
+ * tree-ssa-phiopt.c (spaceship_replacement): Likewise.
+ * tree-ssa-reassoc.c (reassoc_remove_stmt): Likewise.
+ * tree-ssa-tail-merge.c (tail_merge_optimize): Likewise.
+ * tree-ssa-threadedge.c (propagate_threaded_block_debug_into): Likewise.
+ * tree-ssa.c (gimple_replace_ssa_lhs): Likewise.
+ (target_for_debug_bind): Likewise.
+ (insert_debug_temp_for_var_def): Likewise.
+ (insert_debug_temps_for_defs): Likewise.
+ (reset_debug_uses): Likewise.
+ * tree-ssanames.c (release_ssa_name_fn): Likewise.
+ * tree-vect-loop-manip.c (adjust_vec_debug_stmts): Likewise.
+ (adjust_debug_stmts): Likewise.
+ (adjust_phi_and_debug_stmts): Likewise.
+ (vect_do_peeling): Likewise.
+ * tree-vect-loop.c (vect_transform_loop_stmt): Likewise.
+ (vect_transform_loop): Likewise.
+ * tree.h (MAY_HAVE_DEBUG_MARKER_STMTS): Remove
+ (MAY_HAVE_DEBUG_BIND_STMTS): Remove.
+ (MAY_HAVE_DEBUG_STMTS): Use options directly.
+
+2021-11-18 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103277
+ * tree-ssa-dse.c (need_ab_cleanup): New.
+ (dse_optimize_redundant_stores): Adjust.
+ (delete_dead_or_redundant_assignment): Get extra
+ need_ab_cleanup argument and set when abnormal cleanup is
+ needed.
+ (dse_optimize_call): Adjust.
+ (dse_optimize_stmt): Likewise.
+ (pass_dse::execute): Allocate and deallocate need_ab_cleanup.
+ Perform abnormal cleanup.
+ * tree-ssa-dse.h (delete_dead_or_redundant_assignment): Adjust.
+
+2021-11-18 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/i386-expand.c (ix86_expand_atomic_fetch_op_loop):
+ Adjust generated cfg to avoid infinite loop.
+
+2021-11-18 konglin1 <lingling.kong@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm512_mul_pch): Add alias for _mm512_fmul_pch.
+ (_mm512_mask_mul_pch): Likewise.
+ (_mm512_maskz_mul_pch): Likewise.
+ (_mm512_mul_round_pch): Likewise.
+ (_mm512_mask_mul_round_pch): Likewise.
+ (_mm512_maskz_mul_round_pch): Likewise.
+ (_mm512_cmul_pch): Likewise.
+ (_mm512_mask_cmul_pch): Likewise.
+ (_mm512_maskz_cmul_pch): Likewise.
+ (_mm512_cmul_round_pch): Likewise.
+ (_mm512_mask_cmul_round_pch): Likewise.
+ (_mm512_maskz_cmul_round_pch): Likewise.
+ (_mm_mul_sch): Likewise.
+ (_mm_mask_mul_sch): Likewise.
+ (_mm_maskz_mul_sch): Likewise.
+ (_mm_mul_round_sch): Likewise.
+ (_mm_mask_mul_round_sch): Likewise.
+ (_mm_maskz_mul_round_sch): Likewise.
+ (_mm_cmul_sch): Likewise.
+ (_mm_mask_cmul_sch): Likewise.
+ (_mm_maskz_cmul_sch): Likewise.
+ (_mm_cmul_round_sch): Likewise.
+ (_mm_mask_cmul_round_sch): Likewise.
+ (_mm_maskz_cmul_round_sch): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_mul_pch): Likewise.
+ (_mm_mask_mul_pch): Likewise.
+ (_mm_maskz_mul_pch): Likewise.
+ (_mm256_mul_pch): Likewise.
+ (_mm256_mask_mul_pch): Likewise.
+ (_mm256_maskz_mul_pch): Likewise.
+ (_mm_cmul_pch): Likewise.
+ (_mm_mask_cmul_pch): Likewise.
+ (_mm_maskz_cmul_pch): Likewise.
+ (_mm256_cmul_pch): Likewise.
+ (_mm256_mask_cmul_pch): Likewise.
+ (_mm256_maskz_cmul_pch): Likewise.
+
+2021-11-17 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/103228
+ PR tree-optimization/55177
+ * match.pd ((type) X bitop CST): Also do this
+ transformation for nop conversions.
+
+2021-11-17 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/102759
+ * gimple-array-bounds.cc (build_printable_array_type): Move...
+ * gimple-ssa-warn-access.cc (build_printable_array_type): Avoid
+ pathological function redeclarations that remove a previously
+ declared prototype.
+ Improve formatting of function arguments in informational notes.
+ * pointer-query.cc (build_printable_array_type): ...to here.
+ * pointer-query.h (build_printable_array_type): Declared.
+
+2021-11-17 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/102952
+ * config/i386/i386-opts.h (harden_sls): New enum.
+ * config/i386/i386.c (output_indirect_thunk): Mitigate against
+ SLS for function return.
+ (ix86_output_function_return): Likewise.
+ (ix86_output_jmp_thunk_or_indirect): Mitigate against indirect
+ branch.
+ (ix86_output_indirect_jmp): Likewise.
+ (ix86_output_call_insn): Likewise.
+ * config/i386/i386.opt: Add -mharden-sls=.
+ * doc/invoke.texi: Document -mharden-sls=.
+
+2021-11-17 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/103307
+ * config/i386/i386.c (ix86_code_end): Remove "%!" before ret.
+ (ix86_output_function_return): Likewise.
+ * config/i386/i386.md (simple_return_pop_internal): Likewise.
+
+2021-11-17 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103246
+ * ipa-modref.c (read_modref_records): Fix streaminig in of every_access
+ flag.
+
+2021-11-17 Uroš Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.c (indirect_thunks_used): Redefine as HARD_REG_SET.
+ (ix86_code_end): Use TEST_HARD_REG_BIT on indirect_thunks_used.
+ (ix86_output_indirect_branch_via_reg): Use SET_HARD_REG_BIT
+ on indirect_thunks_used.
+ (ix86_output_indirect_function_return): Ditto.
+
+2021-11-17 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref-tree.c: Include cgraph.h and tree-streamer.h.
+ (modref_access_node::stream_out): New member function.
+ (modref_access_node::stream_in): New member function.
+ * ipa-modref-tree.h (modref_access_node::stream_out,
+ modref_access_node::stream_in): Declare.
+ * ipa-modref.c (modref_summary_lto::useful_p): Free useless kills.
+ (modref_summary_lto::dump): Dump kills.
+ (analyze_store): Record kills for LTO
+ (analyze_stmt): Likewise.
+ (modref_summaries_lto::duplicate): Duplicate kills.
+ (write_modref_records): Use new stream_out member function.
+ (read_modref_records): Likewise.
+ (modref_write): Stream out kills.
+ (read_section): Stream in kills
+ (remap_kills): New function.
+ (update_signature): Use it.
+
+2021-11-17 Uroš Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.h (LEGACY_SSE_REGNO_P): New predicate.
+ (SSE_REGNO_P): Use LEGACY_SSE_REGNO_P predicate.
+ * config/i386/i386.c (zero_all_vector_registers):
+ Use LEGACY_SSE_REGNO_P predicate.
+ (ix86_register_priority): Use REX_INT_REGNO_P, REX_SSE_REGNO_P
+ and EXT_REG_SSE_REGNO_P predicates.
+ (ix86_hard_regno_call_part_clobbered): Use REX_SSE_REGNO_P
+ and LEGACY_SSE_REGNO_P predicates.
+
+2021-11-17 Jason Merrill <jason@redhat.com>
+
+ * doc/invoke.texi (C++ Dialect Options): Document
+ -fimplicit-constexpr.
+
+2021-11-17 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/aarch64/aarch64-modes.def (VECTOR_MODE): New V8DI mode.
+ * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Handle
+ V8DImode.
+ * config/aarch64/iterators.md (define_mode_attr nunits): Add entry
+ for V8DI.
+
+2021-11-17 Martin Uecker <uecker@gcc.gnu.org>
+
+ PR c/91038
+ PR c/29970
+ * gimplify.c (gimplify_var_or_parm_decl): Update comment.
+ (gimplify_compound_lval): Gimplify base expression first.
+ (gimplify_target_expr): Add comment.
+
+2021-11-17 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/103192
+ * tree-ssa-loop-im.c (move_computations_worker): Use
+ reset_flow_sensitive_info instead of manually clearing
+ SSA_NAME_RANGE_INFO and do it for all SSA_NAMEs, not just ones
+ with integral types.
+
+2021-11-17 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/103255
+ * gimple-range-fold.cc (fold_using_range::range_of_address): Return
+ range_nonzero rather than unadjusted base's range. Formatting fixes.
+
+2021-11-17 Richard Sandiford <richard.sandiford@arm.com>
+
+ * doc/md.texi (cond_fmin@var{mode}, cond_fmax@var{mode}): Document.
+ * optabs.def (cond_fmin_optab, cond_fmax_optab): New optabs.
+ * internal-fn.def (COND_FMIN, COND_FMAX): New functions.
+ * internal-fn.c (first_commutative_argument): Handle them.
+ (FOR_EACH_COND_FN_PAIR): Likewise.
+ * match.pd (UNCOND_BINARY, COND_BINARY): Likewise.
+ * config/aarch64/aarch64-sve.md (cond_<fmaxmin><mode>): New
+ pattern.
+
+2021-11-17 Kewen Lin <linkw@linux.ibm.com>
+
+ * config/i386/i386.md (*add<dwi>3_doubleword, *addv<dwi>4_doubleword,
+ *addv<dwi>4_doubleword_1, *sub<dwi>3_doubleword,
+ *subv<dwi>4_doubleword, *subv<dwi>4_doubleword_1,
+ *add<dwi>3_doubleword_cc_overflow_1, *divmodsi4_const,
+ *neg<dwi>2_doubleword, *tls_dynamic_gnu2_combine_64_<mode>): Fix split
+ condition.
+
+2021-11-17 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/103288
+ * tree-ssa-phiopt.c (value_replacement): Return early if middle
+ block has more than one pred.
+
+2021-11-17 Kewen Lin <linkw@linux.ibm.com>
+
+ * config/visium/visium.md (*add<mode>3_insn, *addsi3_insn, *addi3_insn,
+ *sub<mode>3_insn, *subsi3_insn, *subdi3_insn, *neg<mode>2_insn,
+ *negdi2_insn, *and<mode>3_insn, *ior<mode>3_insn, *xor<mode>3_insn,
+ *one_cmpl<mode>2_insn, *ashl<mode>3_insn, *ashr<mode>3_insn,
+ *lshr<mode>3_insn, *trunchiqi2_insn, *truncsihi2_insn,
+ *truncdisi2_insn, *extendqihi2_insn, *extendqisi2_insn,
+ *extendhisi2_insn, *extendsidi2_insn, *zero_extendqihi2_insn,
+ *zero_extendqisi2_insn, *zero_extendsidi2_insn): Fix split condition.
+
+2021-11-17 Marek Polacek <polacek@redhat.com>
+
+ PR preprocessor/103026
+ * doc/invoke.texi: Document -Wbidi-chars.
+
+2021-11-17 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103246
+ * ipa-modref.c (ipa_merge_modref_summary_after_inlining): Fix clearing
+ of to_info_lto
+
+2021-11-16 Jan Hubicka <jh@suse.cz>
+
+ * ipa-modref.c (get_modref_function_summary): Declare.
+ * ipa-modref.h (get_modref_function_summary): New function.
+ * tree-ssa-dse.c (clear_live_bytes_for_ref): Break out from ...
+ (clear_bytes_written_by): ... here; also clear memory killed by
+ calls.
+
+2021-11-16 Iain Sandoe <iain@sandoe.co.uk>
+
+ * ggc-common.c (gt_pch_save): If we cannot find a suitable
+ memory segment for save, then error-out, do not try to
+ continue.
+ (gt_pch_restore): Save the existing line table, and when
+ the replacement is being read, use that when constructing
+ diagnostics.
+
+2021-11-16 Peter Bergner <bergner@linux.ibm.com>
+
+ PR target/102976
+ * config/rs6000/mma.md (*vsx_assemble_pair): Add early-clobber for
+ output operand.
+ (*mma_assemble_acc): Likewise.
+
+2021-11-16 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/102960
+ * gimple-fold.c (get_range_strlen): Take bitmap as an argument rather
+ than a pointer to it.
+ (get_range_strlen_tree): Same. Remove bitmap allocation. Use
+ an auto_bitmap.
+ (get_maxval_strlen): Use an auto_bitmap.
+ * tree-ssa-strlen.c (get_range_strlen_dynamic): Factor out PHI
+ handling...
+ (get_range_strlen_phi): ...into this function.
+ Avoid assuming maximum string length is constant
+ (printf_strlen_execute): Dump pointer query cache contents when
+ details are requisted.
+
+2021-11-16 Jason Merrill <jason@redhat.com>
+
+ * langhooks.h (struct lang_hooks): Adjust comment.
+ * print-tree.c (print_node): Also call print_xnode hook for
+ tcc_constant class.
+
+2021-11-16 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/103218
+ * match.pd: New pattern for "((type)(a<0)) << SIGNBITOFA".
+
+2021-11-16 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc.md (maddhisi4): Use a single move to accumulator.
+ (umaddhisi4): Likewise.
+ (machi): Update pattern.
+ (umachi): Likewise.
+
+2021-11-16 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102880
+ * tree-ssa-dce.c (sort_phi_args): New function.
+ (make_forwarders_with_degenerate_phis): Likewise.
+ (perform_tree_ssa_dce): Call
+ make_forwarders_with_degenerate_phis.
+
+2021-11-16 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102880
+ * tree-ssa-phiopt.c (tree_ssa_phiopt_worker): Push
+ single_pred (bb1) condition to places that really need it.
+ (match_simplify_replacement): Likewise.
+ (value_replacement): Likewise.
+ (replace_phi_edge_with_variable): Deal with extra edges
+ into the middle BB.
+
+2021-11-16 Martin Jambor <mjambor@suse.cz>
+
+ * cfgexpand.c (expand_gimple_basic_block): Use build_debug_expr_decl,
+ add a fixme note about the mode assignment perhaps being unnecessary.
+ * ipa-param-manipulation.c (ipa_param_adjustments::modify_call):
+ Likewise.
+ (ipa_param_body_adjustments::mark_dead_statements): Likewise.
+ (ipa_param_body_adjustments::reset_debug_stmts): Likewise.
+ * tree-inline.c (remap_ssa_name): Likewise.
+ (tree_function_versioning): Likewise.
+ * tree-into-ssa.c (rewrite_debug_stmt_uses): Likewise.
+ * tree-ssa-loop-ivopts.c (remove_unused_ivs): Likewise.
+ * tree-ssa.c (insert_debug_temp_for_var_def): Likewise.
+
+2021-11-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/103208
+ * omp-expand.c (expand_omp_build_cond): New function.
+ (expand_omp_for_init_counts, expand_omp_for_init_vars,
+ expand_omp_for_static_nochunk, expand_omp_for_static_chunk): Use it.
+
+2021-11-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/102009
+ * gimple-ssa-warn-access.cc (pass_waccess::check_alloc_size_call):
+ Punt if any of alloc_size arguments is out of bounds vs. number of
+ call arguments.
+
+2021-11-16 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/i386/i386.md (*bmi2_rorx<mode3>_1): Make conditional
+ on !optimize_function_for_size_p.
+ (*<any_rotate><mode>3_1): Add preferred_for_size attribute.
+ (define_splits): Conditionalize on !optimize_function_for_size_p.
+ (*bmi2_rorxsi3_1_zext): Likewise.
+ (*<any_rotate>si2_1_zext): Add preferred_for_size attribute.
+ (define_splits): Conditionalize on !optimize_function_for_size_p.
+
+2021-11-16 Jan Hubicka <jh@suse.cz>
+
+ PR ipa/103262
+ * ipa-modref.c (merge_call_side_effects): Fix uninitialized
+ access.
+
+2021-11-16 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/103245
+ * match.pd: Combine the abs pattern matching using multiplication.
+ Adding optional nop_convert too.
+
+2021-11-16 H.J. Lu <hjl.tools@gmail.com>
+
+ PR middle-end/103268
+ * tree-ssa-ccp.c (optimize_atomic_bit_test_and): Add a missing
+ return.
+
+2021-11-15 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ * gimple-fold.c (gimple_fold_builtin_strncat): Use ranges to
+ determine if it is safe to transform to strcat.
+ (gimple_fold_builtin_snprintf): Likewise.
+
+2021-11-15 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ * gimple-fold.c (known_lower): New function.
+ (gimple_fold_builtin_strncat_chk,
+ gimple_fold_builtin_memory_chk, gimple_fold_builtin_stxcpy_chk,
+ gimple_fold_builtin_stxncpy_chk,
+ gimple_fold_builtin_snprintf_chk,
+ gimple_fold_builtin_sprintf_chk): Use it.
+
+2021-11-15 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ * gimple-fold.c (dump_transformation): New function.
+ (gimple_fold_builtin_stxcpy_chk,
+ gimple_fold_builtin_stxncpy_chk): Use it. Simplify to
+ BUILT_IN_STRNCPY if return value is not used.
+
+2021-11-15 H.J. Lu <hjl.tools@gmail.com>
+
+ PR middle-end/103184
+ * tree-ssa-ccp.c (optimize_atomic_bit_test_and): Check optab
+ before transforming equivalent, but slighly different cases to
+ their canonical forms.
+
+2021-11-15 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR fortran/102992
+ * config/darwin.h (TARGET_DTORS_FROM_CXA_ATEXIT): New.
+ * doc/tm.texi: Regenerated.
+ * doc/tm.texi.in: Add TARGET_DTORS_FROM_CXA_ATEXIT hook.
+ * ipa.c (cgraph_build_static_cdtor_1): Return the built
+ function decl.
+ (build_cxa_atexit_decl): New.
+ (build_dso_handle_decl): New.
+ (build_cxa_dtor_registrations): New.
+ (compare_cdtor_tu_order): New.
+ (build_cxa_atexit_fns): New.
+ (ipa_cdtor_merge): If dtors_from_cxa_atexit is set,
+ process the DTORs/CTORs accordingly.
+ (pass_ipa_cdtor_merge::gate): Also run if
+ dtors_from_cxa_atexit is set.
+ * target.def (dtors_from_cxa_atexit): New hook.
+
+2021-11-15 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config.in: Regenerate.
+ * configure: Regenerate.
+ * configure.ac: Test ld64 for -platform-version support.
+
+2021-11-15 Thomas Schwinge <thomas@codesourcery.com>
+
+ * diagnostic-spec.h (typedef xint_hash_t)
+ (typedef xint_hash_map_t): Replace with...
+ (typedef nowarn_map_t): ... this.
+ (nowarn_map): Adjust.
+ * diagnostic-spec.c (nowarn_map, suppress_warning_at): Likewise.
+
+2021-11-15 Thomas Schwinge <thomas@codesourcery.com>
+
+ * profile.c (branch_prob): Use 'location_hash' for
+ 'seen_locations'.
+
+2021-11-15 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/103207
+ * value-range.cc (irange::set): Drop overflow.
+
+2021-11-15 Jakub Jelinek <jakub@redhat.com>
+
+ * gimplify.c (optimize_target_teams): Only add OMP_CLAUSE_THREAD_LIMIT
+ to OMP_TARGET_CLAUSES if it isn't there already.
+
+2021-11-15 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::internal_range_of_expr):
+ Remove useless code.
+ (path_range_query::ssa_defined_in_bb): New.
+ (path_range_query::ssa_range_in_phi): Avoid fold_range call that
+ could trigger additional lookups.
+ Do not use the cache for ARGs defined in this block.
+ (path_range_query::compute_ranges_in_block): Use ssa_defined_in_bb.
+ (path_range_query::maybe_register_phi_relation): Same.
+ (path_range_query::range_of_stmt): Adjust comment.
+ * gimple-range-path.h (ssa_defined_in_bb): New.
+
+2021-11-15 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::internal_range_of_expr):
+ Default to global range if nothing found.
+
+2021-11-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103237
+ * tree-vect-loop.c (vect_is_simple_reduction): Fail for
+ double reductions with multiple inner loop LC PHI nodes.
+
+2021-11-15 Hongyu Wang <hongyu.wang@intel.com>
+
+ PR target/103069
+ * config/i386/i386-expand.c (ix86_expand_atomic_fetch_op_loop):
+ New expand function.
+ * config/i386/i386-options.c (ix86_target_string): Add
+ -mrelax-cmpxchg-loop flag.
+ (ix86_valid_target_attribute_inner_p): Likewise.
+ * config/i386/i386-protos.h (ix86_expand_atomic_fetch_op_loop):
+ New expand function prototype.
+ * config/i386/i386.opt: Add -mrelax-cmpxchg-loop.
+ * config/i386/sync.md (atomic_fetch_<logic><mode>): New expander
+ for SI,HI,QI modes.
+ (atomic_<logic>_fetch<mode>): Likewise.
+ (atomic_fetch_nand<mode>): Likewise.
+ (atomic_nand_fetch<mode>): Likewise.
+ (atomic_fetch_<logic><mode>): New expander for DI,TI modes.
+ (atomic_<logic>_fetch<mode>): Likewise.
+ (atomic_fetch_nand<mode>): Likewise.
+ (atomic_nand_fetch<mode>): Likewise.
+ * doc/invoke.texi: Document -mrelax-cmpxchg-loop.
+
+2021-11-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103219
+ * gimple-loop-jam.c (tree_loop_unroll_and_jam): Use single_exit
+ to determine the exit for the VN region.
+
+2021-11-15 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+
+ * tree-ssa-loop.c (pass_vectorize): Move to tree-vectorizer.c.
+ (pass_data_vectorize): Likewise.
+ (make_pass_vectorize): Likewise.
+ * tree-vectorizer.c (vectorize_loops): Merge with
+ pass_vectorize::execute and replace cfun occurences with fun param.
+ (adjust_simduid_builtins): Add fun param, replace cfun occurences with
+ fun, and adjust callers approrpiately.
+ (note_simd_array_uses): Likewise.
+ (vect_loop_dist_alias_call): Likewise.
+ (set_uid_loop_bbs): Likewise.
+ (vect_transform_loops): Likewise.
+ (try_vectorize_loop_1): Likewise.
+ (try_vectorize_loop): Likewise.
+
+2021-11-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/103205
+ * config/i386/sync.md (atomic_bit_test_and_set<mode>,
+ atomic_bit_test_and_complement<mode>,
+ atomic_bit_test_and_reset<mode>): Use OPTAB_WIDEN instead of
+ OPTAB_DIRECT.
+
+2021-11-15 Maciej W. Rozycki <macro@embecosm.com>
+
+ * config/vax/vax.c (vax_lra_p): New prototype and function.
+ (TARGET_LRA_P): Wire it.
+ * config/vax/vax.opt (mlra): New option.
+ * doc/invoke.texi (Option Summary, VAX Options): Document the
+ new option.
+
+2021-11-14 Jan Hubicka <jh@suse.cz>
+
+ * ipa-modref.h (struct modref_summary): Add nondeterministic
+ and calls_interposable flags.
+ * ipa-modref.c (modref_summary::modref_summary): Initialize new flags.
+ (modref_summary::useful_p): Check new flags.
+ (struct modref_summary_lto): Add nondeterministic and
+ calls_interposable flags.
+ (modref_summary_lto::modref_summary_lto): Initialize new flags.
+ (modref_summary_lto::useful_p): Check new flags.
+ (modref_summary::dump): Dump new flags.
+ (modref_summary_lto::dump): Dump new flags.
+ (ignore_nondeterminism_p): New function.
+ (merge_call_side_effects): Merge new flags.
+ (process_fnspec): Likewise.
+ (analyze_load): Volatile access is nondeterministic.
+ (analyze_store): Liekwise.
+ (analyze_stmt): Volatile ASM is nondeterministic.
+ (analyze_function): Clear new flags.
+ (modref_summaries::duplicate): Duplicate new flags.
+ (modref_summaries_lto::duplicate): Duplicate new flags.
+ (modref_write): Stream new flags.
+ (read_section): Stream new flags.
+ (propagate_unknown_call): Update new flags.
+ (modref_propagate_in_scc): Propagate new flags.
+ * tree-ssa-alias.c (ref_maybe_used_by_call_p_1): Check
+ calls_interposable.
+ * tree-ssa-structalias.c (determine_global_memory_access):
+ Likewise.
+
+2021-11-14 Maciej W. Rozycki <macro@embecosm.com>
+
+ * config/vax/vax.h (SET_RATIO): New macro.
+ * config/vax/vax.md (UNSPEC_SETMEM_FILL): New constant.
+ (setmemhi): New expander.
+ (setmemhi1): New insn and splitter.
+ (*setmemhi1): New insn.
+
+2021-11-14 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref-tree.c (modref_access_node::update_for_kills): New
+ member function.
+ (modref_access_node::merge_for_kills): Likewise.
+ (modref_access_node::insert_kill): Likewise.
+ * ipa-modref-tree.h (modref_access_node::update_for_kills,
+ modref_access_node::merge_for_kills, modref_access_node::insert_kill):
+ Declare.
+ (modref_access_node::useful_for_kill): New member function.
+ * ipa-modref.c (modref_summary::useful_p): Release useless kills.
+ (lto_modref_summary): Add kills.
+ (modref_summary::dump): Dump kills.
+ (record_access): Add mdoref_access_node parameter.
+ (record_access_lto): Likewise.
+ (merge_call_side_effects): Merge kills.
+ (analyze_call): Add ALWAYS_EXECUTED param and pass it around.
+ (struct summary_ptrs): Add always_executed filed.
+ (analyze_load): Update.
+ (analyze_store): Update; record kills.
+ (analyze_stmt): Add always_executed; record kills in clobbers.
+ (analyze_function): Track always_executed.
+ (modref_summaries::duplicate): Duplicate kills.
+ (update_signature): Release kills.
+ * ipa-modref.h (struct modref_summary): Add kills.
+ * tree-ssa-alias.c (alias_stats): Add kill stats.
+ (dump_alias_stats): Dump kill stats.
+ (store_kills_ref_p): Break out from ...
+ (stmt_kills_ref_p): Use it; handle modref info based kills.
+
+2021-11-14 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/103229
+ * gimple-range-cache.cc (ssa_global_cache::clear): Do not pass
+ null value to memset.
+
+2021-11-14 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref-tree.c (modref_access_node::get_call_arg): New member
+ function.
+ (modref_access_node::get_ao_ref): Likewise.
+ * ipa-modref-tree.h (modref_access_node::get_call_arg): Declare.
+ (modref_access_node::get_ao_ref): Declare.
+ * tree-ssa-alias.c (modref_may_conflict): Use new accessors.
+ * tree-ssa-dse.c (dse_optimize_call): Use new accessors.
+
+2021-11-13 Jan Hubicka <jh@suse.cz>
+
+ PR lto/103211
+ * dbgcnt.def (ipa_attr): New counters.
+ * ipa-pure-const.c: Include dbgcnt.c
+ (ipa_make_function_const): Use debug counter.
+ (ipa_make_function_pure): Likewise.
+ (propagate_pure_const): Fix bug in my previous change.
+
+2021-11-13 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref-tree.c (modref_access_node::range_info_useful_p):
+ Offline from ipa-modref-tree.h.
+ (modref_access_node::dump): Move from ipa-modref.c; make member
+ function.
+ * ipa-modref-tree.h (modref_access_node::range_info_useful_p.
+ modref_access_node::dump): Declare.
+ * ipa-modref.c (dump_access): Remove.
+ (dump_records): Update.
+ (dump_lto_records): Update.
+ (record_access): Update.
+ (record_access_lto): Update.
+
+2021-11-13 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c (modref_summary::modref_summary): Clear new flags.
+ (modref_summary::dump): Dump try_dse.
+ (modref_summary::finalize): Add FUN attribute; compute try-dse.
+ (analyze_function): Update.
+ (read_section): Update.
+ (update_signature): Update.
+ (pass_ipa_modref::execute): Update.
+ * ipa-modref.h (struct modref_summary):
+ * tree-ssa-alias.c (ao_ref_init_from_ptr_and_range): Export.
+ * tree-ssa-alias.h (ao_ref_init_from_ptr_and_range): Declare.
+ * tree-ssa-dse.c (dse_optimize_call): New function.
+ (dse_optimize_stmt): Use it.
+
+2021-11-13 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref-tree.c: Move #if CHECKING_P to proper place.
+
+2021-11-13 Jan Hubicka <jh@suse.cz>
+
+ * ipa-modref-tree.h
+ (struct modref_access_node): Move longer member functions to
+ ipa-modref-tree.c
+ (modref_ref_node::try_merge_with): Turn into modreef_acces_node member
+ function.
+ * ipa-modref-tree.c (modref_access_node::contains): Move here
+ from ipa-modref-tree.h.
+ (modref_access_node::update): Likewise.
+ (modref_access_node::merge): Likewise.
+ (modref_access_node::closer_pair_p): Likewise.
+ (modref_access_node::forced_merge): Likewise.
+ (modref_access_node::update2): Likewise.
+ (modref_access_node::combined_offsets): Likewise.
+ (modref_access_node::try_merge_with): Likewise.
+ (modref_access_node::insert): Likewise.
+
+2021-11-13 Jan Hubicka <jh@suse.cz>
+
+ * ipa-modref.c (modref_summary::global_memory_read_p): Remove.
+ (modref_summary::global_memory_written_p): Remove.
+ (modref_summary::dump): Dump new flags.
+ (modref_summary::finalize): New member function.
+ (analyze_function): Call it.
+ (read_section): Call it.
+ (update_signature): Call it.
+ (pass_ipa_modref::execute): Call it.
+ * ipa-modref.h (struct modref_summary): Remove
+ global_memory_read_p and global_memory_written_p.
+ Add global_memory_read, global_memory_written.
+ * tree-ssa-structalias.c (determine_global_memory_access):
+ Update.
+
+2021-11-13 Jan Hubicka <jh@suse.cz>
+
+ * ipa-fnsummary.c (compute_fn_summary): Use type_attribut_allowed_p
+ * ipa-param-manipulation.c
+ (ipa_param_adjustments::type_attribute_allowed_p):
+ New member function.
+ (drop_type_attribute_if_params_changed_p): New function.
+ (build_adjusted_function_type): Use it.
+ * ipa-param-manipulation.h: Add type_attribute_allowed_p.
+
+2021-11-13 David Malcolm <dmalcolm@redhat.com>
+
+ * doc/invoke.texi (Static Analyzer Options): Add
+ -Wno-analyzer-tainted-allocation-size,
+ -Wno-analyzer-tainted-divisor, -Wno-analyzer-tainted-offset, and
+ -Wno-analyzer-tainted-size to list. Add
+ -Wanalyzer-tainted-allocation-size, -Wanalyzer-tainted-divisor,
+ -Wanalyzer-tainted-offset, and -Wanalyzer-tainted-size to list
+ of options effectively enabled by -fanalyzer.
+ (-Wanalyzer-tainted-allocation-size): New.
+ (-Wanalyzer-tainted-array-index): Tweak wording; add link to CWE.
+ (-Wanalyzer-tainted-divisor): New.
+ (-Wanalyzer-tainted-offset): New.
+ (-Wanalyzer-tainted-size): New.
+
+2021-11-13 Jan Hubicka <jh@suse.cz>
+
+ * attr-fnspec.h (attr_fnspec::arg_eaf_flags): Break out from ...
+ * gimple.c (gimple_call_arg_flags): ... here.
+ * ipa-modref.c (analyze_parms): Record flags known from fnspec.
+ (modref_merge_call_site_flags): Use arg_eaf_flags.
+
+2021-11-13 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/103222
+ * gimple-range-path.cc (path_range_query::compute_ranges_in_phis):
+ New.
+ (path_range_query::compute_ranges_in_block): Call
+ compute_ranges_in_phis.
+ * gimple-range-path.h (path_range_query::compute_ranges_in_phis):
+ New.
+
+2021-11-13 Jan Hubicka <jh@suse.cz>
+
+ * ipa-fnsummary.c (compute_fn_summary): Do not give up on signature
+ changes on "fn spec" attribute; give up on varadic types.
+ * ipa-param-manipulation.c: Include attribs.h.
+ (build_adjusted_function_type): New parameter ARG_MODIFIED; if it is
+ true remove "fn spec" attribute.
+ (ipa_param_adjustments::build_new_function_type): Update.
+ (ipa_param_body_adjustments::modify_formal_parameters): update.
+ * ipa-sra.c: Include attribs.h.
+ (ipa_sra_preliminary_function_checks): Do not check for TYPE_ATTRIBUTES.
+
+2021-11-13 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::path_range_query): Merge
+ ctors.
+ (path_range_query::import_p): Move from header file.
+ (path_range_query::~path_range_query): Adjust for combined ctors.
+ * gimple-range-path.h: Merge ctors.
+ (path_range_query::import_p): Move to .cc file.
+
+2021-11-13 Jan Hubicka <jh@suse.cz>
+
+ PR tree-optimization/103182
+ * ipa-modref.c (callee_to_caller_flags): Fix merging of flags.
+ (modref_eaf_analysis::analyze_ssa_name): Fix merging of flags.
+
+2021-11-12 Stafford Horne <shorne@gmail.com>
+
+ * config/or1k/or1k-protos.h (or1k_profile_hook): New function.
+ * config/or1k/or1k.h (PROFILE_HOOK): Change macro to reference
+ new function or1k_profile_hook.
+ * config/or1k/or1k.c (struct machine_function): Add new field
+ set_mcount_arg_insn.
+ (or1k_profile_hook): New function.
+ (or1k_init_pic_reg): Update to inject pic rtx after _mcount arg
+ when profiling.
+ (or1k_frame_pointer_required): Frame pointer no longer needed
+ when profiling.
+
+2021-11-12 Jan Hubicka <jh@suse.cz>
+
+ PR tree-optimization/103209
+ * tree-ssa-structalias.c (find_func_aliases_for_call): Fix
+ use of handle_rhs_call
+
+2021-11-12 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/103202
+ * gimple-range-path.cc
+ (path_range_query::compute_ranges_in_block): Solve PHI imports first.
+
+2021-11-12 Jan Hubicka <jh@suse.cz>
+
+ * ipa-pure-const.c (propagate_pure_const): Remove redundant check;
+ fix call of ipa_make_function_const and ipa_make_function_pure.
+
+2021-11-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_vector_op::n_advsimd_ops): Delete.
+ (aarch64_vector_op::m_seen_loads): Likewise.
+ (aarch64_vector_costs::aarch64_vector_costs): Don't push to
+ m_advsimd_ops.
+ (aarch64_vector_op::count_ops): Remove vectype and factor parameters.
+ Remove code that tries to predict different vec_flags from the
+ current loop's.
+ (aarch64_vector_costs::add_stmt_cost): Update accordingly.
+ Remove m_advsimd_ops handling.
+
+2021-11-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_vector_costs::m_saw_sve_only_op)
+ (aarch64_sve_only_stmt_p): Delete.
+ (aarch64_vector_costs::prefer_unrolled_loop): New function,
+ extracted from adjust_body_cost.
+ (aarch64_vector_costs::better_main_loop_than_p): New function,
+ using heuristics extracted from adjust_body_cost and
+ adjust_body_cost_sve.
+ (aarch64_vector_costs::adjust_body_cost_sve): Remove
+ advsimd_cycles_per_iter and could_use_advsimd parameters.
+ Update after changes above.
+ (aarch64_vector_costs::adjust_body_cost): Update after changes above.
+
+2021-11-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_vec_op_count::m_vf_factor):
+ New member variable.
+ (aarch64_vec_op_count::aarch64_vec_op_count): Add a parameter for it.
+ (aarch64_vec_op_count::vf_factor): New function.
+ (aarch64_vector_costs::aarch64_vector_costs): When costing for
+ neoverse-512tvb, pass a vf_factor of 2 for the Neoverse V1 version
+ of an SVE loop.
+ (aarch64_vector_costs::adjust_body_cost): Read the vf factor
+ instead of hard-coding 2.
+
+2021-11-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c
+ (aarch64_vec_op_count::rename_cycles_per_iter): New function.
+ (aarch64_vec_op_count::min_nonpred_cycles_per_iter): Likewise.
+ (aarch64_vec_op_count::min_pred_cycles_per_iter): Likewise.
+ (aarch64_vec_op_count::min_cycles_per_iter): Likewise.
+ (aarch64_vec_op_count::dump): Move earlier in file. Dump the
+ above properties too.
+ (aarch64_estimate_min_cycles_per_iter): Delete.
+ (adjust_body_cost): Use aarch64_vec_op_count::min_cycles_per_iter
+ instead of aarch64_estimate_min_cycles_per_iter. Rely on the dump
+ routine to print CPI estimates.
+ (adjust_body_cost_sve): Likewise. Use the other functions above
+ instead of doing the work inline.
+
+2021-11-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_vec_op_count): Allow default
+ initialization.
+ (aarch64_vec_op_count::base_issue_info): Remove handling of null
+ issue_infos.
+ (aarch64_vec_op_count::simd_issue_info): Likewise.
+ (aarch64_vec_op_count::sve_issue_info): Likewise.
+ (aarch64_vector_costs::m_ops): Turn into a vector.
+ (aarch64_vector_costs::m_advsimd_ops): Likewise.
+ (aarch64_vector_costs::aarch64_vector_costs): Add entries to
+ the vectors based on aarch64_tune_params.
+ (aarch64_vector_costs::analyze_loop_vinfo): Update the pred_ops
+ of all entries in m_ops.
+ (aarch64_vector_costs::add_stmt_cost): Call count_ops for all
+ entries in m_ops.
+ (aarch64_estimate_min_cycles_per_iter): Remove issue_info
+ parameter and get the information from the ops instead.
+ (aarch64_vector_costs::adjust_body_cost_sve): Take a
+ aarch64_vec_issue_info instead of a aarch64_vec_op_count.
+ (aarch64_vector_costs::adjust_body_cost): Update call accordingly.
+ Exit earlier if m_ops is empty for either cost structure.
+
+2021-11-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_vector_costs::m_scalar_ops)
+ (aarch64_vector_costs::m_sve_ops): Replace with...
+ (aarch64_vector_costs::m_ops): ...this.
+ (aarch64_vector_costs::analyze_loop_vinfo): Update accordingly.
+ (aarch64_vector_costs::adjust_body_cost_sve): Likewise.
+ (aarch64_vector_costs::aarch64_vector_costs): Likewise.
+ Initialize m_vec_flags here rather than in add_stmt_cost.
+ (aarch64_vector_costs::count_ops): Test for scalar reductions too.
+ Allow vectype to be null.
+ (aarch64_vector_costs::add_stmt_cost): Call count_ops for scalar
+ code too. Don't require vectype to be nonnull.
+ (aarch64_vector_costs::adjust_body_cost): Take the loop_vec_info
+ and scalar costs as parameters. Use the scalar costs to determine
+ the cycles per iteration of the scalar loop, then multiply it
+ by the estimated VF.
+ (aarch64_vector_costs::finish_cost): Update call accordingly.
+
+2021-11-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_dr_type): New function.
+ (aarch64_vector_costs::count_ops): Use it rather than the
+ vectype to determine floatness.
+
+2021-11-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_sve_in_loop_reduction_latency):
+ Remove vectype parameter and get floatness from the type of the
+ stmt lhs instead.
+ (arch64_in_loop_reduction_latency): Likewise.
+ (aarch64_detect_vector_stmt_subtype): Update caller.
+ (aarch64_vector_costs::count_ops): Likewise.
+
+2021-11-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_sve_op_count): Fold into...
+ (aarch64_vec_op_count): ...this. Add a constructor.
+ (aarch64_vec_op_count::vec_flags): New function.
+ (aarch64_vec_op_count::base_issue_info): Likewise.
+ (aarch64_vec_op_count::simd_issue_info): Likewise.
+ (aarch64_vec_op_count::sve_issue_info): Likewise.
+ (aarch64_vec_op_count::m_issue_info): New member variable.
+ (aarch64_vec_op_count::m_vec_flags): Likewise.
+ (aarch64_vector_costs): Add a constructor.
+ (aarch64_vector_costs::m_sve_ops): Change type to aarch64_vec_op_count.
+ (aarch64_vector_costs::aarch64_vector_costs): New function.
+ Initialize m_scalar_ops, m_advsimd_ops and m_sve_ops.
+ (aarch64_vector_costs::count_ops): Remove vec_flags and
+ issue_info parameters, using the new aarch64_vec_op_count
+ functions instead.
+ (aarch64_vector_costs::add_stmt_cost): Update call accordingly.
+ (aarch64_sve_op_count::dump): Fold into...
+ (aarch64_vec_op_count::dump): ..here.
+
+2021-11-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c: Include tree-dfa.h.
+ (aarch64_check_consecutive_mems): New function that takes MEM_EXPR
+ and MEM_OFFSET into account.
+ (aarch64_swap_ldrstr_operands): Use it.
+ (aarch64_operands_ok_for_ldpstp): Likewise. Check that the
+ address of the second memory doesn't depend on the result of
+ the first load.
+
+2021-11-12 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-pure-const.c (ipa_make_function_pure): Fix exit condition.
+
+2021-11-12 Jan Hubicka <jh@suse.cz>
+
+ PR tree-optimization/103175
+ * ipa-modref.c (modref_lattice::merge): Add sanity check.
+ (callee_to_caller_flags): Make flags adjustment sane.
+ (modref_eaf_analysis::analyze_ssa_name): Likewise.
+
+2021-11-12 Jan Hubicka <jh@suse.cz>
+
+ PR ipa/103200
+ * ipa-modref.c (analyze_function, modref_propagate_in_scc): Do
+ not mark pure/const function if there are side-effects.
+
+2021-11-12 Chung-Lin Tang <cltang@codesourcery.com>
+
+ * tree.h (OMP_CLAUSE_MAP_RUNTIME_IMPLICIT_P): New access macro for
+ 'implicit' bit, using 'base.deprecated_flag' field of tree_node.
+ * tree-pretty-print.c (dump_omp_clause): Add support for printing
+ implicit attribute in tree dumping.
+ * gimplify.c (gimplify_adjust_omp_clauses_1):
+ Set OMP_CLAUSE_MAP_RUNTIME_IMPLICIT_P to 1 if map clause is implicitly
+ created.
+ (gimplify_adjust_omp_clauses): Adjust place of adding implicitly created
+ clauses, from simple append, to starting of list, after non-map clauses.
+ * omp-low.c (lower_omp_target): Add GOMP_MAP_IMPLICIT bits into kind
+ values passed to libgomp for implicit maps.
+
+2021-11-12 Jakub Jelinek <jakub@redhat.com>
+
+ * omp-builtins.def (BUILT_IN_GOMP_TEAMS): Remove.
+ (BUILT_IN_GOMP_TEAMS4): New.
+ * builtin-types.def (BT_FN_VOID_UINT_UINT): Remove.
+ (BT_FN_BOOL_UINT_UINT_UINT_BOOL): New.
+ * omp-low.c (lower_omp_teams): Use GOMP_teams4 instead of
+ GOMP_teams, pass to it also num_teams lower-bound expression
+ or a dup of upper-bound if it is missing and a flag whether
+ it is the first call or not.
+
+2021-11-12 Martin Liska <mliska@suse.cz>
+
+ PR tree-optimization/102497
+ * gimple-predicate-analysis.cc (add_pred): Remove unused
+ function:
+
+2021-11-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103204
+ * tree-ssa-sccvn.c (valueize_refs_1): Re-valueize the
+ top operand after folding in an address.
+
+2021-11-11 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::path_range_query): New
+ ctor without a ranger.
+ (path_range_query::~path_range_query): Free ranger if necessary.
+ (path_range_query::range_on_path_entry): Adjust m_ranger for pointer.
+ (path_range_query::ssa_range_in_phi): Same.
+ (path_range_query::compute_ranges_in_block): Same.
+ (path_range_query::compute_imports): Same.
+ (path_range_query::compute_ranges): Same.
+ (path_range_query::range_of_stmt): Same.
+ (path_range_query::compute_outgoing_relations): Same.
+ * gimple-range-path.h (class path_range_query): New ctor.
+ * tree-ssa-loop-ch.c (ch_base::copy_headers): Remove gimple_ranger
+ as path_range_query allocates one.
+ * tree-ssa-threadbackward.c (class back_threader): Remove m_ranger.
+ (back_threader::~back_threader): Same.
+
+2021-11-11 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c
+ (back_threader_profitability::profitable_path_p): Remove loop
+ crossing restriction.
+
+2021-11-11 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c (analyze_function): Do pure/const discovery, return
+ true on success.
+ (pass_modref::execute): If pure/const is discovered fixup cfg.
+ (ignore_edge): Do not ignore pure/const edges.
+ (modref_propagate_in_scc): Do pure/const discovery, return true if
+ cdtor was promoted pure/const.
+ (pass_ipa_modref::execute): If needed remove unreachable functions.
+ * ipa-pure-const.c (warn_function_noreturn): Fix whitespace.
+ (warn_function_cold): Likewise.
+ (skip_function_for_local_pure_const): Move earlier.
+ (ipa_make_function_const): Break out from ...
+ (ipa_make_function_pure): Break out from ...
+ (propagate_pure_const): ... here.
+ (pass_local_pure_const::execute): Use it.
+ * ipa-utils.h (ipa_make_function_const): Declare.
+ (ipa_make_function_pure): Declare.
+ * passes.def: Move early modref after pure-const.
+
+2021-11-11 David Malcolm <dmalcolm@redhat.com>
+
+ PR other/103129
+ * diagnostic-show-locus.c (def_policy): Use def_tabstop.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-builtins.c (TYPES_COMBINE): Delete.
+ (TYPES_COMBINEP): Delete.
+ * config/aarch64/aarch64-simd-builtins.def: Declare type-
+ qualified builtins for vcombine_* intrinsics.
+ * config/aarch64/arm_neon.h (vcombine_s8): Remove unnecessary
+ cast.
+ (vcombine_s16): Likewise.
+ (vcombine_s32): Likewise.
+ (vcombine_f32): Likewise.
+ (vcombine_u8): Use type-qualified builtin and remove casts.
+ (vcombine_u16): Likewise.
+ (vcombine_u32): Likewise.
+ (vcombine_u64): Likewise.
+ (vcombine_p8): Likewise.
+ (vcombine_p16): Likewise.
+ (vcombine_p64): Likewise.
+ (vcombine_bf16): Remove unnecessary cast.
+ * config/aarch64/iterators.md (VD_I): New mode iterator.
+ (VDC_P): New mode iterator.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-builtins.c (TYPES_LOAD1_U): Define.
+ (TYPES_LOAD1_P): Define.
+ (TYPES_STORE1_U): Define.
+ (TYPES_STORE1P): Rename to...
+ (TYPES_STORE1_P): This.
+ (get_mem_type_for_load_store): Add unsigned and poly types.
+ (aarch64_general_gimple_fold_builtin): Add unsigned and poly
+ type-qualified builtin declarations.
+ * config/aarch64/aarch64-simd-builtins.def: Declare type-
+ qualified builtins for LD1/ST1.
+ * config/aarch64/arm_neon.h (vld1_p8): Use type-qualified
+ builtin and remove cast.
+ (vld1_p16): Likewise.
+ (vld1_u8): Likewise.
+ (vld1_u16): Likewise.
+ (vld1_u32): Likewise.
+ (vld1q_p8): Likewise.
+ (vld1q_p16): Likewise.
+ (vld1q_p64): Likewise.
+ (vld1q_u8): Likewise.
+ (vld1q_u16): Likewise.
+ (vld1q_u32): Likewise.
+ (vld1q_u64): Likewise.
+ (vst1_p8): Likewise.
+ (vst1_p16): Likewise.
+ (vst1_u8): Likewise.
+ (vst1_u16): Likewise.
+ (vst1_u32): Likewise.
+ (vst1q_p8): Likewise.
+ (vst1q_p16): Likewise.
+ (vst1q_p64): Likewise.
+ (vst1q_u8): Likewise.
+ (vst1q_u16): Likewise.
+ (vst1q_u32): Likewise.
+ (vst1q_u64): Likewise.
+ * config/aarch64/iterators.md (VALLP_NO_DI): New iterator.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def: Declare unsigned
+ builtins for vector reduction.
+ * config/aarch64/arm_neon.h (vaddv_u8): Use type-qualified
+ builtin and remove casts.
+ (vaddv_u16): Likewise.
+ (vaddv_u32): Likewise.
+ (vaddvq_u8): Likewise.
+ (vaddvq_u16): Likewise.
+ (vaddvq_u32): Likewise.
+ (vaddvq_u64): Likewise.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def:
+ * config/aarch64/arm_neon.h (vpaddq_u8): Use type-qualified
+ builtin and remove casts.
+ (vpaddq_u16): Likewise.
+ (vpaddq_u32): Likewise.
+ (vpaddq_u64): Likewise.
+ (vpadd_u8): Likewise.
+ (vpadd_u16): Likewise.
+ (vpadd_u32): Likewise.
+ (vpaddd_u64): Likewise.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def: Declare unsigned
+ builtins for [r]subhn[2].
+ * config/aarch64/arm_neon.h (vsubhn_s16): Remove unnecessary
+ cast.
+ (vsubhn_s32): Likewise.
+ (vsubhn_s64): Likewise.
+ (vsubhn_u16): Use type-qualified builtin and remove casts.
+ (vsubhn_u32): Likewise.
+ (vsubhn_u64): Likewise.
+ (vrsubhn_s16): Remove unnecessary cast.
+ (vrsubhn_s32): Likewise.
+ (vrsubhn_s64): Likewise.
+ (vrsubhn_u16): Use type-qualified builtin and remove casts.
+ (vrsubhn_u32): Likewise.
+ (vrsubhn_u64): Likewise.
+ (vrsubhn_high_s16): Remove unnecessary cast.
+ (vrsubhn_high_s32): Likewise.
+ (vrsubhn_high_s64): Likewise.
+ (vrsubhn_high_u16): Use type-qualified builtin and remove
+ casts.
+ (vrsubhn_high_u32): Likewise.
+ (vrsubhn_high_u64): Likewise.
+ (vsubhn_high_s16): Remove unnecessary cast.
+ (vsubhn_high_s32): Likewise.
+ (vsubhn_high_s64): Likewise.
+ (vsubhn_high_u16): Use type-qualified builtin and remove
+ casts.
+ (vsubhn_high_u32): Likewise.
+ (vsubhn_high_u64): Likewise.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def: Declare unsigned
+ builtins for [r]addhn[2].
+ * config/aarch64/arm_neon.h (vaddhn_s16): Remove unnecessary
+ cast.
+ (vaddhn_s32): Likewise.
+ (vaddhn_s64): Likewise.
+ (vaddhn_u16): Use type-qualified builtin and remove casts.
+ (vaddhn_u32): Likewise.
+ (vaddhn_u64): Likewise.
+ (vraddhn_s16): Remove unnecessary cast.
+ (vraddhn_s32): Likewise.
+ (vraddhn_s64): Likewise.
+ (vraddhn_u16): Use type-qualified builtin and remove casts.
+ (vraddhn_u32): Likewise.
+ (vraddhn_u64): Likewise.
+ (vaddhn_high_s16): Remove unnecessary cast.
+ (vaddhn_high_s32): Likewise.
+ (vaddhn_high_s64): Likewise.
+ (vaddhn_high_u16): Use type-qualified builtin and remove
+ casts.
+ (vaddhn_high_u32): Likewise.
+ (vaddhn_high_u64): Likewise.
+ (vraddhn_high_s16): Remove unnecessary cast.
+ (vraddhn_high_s32): Likewise.
+ (vraddhn_high_s64): Likewise.
+ (vraddhn_high_u16): Use type-qualified builtin and remove
+ casts.
+ (vraddhn_high_u32): Likewise.
+ (vraddhn_high_u64): Likewise.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def: Use BINOPU type
+ qualifiers in generator macros for uhsub builtins.
+ * config/aarch64/arm_neon.h (vhsub_s8): Remove unnecessary
+ cast.
+ (vhsub_s16): Likewise.
+ (vhsub_s32): Likewise.
+ (vhsub_u8): Use type-qualified builtin and remove casts.
+ (vhsub_u16): Likewise.
+ (vhsub_u32): Likewise.
+ (vhsubq_s8): Remove unnecessary cast.
+ (vhsubq_s16): Likewise.
+ (vhsubq_s32): Likewise.
+ (vhsubq_u8): Use type-qualified builtin and remove casts.
+ (vhsubq_u16): Likewise.
+ (vhsubq_u32): Likewise.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def: Use BINOPU type
+ qualifiers in generator macros for u[r]hadd builtins.
+ * config/aarch64/arm_neon.h (vhadd_s8): Remove unnecessary
+ cast.
+ (vhadd_s16): Likewise.
+ (vhadd_s32): Likewise.
+ (vhadd_u8): Use type-qualified builtin and remove casts.
+ (vhadd_u16): Likewise.
+ (vhadd_u32): Likewise.
+ (vhaddq_s8): Remove unnecessary cast.
+ (vhaddq_s16): Likewise.
+ (vhaddq_s32): Likewise.
+ (vhaddq_u8): Use type-qualified builtin and remove casts.
+ (vhaddq_u16): Likewise.
+ (vhaddq_u32): Likewise.
+ (vrhadd_s8): Remove unnecessary cast.
+ (vrhadd_s16): Likewise.
+ (vrhadd_s32): Likewise.
+ (vrhadd_u8): Use type-qualified builtin and remove casts.
+ (vrhadd_u16): Likewise.
+ (vrhadd_u32): Likewise.
+ (vrhaddq_s8): Remove unnecessary cast.
+ (vrhaddq_s16): Likewise.
+ (vrhaddq_s32): Likewise.
+ (vrhaddq_u8): Use type-wualified builtin and remove casts.
+ (vrhaddq_u16): Likewise.
+ (vrhaddq_u32): Likewise.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def: Use BINOPU type
+ qualifiers in generator macros for usub[lw][2] builtins.
+ * config/aarch64/arm_neon.h (vsubl_s8): Remove unnecessary
+ cast.
+ (vsubl_s16): Likewise.
+ (vsubl_s32): Likewise.
+ (vsubl_u8): Use type-qualified builtin and remove casts.
+ (vsubl_u16): Likewise.
+ (vsubl_u32): Likewise.
+ (vsubl_high_s8): Remove unnecessary cast.
+ (vsubl_high_s16): Likewise.
+ (vsubl_high_s32): Likewise.
+ (vsubl_high_u8): Use type-qualified builtin and remove casts.
+ (vsubl_high_u16): Likewise.
+ (vsubl_high_u32): Likewise.
+ (vsubw_s8): Remove unnecessary casts.
+ (vsubw_s16): Likewise.
+ (vsubw_s32): Likewise.
+ (vsubw_u8): Use type-qualified builtin and remove casts.
+ (vsubw_u16): Likewise.
+ (vsubw_u32): Likewise.
+ (vsubw_high_s8): Remove unnecessary cast.
+ (vsubw_high_s16): Likewise.
+ (vsubw_high_s32): Likewise.
+ (vsubw_high_u8): Use type-qualified builtin and remove casts.
+ (vsubw_high_u16): Likewise.
+ (vsubw_high_u32): Likewise.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def: Use BINOPU type
+ qualifiers in generator macros for uadd[lw][2] builtins.
+ * config/aarch64/arm_neon.h (vaddl_s8): Remove unnecessary
+ cast.
+ (vaddl_s16): Likewise.
+ (vaddl_s32): Likewise.
+ (vaddl_u8): Use type-qualified builtin and remove casts.
+ (vaddl_u16): Likewise.
+ (vaddl_u32): Likewise.
+ (vaddl_high_s8): Remove unnecessary cast.
+ (vaddl_high_s16): Likewise.
+ (vaddl_high_s32): Likewise.
+ (vaddl_high_u8): Use type-qualified builtin and remove casts.
+ (vaddl_high_u16): Likewise.
+ (vaddl_high_u32): Likewise.
+ (vaddw_s8): Remove unnecessary cast.
+ (vaddw_s16): Likewise.
+ (vaddw_s32): Likewise.
+ (vaddw_u8): Use type-qualified builtin and remove casts.
+ (vaddw_u16): Likewise.
+ (vaddw_u32): Likewise.
+ (vaddw_high_s8): Remove unnecessary cast.
+ (vaddw_high_s16): Likewise.
+ (vaddw_high_s32): Likewise.
+ (vaddw_high_u8): Use type-qualified builtin and remove casts.
+ (vaddw_high_u16): Likewise.
+ (vaddw_high_u32): Likewise.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def: Declare type-
+ qualified builtins for [R]SHRN[2].
+ * config/aarch64/arm_neon.h (vshrn_n_u16): Use type-qualified
+ builtin and remove casts.
+ (vshrn_n_u32): Likewise.
+ (vshrn_n_u64): Likewise.
+ (vrshrn_high_n_u16): Likewise.
+ (vrshrn_high_n_u32): Likewise.
+ (vrshrn_high_n_u64): Likewise.
+ (vrshrn_n_u16): Likewise.
+ (vrshrn_n_u32): Likewise.
+ (vrshrn_n_u64): Likewise.
+ (vshrn_high_n_u16): Likewise.
+ (vshrn_high_n_u32): Likewise.
+ (vshrn_high_n_u64): Likewise.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def: Declare unsigned
+ type-qualified builtins for XTN[2].
+ * config/aarch64/arm_neon.h (vmovn_high_u16): Use type-
+ qualified builtin and remove casts.
+ (vmovn_high_u32): Likewise.
+ (vmovn_high_u64): Likewise.
+ (vmovn_u16): Likewise.
+ (vmovn_u32): Likewise.
+ (vmovn_u64): Likewise.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def: Use poly type
+ qualifier in builtin generator macros.
+ * config/aarch64/arm_neon.h (vmul_p8): Use type-qualified
+ builtin and remove casts.
+ (vmulq_p8): Likewise.
+ (vmull_high_p8): Likewise.
+ (vmull_p8): Likewise.
+
+2021-11-11 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-simd-builtins.def: Declare type-
+ qualified builtin generators for unsigned MLA/MLS intrinsics.
+ * config/aarch64/arm_neon.h (vmla_n_u16): Use type-qualified
+ builtin.
+ (vmla_n_u32): Likewise.
+ (vmla_u8): Likewise.
+ (vmla_u16): Likewise.
+ (vmla_u32): Likewise.
+ (vmlaq_n_u16): Likewise.
+ (vmlaq_n_u32): Likewise.
+ (vmlaq_u8): Likewise.
+ (vmlaq_u16): Likewise.
+ (vmlaq_u32): Likewise.
+ (vmls_n_u16): Likewise.
+ (vmls_n_u32): Likewise.
+ (vmls_u8): Likewise.
+ (vmls_u16): Likewise.
+ (vmls_u32): Likewise.
+ (vmlsq_n_u16): Likewise.
+ (vmlsq_n_u32): Likewise.
+ (vmlsq_u8): Likewise.
+ (vmlsq_u16): Likewise.
+ (vmlsq_u32): Likewise.
+
+2021-11-11 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c (modref_summary::useful_p): Check also for side-effects
+ with looping const/pure.
+ (modref_summary_lto::useful_p): Likewise.
+ (merge_call_side_effects): Merge side effects before early exit
+ for pure/const.
+ (process_fnspec): Also handle pure functions.
+ (analyze_call): Do not early exit on looping pure const.
+ (propagate_unknown_call): Also handle nontrivial SCC as side-effect.
+ (modref_propagate_in_scc): Update.
+
+2021-11-11 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103190
+ * tree-ssa-reassoc.c (insert_stmt_after): Only assert on asm goto.
+
+2021-11-11 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::add_copies_to_imports):
+ Rename to...
+ (path_range_query::compute_imports): ...this. Adapt it so it can
+ be passed the imports bitmap instead of working on m_imports.
+ (path_range_query::compute_ranges): Call compute_imports in all
+ cases unless an imports bitmap is passed.
+ * gimple-range-path.h (path_range_query::compute_imports): New.
+ (path_range_query::add_copies_to_imports): Remove.
+ * tree-ssa-threadbackward.c (back_threader::resolve_def): Remove.
+ (back_threader::find_paths_to_names): Inline resolve_def.
+ (back_threader::find_paths): Call compute_imports.
+ (back_threader::resolve_phi): Adjust comment.
+
+2021-11-11 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103188
+ * tree-ssa-loop-ch.c (should_duplicate_loop_header_p):
+ Remove query parameter, split out check for size
+ optimization.
+ (ch_base::m_ranger, cb_base::m_query): Remove.
+ (ch_base::copy_headers): Split processing loop into
+ analysis around which we allocate and use ranger and
+ transform where we do not.
+ (pass_ch::execute): Do not allocate/free ranger here.
+ (pass_ch_vect::execute): Likewise.
+
+2021-11-11 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-pure-const.c (propagate_pure_const): Self recursion is
+ a side effects.
+
+2021-11-11 Jan Hubicka <hubicka@ucw.cz>
+
+ * cgraph.c (set_noreturn_flag_1): New function.
+ (cgraph_node::set_noreturn_flag): New member function
+ * cgraph.h (cgraph_node::set_noreturn_flags): Declare.
+ * ipa-pure-const.c (pass_local_pure_const::execute): Use it.
+
+2021-11-11 Aldy Hernandez <aldyh@redhat.com>
+ Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-loop-ch.c (entry_loop_condition_is_static): Resolve
+ statically to the edge remaining in the loop.
+
+2021-11-11 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/103181
+ * tree-eh.c (operation_could_trap_helper_p): Properly
+ check vector constants for a zero element for integer
+ division. Separate floating point and integer division code.
+
+2021-11-11 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/101378
+ * dwarf2out.c (field_byte_offset): Do the PCC_BITFIELD_TYPE_MATTERS
+ handling only for DECL_BIT_FIELD_TYPE decls.
+
+2021-11-11 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+
+ PR target/102376
+ * config/aarch64/aarch64.c (aarch64_process_target_attr): Check if
+ token is arch extension without leading '+' and emit appropriate
+ diagnostic for the same.
+
+2021-11-11 Jakub Jelinek <jakub@redhat.com>
+
+ * tree.h (OMP_CLAUSE_NUM_TEAMS_EXPR): Rename to ...
+ (OMP_CLAUSE_NUM_TEAMS_UPPER_EXPR): ... this.
+ (OMP_CLAUSE_NUM_TEAMS_LOWER_EXPR): Define.
+ * tree.c (omp_clause_num_ops): Increase num ops for
+ OMP_CLAUSE_NUM_TEAMS to 2.
+ * tree-pretty-print.c (dump_omp_clause): Print optional lower bound
+ for OMP_CLAUSE_NUM_TEAMS.
+ * gimplify.c (gimplify_scan_omp_clauses): Gimplify
+ OMP_CLAUSE_NUM_TEAMS_LOWER_EXPR if non-NULL.
+ (optimize_target_teams): Use OMP_CLAUSE_NUM_TEAMS_UPPER_EXPR instead
+ of OMP_CLAUSE_NUM_TEAMS_EXPR. Handle OMP_CLAUSE_NUM_TEAMS_LOWER_EXPR.
+ * omp-low.c (lower_omp_teams): Use OMP_CLAUSE_NUM_TEAMS_UPPER_EXPR
+ instead of OMP_CLAUSE_NUM_TEAMS_EXPR.
+ * omp-expand.c (expand_teams_call, get_target_arguments): Likewise.
+
+2021-11-11 Richard Biener <rguenther@suse.de>
+
+ * cfganal.c (find_pdom): Remove.
+ (control_dependences::find_control_dependence): Remove
+ special-casing of entry block, call get_immediate_dominator
+ directly.
+ * gimple-predicate-analysis.cc (find_pdom): Remove.
+ (find_dom): Likewise.
+ (find_control_equiv_block): Call get_immediate_dominator
+ directly.
+ (compute_control_dep_chain): Likewise.
+ (predicate::init_from_phi_def): Likewise.
+
+2021-11-11 Richard Biener <rguenther@suse.de>
+
+ * cfganal.h (control_dependences::control_dependence_map):
+ Embed bitmap_head.
+ (control_dependences::m_bitmaps): New.
+ * cfganal.c (control_dependences::set_control_dependence_map_bit):
+ Adjust.
+ (control_dependences::clear_control_dependence_bitmap):
+ Likewise.
+ (control_dependences::find_control_dependence): Do not
+ find_edge for the abnormal edge test.
+ (control_dependences::control_dependences): Instead do not
+ add abnormal edges to the edge list. Adjust.
+ (control_dependences::~control_dependences): Likewise.
+ (control_dependences::get_edges_dependent_on): Likewise.
+ * function-tests.c: Include bitmap.h.
+
+2021-11-11 Kewen Lin <linkw@linux.ibm.com>
+
+ * doc/invoke.texi: Change references to "future cpu" to "power10",
+ "-mcpu=future" to "-mcpu=power10". Adjust words for float128.
+
+2021-11-11 Cui,Lili <lili.cui@intel.com>
+
+ * config/i386/i386-options.c (m_CORE_AVX2): Remove Alderlake
+ from m_CORE_AVX2.
+ (processor_cost_table): Use alderlake_cost for Alderlake.
+ * config/i386/i386.c (ix86_sched_init_global): Handle Alderlake.
+ * config/i386/x86-tune-costs.h (struct processor_costs): Add alderlake
+ cost.
+ * config/i386/x86-tune-sched.c (ix86_issue_rate): Change Alderlake
+ issue rate to 4.
+ (ix86_adjust_cost): Handle Alderlake.
+ * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Enable for Alderlake.
+ (X86_TUNE_PARTIAL_REG_DEPENDENCY): Likewise.
+ (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Likewise.
+ (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Likewise.
+ (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Likewise.
+ (X86_TUNE_MEMORY_MISMATCH_STALL): Likewise.
+ (X86_TUNE_USE_LEAVE): Likewise.
+ (X86_TUNE_PUSH_MEMORY): Likewise.
+ (X86_TUNE_USE_INCDEC): Likewise.
+ (X86_TUNE_INTEGER_DFMODE_MOVES): Likewise.
+ (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Likewise.
+ (X86_TUNE_USE_SAHF): Likewise.
+ (X86_TUNE_USE_BT): Likewise.
+ (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Likewise.
+ (X86_TUNE_ONE_IF_CONV_INSN): Likewise.
+ (X86_TUNE_AVOID_MFENCE): Likewise.
+ (X86_TUNE_USE_SIMODE_FIOP): Likewise.
+ (X86_TUNE_EXT_80387_CONSTANTS): Likewise.
+ (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Likewise.
+ (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Likewise.
+ (X86_TUNE_SSE_TYPELESS_STORES): Likewise.
+ (X86_TUNE_SSE_LOAD0_BY_PXOR): Likewise.
+ (X86_TUNE_AVOID_4BYTE_PREFIXES): Likewise.
+ (X86_TUNE_USE_GATHER): Disable for Alderlake.
+ (X86_TUNE_AVX256_MOVE_BY_PIECES): Likewise.
+ (X86_TUNE_AVX256_STORE_BY_PIECES): Likewise.
+
+2021-11-11 liuhongt <hongtao.liu@intel.com>
+
+ PR target/103151
+ * config/i386/sse.md (V_128_256): Extend to V8HF/V16HF.
+ (avxsizesuffix): Ditto.
+
+2021-11-11 Kito Cheng <kito.cheng@sifive.com>
+
+ * common/config/riscv/riscv-common.c (riscv_subset_list::to_string): Fix
+ wrong marco checking.
+
+2021-11-10 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/102906
+ * tree-ssa-loop-ch.c (entry_loop_condition_is_static): New.
+ (should_duplicate_loop_header_p): Call entry_loop_condition_is_static.
+ (class ch_base): Add m_ranger and m_query.
+ (ch_base::copy_headers): Pass m_query to
+ entry_loop_condition_is_static.
+ (pass_ch::execute): Allocate and deallocate m_ranger and
+ m_query.
+ (pass_ch_vect::execute): Same.
+
+2021-11-10 Andrew Pinski <apinski@marvell.com>
+
+ PR target/103170
+ * config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>):
+ Use vwcore iterator for the r constraint output string.
+
+2021-11-10 qing zhao <qing.zhao@oracle.com>
+
+ * internal-fn.c (expand_DEFERRED_INIT): Apply pattern initialization
+ only when have_insn_for return true for the mode. Fix a memory leak.
+
+2021-11-10 Christophe Lyon <christophe.lyon@foss.st.com>
+
+ * config/arm/arm.c (cortexa9_extra_costs, cortexa8_extra_costs,
+ cortexa5_extra_costs, cortexa7_extra_costs,
+ cortexa12_extra_costs, cortexa15_extra_costs, v7m_extra_costs):
+ Initialize movi, dup and extract costing fields.
+
+2021-11-10 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::path_range_query): Do
+ not init m_path.
+ (path_range_query::dump): Change m_path uses to non-pointer.
+ (path_range_query::defined_outside_path): Same.
+ (path_range_query::set_path): Same.
+ (path_range_query::add_copies_to_imports): Same.
+ (path_range_query::range_of_stmt): Same.
+ (path_range_query::compute_outgoing_relations): Same.
+ (path_range_query::compute_ranges): Imports are now optional.
+ Implement overload that takes an edge.
+ * gimple-range-path.h (class path_range_query): Make imports
+ optional for compute_ranges. Add compute_ranges(edge) overload.
+ Make m_path an auto_vec instead of a pointer and adjust
+ accordingly.
+
+2021-11-10 Tamar Christina <tamar.christina@arm.com>
+
+ * tree-vectorizer.h (struct scalar_cond_masked_key): Add inverted_p.
+ (default_hash_traits<scalar_conf_masked_key>): Likewise.
+ * tree-vect-stmts.c (vectorizable_condition): Check if inverse of mask
+ is live.
+ * tree-vectorizer.c (scalar_cond_masked_key::get_cond_ops_from_tree):
+ Register mask inverses.
+
+2021-11-10 Tamar Christina <tamar.christina@arm.com>
+
+ * tree-vectorizer.c (vectorize_loops): Do local CSE through RPVN upon
+ successful vectorization.
+
+2021-11-10 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-cache.cc (sbr_vector::grow): New.
+ (sbr_vector::set_bb_range): Call grow.
+ (sbr_vector::get_bb_range): Same.
+ (sbr_vector::bb_range_p): Remove assert.
+
+2021-11-10 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-simd.md (*aarch64_topbits_shuffle<mode>_le
+ ,*aarch64_topbits_shuffle<mode>_be): Remove.
+
+2021-11-10 Jan Hubicka <jh@suse.cz>
+
+ * ipa-modref.c: Include tree-eh.h
+ (modref_summary::modref_summary): Initialize side_effects.
+ (struct modref_summary_lto): New bool field side_effects.
+ (modref_summary_lto::modref_summary_lto): Initialize side_effects.
+ (modref_summary::dump): Dump side_effects.
+ (modref_summary_lto::dump): Dump side_effects.
+ (merge_call_side_effects): Merge side effects.
+ (process_fnspec): Calls to non-const/pure or looping
+ function is a side effect.
+ (analyze_call): Self-recursion is a side-effect; handle
+ special builtins.
+ (analyze_load): Watch for volatile and throwing memory.
+ (analyze_store): Likewise.
+ (analyze_stmt): Watch for volatitle asm.
+ (analyze_function): Handle side_effects.
+ (modref_summaries::duplicate): Duplicate side_effects.
+ (modref_summaries_lto::duplicate): Likewise.
+ (modref_write): Stream side_effects.
+ (read_section): Likewise.
+ (update_signature): Update.
+ (propagate_unknown_call): Handle side_effects.
+ (modref_propagate_in_scc): Likewise.
+ * ipa-modref.h (struct modref_summary): Add side_effects.
+ * ipa-pure-const.c (special_builtin_state): Rename to ...
+ (builtin_safe_for_const_function_p): ... this one.
+ (check_call): Update.
+ (finite_function_p): Break out from ...
+ (propagate_pure_const): ... here
+ * ipa-utils.h (finite_function): Declare.
+
+2021-11-10 Lucas A. M. Magalhães <lamm@linux.ibm.com>
+
+ * config.gcc (powerpc*-*-*): Remove -rpath from
+ --with-advance-toolchain.
+
+2021-11-10 Marek Polacek <polacek@redhat.com>
+
+ PR c++/101940
+ * attribs.c (struct scoped_attributes): Add a bool member.
+ (lookup_scoped_attribute_spec): Forward declare.
+ (register_scoped_attributes): New bool parameter, defaulted to
+ false. Use it.
+ (handle_ignored_attributes_option): New function.
+ (free_attr_data): New function.
+ (init_attributes): Call handle_ignored_attributes_option.
+ (attr_namespace_ignored_p): New function.
+ (decl_attributes): Check attr_namespace_ignored_p before
+ warning.
+ * attribs.h (free_attr_data): Declare.
+ (register_scoped_attributes): Adjust declaration.
+ (handle_ignored_attributes_option): Declare.
+ (canonicalize_attr_name): New function template.
+ (canonicalize_attr_name): Use it.
+ * common.opt (Wattributes=): New option with a variable.
+ * doc/extend.texi: Document #pragma GCC diagnostic ignored_attributes.
+ * doc/invoke.texi: Document -Wno-attributes=.
+ * opts.c (common_handle_option) <case OPT_Wattributes_>: Handle.
+ * plugin.h (register_scoped_attributes): Adjust declaration.
+ * toplev.c (compile_file): Call free_attr_data.
+
+2021-11-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/arm/arm-cpus.in (cortex-a710): New CPU.
+ * config/arm/arm-tables.opt: Regenerate.
+ * config/arm/arm-tune.md: Regenerate.
+ * doc/invoke.texi: Update docs.
+
+2021-11-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64-builtins.c
+ (aarch64_general_gimple_fold_builtin): Mark argument as unused.
+
+2021-11-10 Martin Liska <mliska@suse.cz>
+
+ * lto-wrapper.c (merge_and_complain): Make the first argument
+ a reference type.
+
+2021-11-10 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/iterators.md (optab): Use fmax_nan instead of
+ smax_nan and fmin_nan instead of smin_nan.
+ (maxmin_uns): Rename to...
+ (fmaxmin): ...this and make the same changes. Remove entries
+ unrelated to fmax* and fmin*.
+ * config/aarch64/aarch64.md (<maxmin_uns><mode>3): Rename to...
+ (<fmaxmin><mode>3): ...this.
+ * config/aarch64/aarch64-simd.md (aarch64_<maxmin_uns>p<mode>):
+ Rename to...
+ (aarch64_<optab>p<mode>): ...this.
+ (<maxmin_uns><mode>3): Rename to...
+ (<fmaxmin><mode>3): ...this.
+ (reduc_<maxmin_uns>_scal_<mode>): Rename to...
+ (reduc_<optab>_scal_<mode>): ...this and update gen* call.
+ (aarch64_reduc_<maxmin_uns>_internal<mode>): Rename to...
+ (aarch64_reduc_<optab>_internal<mode>): ...this.
+ (aarch64_reduc_<maxmin_uns>_internalv2si): Rename to...
+ (aarch64_reduc_<optab>_internalv2si): ...this.
+ * config/aarch64/aarch64-sve.md (<maxmin_uns><mode>3): Rename to...
+ (<fmaxmin><mode>3): ...this.
+ * config/aarch64/aarch64-simd-builtins.def (smax_nan, smin_nan)
+ Rename to...
+ (fmax_nan, fmin_nan): ...this.
+ * config/aarch64/arm_neon.h (vmax_f32, vmax_f64, vmaxq_f32, vmaxq_f64)
+ (vmin_f32, vmin_f64, vminq_f32, vminq_f64, vmax_f16, vmaxq_f16)
+ (vmin_f16, vminq_f16): Update accordingly.
+
+2021-11-10 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vectorizer.h (vector_costs::finish_cost): Take the
+ corresponding scalar costs as a parameter.
+ (finish_cost): Likewise.
+ * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost)
+ (vect_estimate_min_profitable_iters): Update accordingly.
+ * tree-vect-slp.c (vect_bb_vectorization_profitable_p): Likewise.
+ * tree-vectorizer.c (vector_costs::finish_cost): Likewise.
+ * config/aarch64/aarch64.c (aarch64_vector_costs::finish_cost):
+ Likewise.
+ * config/rs6000/rs6000.c (rs6000_cost_data::finish_cost): Likewise.
+
+2021-11-10 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vectorizer.h (_loop_vec_info::scalar_costs): New member
+ variable.
+ (_loop_vec_info::single_scalar_iteration_cost): Delete.
+ (LOOP_VINFO_SINGLE_SCALAR_ITERATION_COST): Delete.
+ (vector_costs::total_cost): New function.
+ * tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Update
+ after above changes.
+ (_loop_vec_info::~_loop_vec_info): Delete scalar_costs.
+ (vect_compute_single_scalar_iteration_cost): Store the costs
+ in loop_vinfo->scalar_costs.
+ (vect_estimate_min_profitable_iters): Get the scalar cost from
+ loop_vinfo->scalar_costs.
+
+2021-11-10 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vectorizer.h (vector_costs::better_main_loop_than_p)
+ (vector_costs::better_epilogue_loop_than_p)
+ (vector_costs::compare_inside_loop_cost)
+ (vector_costs::compare_outside_loop_cost): Likewise.
+ * tree-vectorizer.c (vector_costs::better_main_loop_than_p)
+ (vector_costs::better_epilogue_loop_than_p)
+ (vector_costs::compare_inside_loop_cost)
+ (vector_costs::compare_outside_loop_cost): New functions,
+ containing code moved from...
+ * tree-vect-loop.c (vect_better_loop_vinfo_p): ...here.
+
+2021-11-10 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vectorizer.h (_loop_vec_info): Remove vec_outside_cost
+ and vec_inside_cost.
+ (vector_costs::outside_cost): New function.
+ * tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Update
+ after above.
+ (vect_estimate_min_profitable_iters): Likewise.
+ (vect_better_loop_vinfo_p): Get the inside and outside costs
+ from the loop_vec_infos' vector_costs.
+
+2021-11-10 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vectorizer.h (vec_info::target_cost_data): Replace with...
+ (_loop_vec_info::vector_costs): ...this.
+ (LOOP_VINFO_TARGET_COST_DATA): Delete.
+ * tree-vectorizer.c (vec_info::vec_info): Remove target_cost_data
+ initialization.
+ (vec_info::~vec_info): Remove corresponding delete.
+ * tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Initialize
+ vector_costs to null.
+ (_loop_vec_info::~_loop_vec_info): Delete vector_costs.
+ (vect_analyze_loop_operations): Update after above changes.
+ (vect_analyze_loop_2): Likewise.
+ (vect_estimate_min_profitable_iters): Likewise.
+ * tree-vect-slp.c (vect_slp_analyze_operations): Likewise.
+
+2021-11-10 Jan Hubicka <hubicka@ucw.cz>
+
+ * tree-core.h (EAF_DIRECT): Remove.
+ (EAF_NOCLOBBER): Remove.
+ (EAF_UNUSED): Remove.
+ (EAF_NOESCAPE): Remove.
+ (EAF_NO_DIRECT_CLOBBER): New.
+ (EAF_NO_INDIRECT_CLOBBER): New.
+ (EAF_NODIRECTESCAPE): Remove.
+ (EAF_NO_DIRECT_ESCAPE): New.
+ (EAF_NO_INDIRECT_ESCAPE): New.
+ (EAF_NOT_RETURNED): Remove.
+ (EAF_NOT_RETURNED_INDIRECTLY): New.
+ (EAF_NOREAD): Remove.
+ (EAF_NO_DIRECT_READ): New.
+ (EAF_NO_INDIRECT_READ): New.
+ * gimple.c (gimple_call_arg_flags): Update for new flags.
+ (gimple_call_retslot_flags): Update for new flags.
+ * ipa-modref.c (dump_eaf_flags): Likewise.
+ (remove_useless_eaf_flags): Likewise.
+ (deref_flags): Likewise.
+ (modref_lattice::init): Likewise.
+ (modref_lattice::merge): Likewise.
+ (modref_lattice::merge_direct_load): Likewise.
+ (modref_lattice::merge_direct_store): Likewise.
+ (modref_eaf_analysis::merge_call_lhs_flags): Likewise.
+ (callee_to_caller_flags): Likewise.
+ (modref_eaf_analysis::analyze_ssa_name): Likewise.
+ (modref_eaf_analysis::propagate): Likewise.
+ (modref_merge_call_site_flags): Likewise.
+ * ipa-modref.h (interposable_eaf_flags): Likewise.
+ * tree-ssa-alias.c: (ref_maybe_used_by_call_p_1) Likewise.
+ * tree-ssa-structalias.c (handle_call_arg): Likewise.
+ (handle_rhs_call): Likewise.
+ * tree-ssa-uninit.c (maybe_warn_pass_by_reference): Likewise.
+
+2021-11-10 Tamar Christina <tamar.christina@arm.com>
+
+ * tree-vect-slp-patterns.c (complex_mul_pattern::matches): Remove l1node.
+
+2021-11-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64-builtins.c
+ (aarch64_general_gimple_fold_builtin): Change pointer alignment and
+ alias.
+
+2021-11-10 Jan Hubicka <jh@suse.cz>
+
+ * ipa-modref-tree.h (modref_tree::remap_params): Fix off-by-one error.
+
+2021-11-10 H.J. Lu <hongjiu.lu@intel.com>
+ Hongtao Liu <hongtao.liu@intel.com>
+
+ PR middle-end/102566
+ * match.pd (nop_atomic_bit_test_and_p): New match.
+ * tree-ssa-ccp.c (convert_atomic_bit_not): New function.
+ (gimple_nop_atomic_bit_test_and_p): New prototype.
+ (optimize_atomic_bit_test_and): Transform equivalent, but slighly
+ different cases to their canonical forms.
+
+2021-11-10 liuhongt <hongtao.liu@intel.com>
+
+ PR tree-optimization/103126
+ * tree-vect-loop.c (neutral_op_for_reduction): Remove static.
+ * tree-vectorizer.h (neutral_op_for_reduction): Declare.
+ * tree-if-conv.c : Include tree-vectorizer.h.
+ (is_cond_scalar_reduction): Handle
+ BIT_XOR_EXPR/BIT_IOR_EXPR/BIT_AND_EXPR.
+ (convert_scalar_cond_reduction): Ditto.
+
+2021-11-10 konglin1 <lingling.kong@intel.com>
+
+ * config/i386/sse.md (cmul<conj_op><mode>3): add new define_expand.
+ (cmla<conj_op><mode>4): Likewise
+
+2021-11-10 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadedge.c: Do not include
+ gimple-ssa-evrp-analyze.h.
+ * value-pointer-equiv.cc: Same.
+
+2021-11-10 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c
+ (back_threader::maybe_register_path_dump): Abstract path dumping...
+ (dump_path): ...here.
+ (back_threader::resolve_phi): Call dump_path.
+ (debug): Same.
+
+2021-11-10 konglin1 <lingling.kong@intel.com>
+
+ * config/i386/sse.md (fma_<complexpairopname>_<mode>_pair):
+ Add new define_insn.
+ (fma_<mode>_fmaddc_bcst): Add new define_insn_and_split.
+ (fma_<mode>_fcmaddc_bcst): Likewise
+
+2021-11-10 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102464
+ * match.pd: Simplify (trunc)fmax/fmin((extend)a, (extend)b) to
+ MAX/MIN(a,b)
+
+2021-11-10 Andrew Pinski <apinski@marvell.com>
+
+ PR target/101529
+ * config/aarch64/aarch64.c (aarch64_evpc_ins): Don't use target
+ as an input, use original one.
+
+2021-11-10 Sandra Loosemore <sandra@codesourcery.com>
+
+ * config/nios2/nios2.c (nios2_can_inline_p): New.
+ (TARGET_CAN_INLINE_P): Define.
+
+2021-11-09 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-call.c (rs6000_gimple_fold_new_builtin):
+ Disable gimple fold for RS6000_BIF_{XVMINDP,XVMINSP,VMINFP} and
+ RS6000_BIF_{XVMAXDP,XVMAXSP,VMAXFP} when fast-math is not set.
+ (lxvrse_expand_builtin): Modify the expansion for sign extension.
+ All extensions are done within VSX registers.
+
+2021-11-09 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/10352
+ * match.pd: Remove check of TYPE_PRECISION for
+ the a?0:pow2 case.
+
+2021-11-09 Andrew MacLeod <amacleod@redhat.com>
+
+ * function.c (allocate_struct_function): Don't set x_range_query.
+ * function.h (get_range_query): Move to value-query.h.
+ * gimple-range.cc (enable_ranger): Check that query is currently NULL.
+ (disable_ranger): Clear function current query field.
+ * value-query.cc (get_global_range_query): Relocate to:
+ * value-query.h (get_global_range_query): Here and inline.
+ (get_range_query): Relocate here from function.h.
+
+2021-11-09 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c
+ (back_threader::maybe_register_path_dump): New.
+ (back_threader::maybe_register_path): Call maybe_register_path_dump.
+
+2021-11-09 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (back_threader::maybe_register_path):
+ Return NULL when unprofitable.
+
+2021-11-09 Martin Jambor <mjambor@suse.cz>
+
+ * tree.h (build_debug_expr_decl): Declare.
+ * tree.c (build_debug_expr_decl): New function.
+ * cfgexpand.c (avoid_deep_ter_for_debug): Use build_debug_expr_decl
+ instead of building a DEBUG_EXPR_DECL.
+ * ipa-param-manipulation.c
+ (ipa_param_body_adjustments::prepare_debug_expressions): Likewise.
+ * omp-simd-clone.c (ipa_simd_modify_stmt_ops): Likewise.
+ * tree-ssa-ccp.c (optimize_atomic_bit_test_and): Likewise.
+ * tree-ssa-phiopt.c (spaceship_replacement): Likewise.
+ * tree-ssa-reassoc.c (make_new_ssa_for_def): Likewise.
+
+2021-11-09 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-call.c (rs6000_type_string): New function.
+ (def_builtin): Change debug formatting for easier parsing and
+ include more information.
+ (rs6000_init_builtins): Add dump of autogenerated builtins.
+ (altivec_init_builtins): Dump __builtin_altivec_mask_for_load for
+ completeness.
+
+2021-11-09 Marek Polacek <polacek@redhat.com>
+
+ * ipa-modref.c (analyze_parms): Fix a typo.
+
+2021-11-09 Kito Cheng <kito.cheng@sifive.com>
+
+ PR target/102957
+ * common/config/riscv/riscv-common.c (multi_letter_subset_rank): Remove
+ assertion for Z*-ext.
+
+2021-11-09 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c (analyze_parms): Add past_flags, past_retslot_flags
+ and past_static_chain; merge past summary with current one.
+ (analyze_function): Update.
+
+2021-11-09 Aldy Hernandez <aldyh@redhat.com>
+
+ * doc/invoke.texi (Invoking GCC): Document --param=threader-debug.
+
+2021-11-09 Martin Liska <mliska@suse.cz>
+
+ * print-rtl.c (rtx_writer::rtx_writer): Make the compilation
+ conditional based on
+ * print-rtl.h (class rtx_writer): Likewise.
+
+2021-11-09 Thomas Schwinge <thomas@codesourcery.com>
+
+ * input.h (location_hash): Use 'BUILTINS_LOCATION' as spare value
+ for 'Deleted'. Turn into a '#define'.
+
+2021-11-09 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::dump): Clean up.
+ (path_range_query::compute_ranges): Same.
+ * value-relation.cc (path_oracle::dump): Same.
+
+2021-11-09 Aldy Hernandez <aldyh@redhat.com>
+
+ * dumpfile.c (dump_options): Remove TDF_THREADING entry.
+ * dumpfile.h (enum dump_flag): Remove TDF_THREADING and adjust
+ remaining entries.
+ * flag-types.h (enum threader_debug): New.
+ * gimple-range-path.cc (DEBUG_SOLVER): Use param_threader_debug.
+ * params.opt: Add entry for --param=threader-debug=.
+
+2021-11-09 Thomas Schwinge <thomas@codesourcery.com>
+
+ PR middle-end/101204
+ PR other/103157
+ * diagnostic-spec.h (typedef xint_hash_t): Turn into...
+ (struct xint_hash_t): ... this.
+ * doc/gty.texi: Update.
+
+2021-11-09 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/arm/arm-cpus.in (armv9): New define.
+ (ARMv9a): New group.
+ (armv9-a): New arch definition.
+ * config/arm/arm-tables.opt: Regenerate.
+ * config/arm/arm.h (BASE_ARCH_9A): New arch enum value.
+ * config/arm/t-aprofile: Added armv9-a and armv9+simd.
+ * config/arm/t-arm-elf: Added arm9-a, v9_fps and all_v9_archs
+ to MULTILIB_MATCHES.
+ * config/arm/t-multilib: Added v9_a_nosimd_variants and
+ v9_a_simd_variants to MULTILIB_MATCHES.
+ * doc/invoke.texi: Update docs.
+
+2021-11-09 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/103132
+ * ipa-param-manipulation.c (replace_with_mapped_expr): Early
+ return with error_mark_mode when part of expression is mapped to
+ NULL.
+ (ipa_param_body_adjustments::remap_with_debug_expressions): Set
+ mapped value to NULL if walk_tree returns error_mark_mode.
+
+2021-11-09 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-strlen.c (compare_nonzero_chars): Pass statement
+ context to ranger.
+ (get_addr_stridx): Same.
+ (get_stridx): Same.
+ (get_range_strlen_dynamic): Same.
+ (handle_builtin_strlen): Same.
+ (handle_builtin_strchr): Same.
+ (handle_builtin_strcpy): Same.
+ (maybe_diag_stxncpy_trunc): Same.
+ (handle_builtin_stxncpy_strncat): Same.
+ (handle_builtin_memcpy): Same.
+ (handle_builtin_strcat): Same.
+ (handle_alloc_call): Same.
+ (handle_builtin_memset): Same.
+ (handle_builtin_string_cmp): Same.
+ (handle_pointer_plus): Same.
+ (count_nonzero_bytes_addr): Same.
+ (count_nonzero_bytes): Same.
+ (handle_store): Same.
+ (fold_strstr_to_strncmp): Same.
+ (handle_integral_assign): Same.
+ (check_and_optimize_stmt): Same.
+ (class strlen_dom_walker): Replace evrp with ranger.
+ (strlen_dom_walker::before_dom_children): Remove evrp.
+ (strlen_dom_walker::after_dom_children): Remove evrp.
+ * gimple-ssa-warn-access.cc (maybe_check_access_sizes):
+ Restrict sprintf output.
+
+2021-11-09 Martin Liska <mliska@suse.cz>
+
+ * genconditions.c (write_one_condition): Add const qualifier
+ to pointer casting.
+
+2021-11-09 Jeff Law <jeffreyalaw@gmail.com>
+
+ * match.pd: New pattern to simplify (1 << n) & M ==/!= 0 for M
+ being a power of 2.
+
+2021-11-08 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-builtin-new.def (VEC_INIT_V16QI): Use
+ escape-newline support.
+ (VEC_INIT_V4SI): Likewise.
+ (VEC_INIT_V8HI): Likewise.
+ (PACK_V1TI): Likewise.
+ (DIVDEU): Likewise.
+ (VFIRSTMISMATCHOREOSINDEX_V16QI): Likewise.
+ (VFIRSTMISMATCHOREOSINDEX_V8HI): Likewise.
+ (VFIRSTMISMATCHOREOSINDEX_V4SI): Likewise.
+ (CMPRB2): Likewise.
+ (VSTDCP): Likewise.
+ (VSIEDP): Likewise.
+ (FMAF128_ODD): Likewise.
+ (VSCEQPUO): Likewise.
+ (VSIEQP): Likewise.
+ (VSIEQPF): Likewise.
+ (VSTDCQP): Likewise.
+ (PACK_TD): Likewise.
+ (TABORTDC): Likewise.
+ (TABORTDCI): Likewise.
+ (SE_LXVRBX): Likewise.
+ (SE_LXVRHX): Likewise.
+ (SE_LXVRWX): Likewise.
+ (SE_LXVRDX): Likewise.
+ (VREPLACE_UN_UV2DI): Likewise.
+ (VREPLACE_UN_UV4SI): Likewise.
+ (VREPLACE_UN_V2DI): Likewise.
+ (VREPLACE_ELT_UV2DI): Likewise.
+ (VREPLACE_ELT_V2DI): Likewise.
+ (ZE_LXVRBX): Likewise.
+ (ZE_LXVRHX): Likewise.
+ (ZE_LXVRWX): Likewise.
+ (ZE_LXVRDX): Likewise.
+ (CFUGED): Likewise.
+ (CNTLZDM): Likewise.
+ (CNTTZDM): Likewise.
+ (PDEPD): Likewise.
+ (PEXTD): Likewise.
+ (PMXVBF16GER2): Likewise.
+ (PMXVBF16GER2_INTERNAL): Likewise.
+ (PMXVBF16GER2NN): Likewise.
+ (PMXVBF16GER2NN_INTERNAL): Likewise.
+ (PMXVBF16GER2NP): Likewise.
+ (PMXVBF16GER2NP_INTERNAL): Likewise.
+ (PMXVBF16GER2PN): Likewise.
+ (PMXVBF16GER2PN_INTERNAL): Likewise.
+ (PMXVBF16GER2PP): Likewise.
+ (PMXVBF16GER2PP_INTERNAL): Likewise.
+ (PMXVF16GER2): Likewise.
+ (PMXVF16GER2_INTERNAL): Likewise.
+ (PMXVF16GER2NN): Likewise.
+ (PMXVF16GER2NN_INTERNAL): Likewise.
+ (PMXVF16GER2NP): Likewise.
+ (PMXVF16GER2NP_INTERNAL): Likewise.
+ (PMXVF16GER2PN): Likewise.
+ (PMXVF16GER2PN_INTERNAL): Likewise.
+ (PMXVF16GER2PP): Likewise.
+ (PMXVF16GER2PP_INTERNAL): Likewise.
+ (PMXVF32GER_INTERNAL): Likewise.
+ (PMXVF32GERNN): Likewise.
+ (PMXVF32GERNN_INTERNAL): Likewise.
+ (PMXVF32GERNP): Likewise.
+ (PMXVF32GERNP_INTERNAL): Likewise.
+ (PMXVF32GERPN): Likewise.
+ (PMXVF32GERPN_INTERNAL): Likewise.
+ (PMXVF32GERPP): Likewise.
+ (PMXVF32GERPP_INTERNAL): Likewise.
+ (PMXVF64GER): Likewise.
+ (PMXVF64GER_INTERNAL): Likewise.
+ (PMXVF64GERNN): Likewise.
+ (PMXVF64GERNN_INTERNAL): Likewise.
+ (PMXVF64GERNP): Likewise.
+ (PMXVF64GERNP_INTERNAL): Likewise.
+ (PMXVF64GERPN): Likewise.
+ (PMXVF64GERPN_INTERNAL): Likewise.
+ (PMXVF64GERPP): Likewise.
+ (PMXVF64GERPP_INTERNAL): Likewise.
+ (PMXVI16GER2): Likewise.
+ (PMXVI16GER2_INTERNAL): Likewise.
+ (PMXVI16GER2PP): Likewise.
+ (PMXVI16GER2PP_INTERNAL): Likewise.
+ (PMXVI16GER2S): Likewise.
+ (PMXVI16GER2S_INTERNAL): Likewise.
+ (PMXVI16GER2SPP): Likewise.
+ (PMXVI16GER2SPP_INTERNAL): Likewise.
+ (PMXVI4GER8): Likewise.
+ (PMXVI4GER8_INTERNAL): Likewise.
+ (PMXVI4GER8PP): Likewise.
+ (PMXVI4GER8PP_INTERNAL): Likewise.
+ (PMXVI8GER4): Likewise.
+ (PMXVI8GER4_INTERNAL): Likewise.
+ (PMXVI8GER4PP): Likewise.
+ (PMXVI8GER4PP_INTERNAL): Likewise.
+ (PMXVI8GER4SPP): Likewise.
+ (PMXVI8GER4SPP_INTERNAL): Likewise.
+ * config/rs6000/rs6000-gen-builtins.c (MAXLINES): New macro.
+ (linebuf): Increase size.
+ (lines): New variable.
+ (lastline): Likewise.
+ (real_line_pos): New function.
+ (diag): Change signature.
+ (bif_diag): Change signature; support escape-newline handling.
+ (ovld_diag): Likewise.
+ (fatal): Move earlier.
+ (consume_whitespace): Adjust diag call.
+ (advance_line): Add escape-newline handling; call fatal.
+ (safe_inc_pos): Adjust diag call.
+ (match_identifier): Likewise.
+ (match_integer): Likewise.
+ (match_to_right_bracket): Call fatal instead of diag; adjust diag
+ call.
+ (match_basetype): Adjust diag calls.
+ (match_bracketed_pair): Likewise.
+ (match_const_restriction): Likewise.
+ (match_type): Likewise.
+ (parse_args): Likewise.
+ (parse_bif_attrs): Likewise.
+ (complete_vector_type): Likewise.
+ (complete_base_type): Likewise.
+ (parse_prototype): Likewise.
+ (parse_bif_entry): Likewise.
+ (parse_bif_stanza): Likewise.
+ (parse_ovld_entry): Likewise.
+ (parse_ovld_stanza): Likewise.
+ (main): Allocate buffers for lines[].
+
+2021-11-08 Eric Botcazou <ebotcazou@adacore.com>
+
+ * config/i386/i386.c (legitimize_pic_address): Adjust comment and
+ use the REG argument on the CM_LARGE_PIC code path as well.
+ * config/i386/predicates.md (gotoff_operand): Do not treat VxWorks
+ specially with the large code models.
+
+2021-11-08 Jan Hubicka <hubicka@ucw.cz>
+
+ * gimple.c (gimple_call_static_chain_flags): Revert the workaround
+ allowing interposition since issues with binds_to_local_def were
+ hopefully solved.
+
+2021-11-08 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/103122
+ * gimple-range.cc (gimple_ranger::range_of_expr): Request the cache
+ entry with "calulate new values" set to false.
+
+2021-11-08 Jan Hubicka <hubicka@ucw.cz>
+
+ * builtins.c (is_simple_builtin): Add builitin_dwarf_cfa
+ and builtin_return_address.
+ (builtin_fnspec): Annotate builtin_return,
+ bulitin_eh_pointer, builtin_eh_filter, builtin_unwind_resume,
+ builtin_cxa_end_cleanup, builtin_eh_copy_values,
+ builtin_frame_address, builtin_apply_args,
+ builtin_asan_before_dynamic_init, builtin_asan_after_dynamic_init,
+ builtin_prefetch, builtin_dwarf_cfa, builtin_return_addrss
+ as ".c"
+ * ipa-pure-const.c (special_builtin_state): Add builtin_dwarf_cfa
+ and builtin_return_address.
+
+2021-11-08 Jan Hubicka <hubicka@ucw.cz>
+
+ PR tree-optimization/103177
+ * passes.def: Move uncprop after pure/const and modref.
+
+2021-11-08 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/103099
+ PR ipa/103107
+ * tree-inline.c (remap_gimple_stmt): Unshare the expression without
+ location before invoking remap_with_debug_expressions on it.
+ * ipa-param-manipulation.c
+ (ipa_param_body_adjustments::prepare_debug_expressions): Likewise.
+
+2021-11-08 David Edelsohn <dje.gcc@gmail.com>
+
+ * config/rs6000/vsx.md (vsx_splat_v4si_di): Revert "wa"
+ constraint to "we".
+
+2021-11-08 Richard Biener <rguenther@suse.de>
+
+ * cfgloop.c (verify_loop_structure): Use a temporary BB flag
+ instead of an sbitmap to cache irreducible state.
+
+2021-11-08 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/103120
+ * gimple-range-path.cc (path_range_query::range_defined_in_block):
+ Bail if there's a cache entry.
+
+2021-11-08 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000.c (rs6000_builtin_reciprocal): Use
+ rs6000_builtin_decls_x when appropriate.
+ (add_condition_to_bb): Likewise.
+ (rs6000_atomic_assign_expand_fenv): Likewise.
+
+2021-11-08 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-call.c (rs6000_new_builtin_decl): New function.
+ (rs6000_builtin_decl): Call it.
+
+2021-11-08 Martin Liska <mliska@suse.cz>
+
+ * cgraph.c (cgraph_node::dump): Dump it from decl.
+
+2021-11-08 Martin Liska <mliska@suse.cz>
+
+ PR gcov-profile/100520
+ * coverage.c (coverage_compute_profile_id): Strip .gk when
+ compare debug is used.
+ * system.h (endswith): New function.
+
+2021-11-08 Martin Liska <mliska@suse.cz>
+
+ * cgraph.c (cgraph_node::dump): Dump static_chain_decl.
+
+2021-11-08 Thomas Schwinge <thomas@codesourcery.com>
+
+ * config/rs6000/rbtree.c: Fix 'Copyright (C) 2020-21' into '2020-2021'
+ * config/rs6000/rbtree.h: Likewise.
+ * config/rs6000/rs6000-builtin-new.def: Likewise.
+ * config/rs6000/rs6000-gen-builtins.c: Likewise.
+ * config/rs6000/rs6000-overload.def: Likewise.
+
+2021-11-08 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_ldn_stn_vectors): New function.
+ (aarch64_address_cost): Use it instead of testing for CImode and
+ XImode directly.
+
+2021-11-08 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genmodes.c (emit_insn_modes_h): Define NUM_MODE_* macros.
+ * expmed.h (NUM_MODE_INT): Delete in favor of genmodes definitions.
+ (NUM_MODE_PARTIAL_INT, NUM_MODE_VECTOR_INT): Likewise.
+ * real.h (real_format_for_mode): Use NUM_MODE_FLOAT and
+ NUM_MODE_DECIMAL_FLOAT.
+ (REAL_MODE_FORMAT): Likewise.
+
+2021-11-08 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * tree-vect-loop.c (vect_better_loop_vinfo_p): Change how epilogue loop
+ costs are compared.
+
+2021-11-08 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (vect_create_loop_vinfo): Add main_loop_info
+ parameter.
+ * tree-vect-loop.c (vect_create_loop_vinfo): Likewise. Set
+ LOOP_VINFO_ORIG_LOOP_INFO and conditionalize set of
+ LOOP_VINFO_NITERS_ASSUMPTIONS.
+ (vect_analyze_loop_1): Adjust.
+ (vect_analyze_loop): Move loop constraint setting and
+ SCEV/niter reset here from vect_create_loop_vinfo to perform
+ it only once.
+ (vect_analyze_loop_form): Move dumping of symbolic niters
+ here from vect_create_loop_vinfo.
+
+2021-11-08 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref-tree.h (enum modref_special_parms): New enum.
+ (struct modref_access_node): update for special parms.
+ (struct modref_ref_node): Likewise.
+ (struct modref_parm_map): Likewise.
+ (struct modref_tree): Likewise.
+ * ipa-modref.c (dump_access): Likewise.
+ (get_access): Detect static chain.
+ (parm_map_for_arg): Take tree as arg instead of
+ stmt and index.
+ (merge_call_side_effects): Compute map for static chain.
+ (process_fnspec): Update.
+ (struct escape_point): Remove retslot_arg and static_chain_arg.
+ (analyze_parms): Update.
+ (compute_parm_map): Update.
+ (propagate_unknown_call): Update.
+ (modref_propagate_in_scc): Update.
+ (modref_merge_call_site_flags): Update.
+ (ipa_merge_modref_summary_after_inlining): Update.
+ * tree-ssa-alias.c (modref_may_conflict): Handle static chain.
+ * ipa-modref-tree.c (test_merge): Update.
+
+2021-11-08 Haochen Gui <guihaoc@gcc.gnu.org>
+
+ * config/rs6000/rs6000-call.c (rs6000_gimple_fold_builtin): Disable
+ gimple fold for VSX_BUILTIN_XVMINDP, ALTIVEC_BUILTIN_VMINFP,
+ VSX_BUILTIN_XVMAXDP, ALTIVEC_BUILTIN_VMAXFP when fast-math is not
+ set.
+
+2021-11-08 liuhongt <hongtao.liu@intel.com>
+
+ PR tree-optimization/103077
+ * doc/invoke.texi (Options That Control Optimization):
+ Update documentation for -ftree-loop-vectorize and
+ -ftree-slp-vectorize which are enabled by default at -02.
+
+2021-11-08 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102464
+ * match.pd (Simplifcation (trunc)copysign((extend)a, (extend)b)
+ to .COPYSIGN (a, b)): Add !HONOR_SNANS.
+
+2021-11-08 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102464
+ * match.pd: Simplify
+ (trunc)fma ((extend)a, (extend)b, (extend)c) to IFN_FMA (a, b,
+ c) under flag_unsafe_math_optimizations.
+
+2021-11-07 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103055
+ * params.opt (modref-max-depth): Add range.
+ (modref-max-adjustments): Fix range.
+
+2021-11-07 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-pass.h (make_pass_vrp_threader): Remove.
+ * tree-ssa-threadbackward.c
+ (back_threader_profitability::profitable_path_p): Remove
+ ASSERT_EXPR references.
+ * tree-ssa-threadedge.c (jt_state::register_equivs_stmt): Same.
+ * tree-vrp.c (vrp_folder::simplify_casted_conds): Same.
+ (execute_vrp): Same.
+ (class hybrid_threader): Remove.
+ (hybrid_threader::hybrid_threader): Remove.
+ (hybrid_threader::~hybrid_threader): Remove.
+ (hybrid_threader::before_dom_children): Remove.
+ (hybrid_threader::after_dom_children): Remove.
+ (execute_vrp_threader): Remove.
+ (class pass_vrp_threader): Remove.
+ (make_pass_vrp_threader): Remove.
+
+2021-11-07 Jan Hubicka <hubicka@ucw.cz>
+
+ * gimple.c (gimple_call_arg_flags): Use interposable_eaf_flags.
+ (gimple_call_retslot_flags): Likewise.
+ (gimple_call_static_chain_flags): Likewise.
+ * ipa-modref.c (remove_useless_eaf_flags): Do not remove everything for
+ NOVOPS.
+ (modref_summary::useful_p): Likewise.
+ (modref_summary_lto::useful_p): Likewise.
+ (analyze_parms): Do not give up on NOVOPS.
+ (analyze_function): When dumping report chnages in EAF flags
+ between IPA and local pass.
+ (modref_merge_call_site_flags): Compute implicit eaf flags
+ based on callee ecf_flags and fnspec; if the function does not
+ bind to current defs use interposable_eaf_flags.
+ (modref_propagate_flags_in_scc): Update.
+ * ipa-modref.h (interposable_eaf_flags): New function.
+
+2021-11-07 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): New
+ forward decl.
+ (rs6000_invalid_new_builtin): New function.
+ (rs6000_expand_builtin): Call rs6000_expand_new_builtin.
+ (rs6000_expand_ldst_mask): New function.
+ (new_cpu_expand_builtin): Likewise.
+ (elemrev_icode): Likewise.
+ (ldv_expand_builtin): Likewise.
+ (lxvrse_expand_builtin): Likewise.
+ (lxvrze_expand_builtin): Likewise.
+ (stv_expand_builtin): Likewise.
+ (new_mma_expand_builtin): Likewise.
+ (new_htm_spr_num): Likewise.
+ (new_htm_expand_builtin): Likewise.
+ (rs6000_expand_new_builtin): Likewise.
+ (rs6000_init_builtins): Initialize altivec_builtin_mask_for_load.
+
+2021-11-07 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c (modref_lattice): Add do_dataflow,
+ changed and propagate_to fields.
+ (modref_lattice::release): Free propagate_to
+ (modref_lattice::merge): Do not give up early on unknown
+ lattice values.
+ (modref_lattice::merge_deref): Likewise.
+ (modref_eaf_analysis): Update toplevel comment.
+ (modref_eaf_analysis::analyze_ssa_name): Record postponned ssa names;
+ do optimistic dataflow initialization.
+ (modref_eaf_analysis::merge_with_ssa_name): Build dataflow graph.
+ (modref_eaf_analysis::propagate): New member function.
+ (analyze_parms): Update to new API of modref_eaf_analysis.
+
+2021-11-06 Jan Hubicka <hubicka@ucw.cz>
+
+ * cgraph.h (cgraph_node::can_be_discarded_p): Do not
+ return true on functions from other partition.
+
+2021-11-06 David Edelsohn <dje.gcc@gmail.com>
+
+ * config/rs6000/vsx.md (vsx_splat_v4si): Change constraints to "wa".
+ (vsx_splat_v4si_di): Change constraint to "wa".
+
+2021-11-06 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/103061
+ * value-relation.cc (path_oracle::path_oracle): Initialize
+ m_killed_defs.
+ (path_oracle::killing_def): Set m_killed_defs.
+ (path_oracle::query_relation): Do not look at the root oracle for
+ killed defs.
+ * value-relation.h (class path_oracle): Add m_killed_defs.
+
+2021-11-06 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (back_threader::find_paths_to_names):
+ Remove gotos and other cleanups.
+
+2021-11-05 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103073
+ * ipa-modref-tree.h (modref_tree::insert): Do nothing for
+ paradoxical and zero sized accesses.
+
+2021-11-05 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103082
+ * ipa-modref-tree.h (struct modref_access_node): Avoid left shift
+ of negative value
+
+2021-11-05 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.h (ASM_GENERATE_INTERNAL_LABEL): Add LTRAMP
+ to the list of symbol prefixes that must be made linker-
+ visible.
+
+2021-11-05 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config.host: Add support for aarch64-*-darwin.
+ * config/aarch64/host-aarch64-darwin.c: New file.
+ * config/aarch64/x-darwin: New file.
+
+2021-11-05 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/103093
+ * gimple-range-gori.cc (range_def_chain::get_imports): Remove assert.
+
+2021-11-05 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/102943
+ * gimple-range-cache.cc (class update_list): New.
+ (update_list::add): Replace add_to_update.
+ (update_list::pop): New.
+ (ranger_cache::ranger_cache): Adjust.
+ (ranger_cache::~ranger_cache): Adjust.
+ (ranger_cache::add_to_update): Delete.
+ (ranger_cache::propagate_cache): Adjust to new class.
+ (ranger_cache::propagate_updated_value): Ditto.
+ (ranger_cache::fill_block_cache): Ditto.
+ * gimple-range-cache.h (class ranger_cache): Adjust to update class.
+
+2021-11-05 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-loop.c (vect_analyze_loop): Remove obsolete
+ comment and expand on another one. Combine nested if.
+
+2021-11-05 John David Anglin <danglin@gcc.gnu.org>
+
+ PR libgomp/96661
+ * config/pa/pa-modes.def: Add OImode integer type.
+ * config/pa/pa.c (pa_scalar_mode_supported_p): Allow TImode
+ for TARGET_64BIT.
+ * config/pa/pa.h (MIN_UNITS_PER_WORD) Define to MIN_UNITS_PER_WORD
+ to UNITS_PER_WORD if IN_LIBGCC2.
+ * config/pa/pa.md (addti3, addvti3, subti3, subvti3, negti2,
+ negvti2, ashlti3, shrpd_internal): New patterns.
+ Change some multi instruction types to multi.
+
+2021-11-05 Jakub Jelinek <jakub@redhat.com>
+
+ PR bootstrap/100246
+ * config/i386/i386.h
+ (stringop_algs::stringop_strategy::stringop_strategy): Make the ctor
+ constexpr.
+
+2021-11-05 Wilco Dijkstra <wdijkstr@arm.com>
+
+ PR target/103085
+ * config/aarch64/aarch64.c (aarch64_mov_operand_p): Strip the salt
+ first.
+ * config/aarch64/constraints.md: Support const in Usw.
+
+2021-11-05 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.h (PREFERRED_DEBUGGING_TYPE): Define to DWARF2_DEBUG.
+ * config/pa/pa64-hpux.h (PREFERRED_DEBUGGING_TYPE): Remove define.
+
+2021-11-05 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (vec_info_shared::n_stmts): Add.
+ (LOOP_VINFO_N_STMTS): Likewise.
+ (vec_info_for_bb): Remove unused function.
+ * tree-vectorizer.c (vec_info_shared::vec_info_shared):
+ Initialize n_stmts member.
+ * tree-vect-loop.c: Remove INCLUDE_FUNCTIONAL.
+ (vect_create_loop_vinfo): Do not set loop->aux.
+ (vect_analyze_loop_2): Do not get n_stmts as argument,
+ instead use LOOP_VINFO_N_STMTS. Set LOOP_VINFO_VECTORIZABLE_P
+ here.
+ (vect_analyze_loop_1): Remove callback, get the mode iterator
+ and autodetected_vector_mode as argument, advancing the
+ iterator and initializing autodetected_vector_mode here.
+ (vect_analyze_loop): Split analysis loop into two, first
+ processing main loops only and then epilogues.
+
+2021-11-05 Martin Jambor <mjambor@suse.cz>
+
+ * ipa-prop.c (compute_complex_assign_jump_func): Remove
+ unnecessary check for RECORD_TYPE.
+
+2021-11-05 Gerald Pfeifer <gerald@pfeifer.com>
+
+ * doc/install.texi2html: Do not generate old.html any longer.
+
+2021-11-05 Martin Liska <mliska@suse.cz>
+
+ PR debug/102955
+ * opts.c (finish_options): Reset flag_gtoggle when it is used.
+
+2021-11-05 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/103046
+ * dwarf2out.c (add_const_value_attribute): Add MODE argument, use it
+ in CONST_WIDE_INT handling. Adjust recursive calls.
+ (add_location_or_const_value_attribute): Pass DECL_MODE (decl) to
+ new add_const_value_attribute argument.
+ (tree_add_const_value_attribute): Pass TYPE_MODE (type) to new
+ add_const_value_attribute argument.
+
+2021-11-05 Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+
+ * config/vx-common.h: Test value of TARGET_VXWORKS7 rather
+ than definedness.
+
+2021-11-05 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (struct vect_loop_form_info): New.
+ (vect_analyze_loop_form): Adjust.
+ (vect_create_loop_vinfo): New.
+ * tree-parloops.c (gather_scalar_reductions): Adjust for
+ vect_analyze_loop_form API change.
+ * tree-vect-loop.c: Include <functional>.
+ (vect_analyze_loop_form_1): Rename to vect_analyze_loop_form,
+ take struct vect_loop_form_info as output parameter and adjust.
+ (vect_analyze_loop_form): Rename to vect_create_loop_vinfo and
+ split out call to the original vect_analyze_loop_form_1.
+ (vect_reanalyze_as_main_loop): Rename to...
+ (vect_analyze_loop_1): ... this, factor out the call to
+ vect_analyze_loop_form and generalize to be able to use it twice ...
+ (vect_analyze_loop): ... here. Perform vect_analyze_loop_form
+ once only and here.
+
+2021-11-05 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ PR target/102991
+ * config/rs6000/fusion.md: Regenerate.
+ * config/rs6000/genfusion.pl: Fix incorrect clobber constraint.
+
+2021-11-04 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * config/s390/s390.h (STACK_CHECK_MOVING_SP): New macro
+ definition.
+
+2021-11-04 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-builtins.c
+ (aarch64_general_gimple_fold_builtin): Add ashl, sshl, ushl, ashr,
+ ashr_simd, lshr, lshr_simd.
+ * config/aarch64/aarch64-simd-builtins.def (lshr): Use USHIFTIMM.
+ * config/aarch64/arm_neon.h (vshr_n_u8, vshr_n_u16, vshr_n_u32,
+ vshrq_n_u8, vshrq_n_u16, vshrq_n_u32, vshrq_n_u64): Fix type hack.
+
+2021-11-04 Tamar Christina <tamar.christina@arm.com>
+
+ * match.pd: New negate+shift pattern.
+
+2021-11-04 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/103079
+ * gimple-range-gori.cc (gimple_range_calc_op1): Treat undefined as
+ varying.
+ (gimple_range_calc_op2): Ditto.
+
+2021-11-04 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/93385
+ * ipa-param-manipulation.h (class ipa_param_body_adjustments): New
+ members remap_with_debug_expressions, m_dead_ssa_debug_equiv,
+ m_dead_stmt_debug_equiv and prepare_debug_expressions. Added
+ parameter to mark_dead_statements.
+ * ipa-param-manipulation.c: Include tree-phinodes.h and cfgexpand.h.
+ (ipa_param_body_adjustments::mark_dead_statements): New parameter
+ debugstack, push into it all SSA names used in debug statements,
+ produce m_dead_ssa_debug_equiv mapping for the removed param.
+ (replace_with_mapped_expr): New function.
+ (ipa_param_body_adjustments::remap_with_debug_expressions): Likewise.
+ (ipa_param_body_adjustments::prepare_debug_expressions): Likewise.
+ (ipa_param_body_adjustments::common_initialization): Gather and
+ procecc SSA which will be removed but are in debug statements. Simplify.
+ (ipa_param_body_adjustments::ipa_param_body_adjustments): Initialize
+ new members.
+ * tree-inline.c (remap_gimple_stmt): Create a debug bind when possible
+ when avoiding a copy of an unnecessary statement. Remap removed SSA
+ names in existing debug statements.
+ (tree_function_versioning): Do not create DEBUG_EXPR_DECL for removed
+ parameters if we have already done so.
+
+2021-11-04 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103058
+ * gimple.c (gimple_call_static_chain_flags): Handle case when
+ nested function does not bind locally.
+
+2021-11-04 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_function_value): Generate
+ a register rtx for Neon vector-tuple modes.
+ (aarch64_layout_arg): Likewise.
+
+2021-11-04 Jonathan Wright <jonathan.wright@arm.com>
+
+ * lower-subreg.c (simple_move): Prevent decomposition if
+ modes are not tieable.
+
+2021-11-04 Jonathan Wright <jonathan.wright@arm.com>
+ Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64-builtins.c (v2x8qi_UP): Define.
+ (v2x4hi_UP): Likewise.
+ (v2x4hf_UP): Likewise.
+ (v2x4bf_UP): Likewise.
+ (v2x2si_UP): Likewise.
+ (v2x2sf_UP): Likewise.
+ (v2x1di_UP): Likewise.
+ (v2x1df_UP): Likewise.
+ (v2x16qi_UP): Likewise.
+ (v2x8hi_UP): Likewise.
+ (v2x8hf_UP): Likewise.
+ (v2x8bf_UP): Likewise.
+ (v2x4si_UP): Likewise.
+ (v2x4sf_UP): Likewise.
+ (v2x2di_UP): Likewise.
+ (v2x2df_UP): Likewise.
+ (v3x8qi_UP): Likewise.
+ (v3x4hi_UP): Likewise.
+ (v3x4hf_UP): Likewise.
+ (v3x4bf_UP): Likewise.
+ (v3x2si_UP): Likewise.
+ (v3x2sf_UP): Likewise.
+ (v3x1di_UP): Likewise.
+ (v3x1df_UP): Likewise.
+ (v3x16qi_UP): Likewise.
+ (v3x8hi_UP): Likewise.
+ (v3x8hf_UP): Likewise.
+ (v3x8bf_UP): Likewise.
+ (v3x4si_UP): Likewise.
+ (v3x4sf_UP): Likewise.
+ (v3x2di_UP): Likewise.
+ (v3x2df_UP): Likewise.
+ (v4x8qi_UP): Likewise.
+ (v4x4hi_UP): Likewise.
+ (v4x4hf_UP): Likewise.
+ (v4x4bf_UP): Likewise.
+ (v4x2si_UP): Likewise.
+ (v4x2sf_UP): Likewise.
+ (v4x1di_UP): Likewise.
+ (v4x1df_UP): Likewise.
+ (v4x16qi_UP): Likewise.
+ (v4x8hi_UP): Likewise.
+ (v4x8hf_UP): Likewise.
+ (v4x8bf_UP): Likewise.
+ (v4x4si_UP): Likewise.
+ (v4x4sf_UP): Likewise.
+ (v4x2di_UP): Likewise.
+ (v4x2df_UP): Likewise.
+ (TYPES_GETREGP): Delete.
+ (TYPES_SETREGP): Likewise.
+ (TYPES_LOADSTRUCT_U): Define.
+ (TYPES_LOADSTRUCT_P): Likewise.
+ (TYPES_LOADSTRUCT_LANE_U): Likewise.
+ (TYPES_LOADSTRUCT_LANE_P): Likewise.
+ (TYPES_STORE1P): Move for consistency.
+ (TYPES_STORESTRUCT_U): Define.
+ (TYPES_STORESTRUCT_P): Likewise.
+ (TYPES_STORESTRUCT_LANE_U): Likewise.
+ (TYPES_STORESTRUCT_LANE_P): Likewise.
+ (aarch64_simd_tuple_types): Define.
+ (aarch64_lookup_simd_builtin_type): Handle tuple type lookup.
+ (aarch64_init_simd_builtin_functions): Update frontend lookup
+ for builtin functions after handling arm_neon.h pragma.
+ (register_tuple_type): Manually set modes of single-integer
+ tuple types. Record tuple types.
+ * config/aarch64/aarch64-modes.def
+ (ADV_SIMD_D_REG_STRUCT_MODES): Define D-register tuple modes.
+ (ADV_SIMD_Q_REG_STRUCT_MODES): Define Q-register tuple modes.
+ (SVE_MODES): Give single-vector modes priority over vector-
+ tuple modes.
+ (VECTOR_MODES_WITH_PREFIX): Set partial-vector mode order to
+ be after all single-vector modes.
+ * config/aarch64/aarch64-simd-builtins.def: Update builtin
+ generator macros to reflect modifications to the backend
+ patterns.
+ * config/aarch64/aarch64-simd.md (aarch64_simd_ld2<mode>):
+ Use vector-tuple mode iterator and rename to...
+ (aarch64_simd_ld2<vstruct_elt>): This.
+ (aarch64_simd_ld2r<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_simd_ld2r<vstruct_elt>): This.
+ (aarch64_vec_load_lanesoi_lane<mode>): Use vector-tuple mode
+ iterator and rename to...
+ (aarch64_vec_load_lanes<mode>_lane<vstruct_elt>): This.
+ (vec_load_lanesoi<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (vec_load_lanes<mode><vstruct_elt>): This.
+ (aarch64_simd_st2<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_simd_st2<vstruct_elt>): This.
+ (aarch64_vec_store_lanesoi_lane<mode>): Use vector-tuple mode
+ iterator and rename to...
+ (aarch64_vec_store_lanes<mode>_lane<vstruct_elt>): This.
+ (vec_store_lanesoi<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (vec_store_lanes<mode><vstruct_elt>): This.
+ (aarch64_simd_ld3<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_simd_ld3<vstruct_elt>): This.
+ (aarch64_simd_ld3r<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_simd_ld3r<vstruct_elt>): This.
+ (aarch64_vec_load_lanesci_lane<mode>): Use vector-tuple mode
+ iterator and rename to...
+ (vec_load_lanesci<mode>): This.
+ (aarch64_simd_st3<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_simd_st3<vstruct_elt>): This.
+ (aarch64_vec_store_lanesci_lane<mode>): Use vector-tuple mode
+ iterator and rename to...
+ (vec_store_lanesci<mode>): This.
+ (aarch64_simd_ld4<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_simd_ld4<vstruct_elt>): This.
+ (aarch64_simd_ld4r<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_simd_ld4r<vstruct_elt>): This.
+ (aarch64_vec_load_lanesxi_lane<mode>): Use vector-tuple mode
+ iterator and rename to...
+ (vec_load_lanesxi<mode>): This.
+ (aarch64_simd_st4<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_simd_st4<vstruct_elt>): This.
+ (aarch64_vec_store_lanesxi_lane<mode>): Use vector-tuple mode
+ iterator and rename to...
+ (vec_store_lanesxi<mode>): This.
+ (mov<mode>): Define for Neon vector-tuple modes.
+ (aarch64_ld1x3<VALLDIF:mode>): Use vector-tuple mode iterator
+ and rename to...
+ (aarch64_ld1x3<vstruct_elt>): This.
+ (aarch64_ld1_x3_<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_ld1_x3_<vstruct_elt>): This.
+ (aarch64_ld1x4<VALLDIF:mode>): Use vector-tuple mode iterator
+ and rename to...
+ (aarch64_ld1x4<vstruct_elt>): This.
+ (aarch64_ld1_x4_<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_ld1_x4_<vstruct_elt>): This.
+ (aarch64_st1x2<VALLDIF:mode>): Use vector-tuple mode iterator
+ and rename to...
+ (aarch64_st1x2<vstruct_elt>): This.
+ (aarch64_st1_x2_<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_st1_x2_<vstruct_elt>): This.
+ (aarch64_st1x3<VALLDIF:mode>): Use vector-tuple mode iterator
+ and rename to...
+ (aarch64_st1x3<vstruct_elt>): This.
+ (aarch64_st1_x3_<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_st1_x3_<vstruct_elt>): This.
+ (aarch64_st1x4<VALLDIF:mode>): Use vector-tuple mode iterator
+ and rename to...
+ (aarch64_st1x4<vstruct_elt>): This.
+ (aarch64_st1_x4_<mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_st1_x4_<vstruct_elt>): This.
+ (*aarch64_mov<mode>): Define for vector-tuple modes.
+ (*aarch64_be_mov<mode>): Likewise.
+ (aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>): Use vector-tuple
+ mode iterator and rename to...
+ (aarch64_ld<nregs>r<vstruct_elt>): This.
+ (aarch64_ld2<mode>_dreg): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_ld2<vstruct_elt>_dreg): This.
+ (aarch64_ld3<mode>_dreg): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_ld3<vstruct_elt>_dreg): This.
+ (aarch64_ld4<mode>_dreg): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_ld4<vstruct_elt>_dreg): This.
+ (aarch64_ld<VSTRUCT:nregs><VDC:mode>): Use vector-tuple mode
+ iterator and rename to...
+ (aarch64_ld<nregs><vstruct_elt>): Use vector-tuple mode
+ iterator and rename to...
+ (aarch64_ld<VSTRUCT:nregs><VQ:mode>): Use vector-tuple mode
+ (aarch64_ld1x2<VQ:mode>): Delete.
+ (aarch64_ld1x2<VDC:mode>): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_ld1x2<vstruct_elt>): This.
+ (aarch64_ld<VSTRUCT:nregs>_lane<VALLDIF:mode>): Use vector-
+ tuple mode iterator and rename to...
+ (aarch64_ld<nregs>_lane<vstruct_elt>): This.
+ (aarch64_get_dreg<VSTRUCT:mode><VDC:mode>): Delete.
+ (aarch64_get_qreg<VSTRUCT:mode><VQ:mode>): Likewise.
+ (aarch64_st2<mode>_dreg): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_st2<vstruct_elt>_dreg): This.
+ (aarch64_st3<mode>_dreg): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_st3<vstruct_elt>_dreg): This.
+ (aarch64_st4<mode>_dreg): Use vector-tuple mode iterator and
+ rename to...
+ (aarch64_st4<vstruct_elt>_dreg): This.
+ (aarch64_st<VSTRUCT:nregs><VDC:mode>): Use vector-tuple mode
+ iterator and rename to...
+ (aarch64_st<nregs><vstruct_elt>): This.
+ (aarch64_st<VSTRUCT:nregs><VQ:mode>): Use vector-tuple mode
+ iterator and rename to aarch64_st<nregs><vstruct_elt>.
+ (aarch64_st<VSTRUCT:nregs>_lane<VALLDIF:mode>): Use vector-
+ tuple mode iterator and rename to...
+ (aarch64_st<nregs>_lane<vstruct_elt>): This.
+ (aarch64_set_qreg<VSTRUCT:mode><VQ:mode>): Delete.
+ (aarch64_simd_ld1<mode>_x2): Use vector-tuple mode iterator
+ and rename to...
+ (aarch64_simd_ld1<vstruct_elt>_x2): This.
+ * config/aarch64/aarch64.c (aarch64_advsimd_struct_mode_p):
+ Refactor to include new vector-tuple modes.
+ (aarch64_classify_vector_mode): Add cases for new vector-
+ tuple modes.
+ (aarch64_advsimd_partial_struct_mode_p): Define.
+ (aarch64_advsimd_full_struct_mode_p): Likewise.
+ (aarch64_advsimd_vector_array_mode): Likewise.
+ (aarch64_sve_data_mode): Change location in file.
+ (aarch64_array_mode): Handle case of Neon vector-tuple modes.
+ (aarch64_hard_regno_nregs): Handle case of partial Neon
+ vector structures.
+ (aarch64_classify_address): Refactor to include handling of
+ Neon vector-tuple modes.
+ (aarch64_print_operand): Print "d" for "%R" for a partial
+ Neon vector structure.
+ (aarch64_expand_vec_perm_1): Use new vector-tuple mode.
+ (aarch64_modes_tieable_p): Prevent tieing Neon partial struct
+ modes with scalar machines modes larger than 8 bytes.
+ (aarch64_can_change_mode_class): Don't allow changes between
+ partial and full Neon vector-structure modes.
+ * config/aarch64/arm_neon.h (vst2_lane_f16): Use updated
+ builtin and remove boiler-plate code for opaque mode.
+ (vst2_lane_f32): Likewise.
+ (vst2_lane_f64): Likewise.
+ (vst2_lane_p8): Likewise.
+ (vst2_lane_p16): Likewise.
+ (vst2_lane_p64): Likewise.
+ (vst2_lane_s8): Likewise.
+ (vst2_lane_s16): Likewise.
+ (vst2_lane_s32): Likewise.
+ (vst2_lane_s64): Likewise.
+ (vst2_lane_u8): Likewise.
+ (vst2_lane_u16): Likewise.
+ (vst2_lane_u32): Likewise.
+ (vst2_lane_u64): Likewise.
+ (vst2q_lane_f16): Likewise.
+ (vst2q_lane_f32): Likewise.
+ (vst2q_lane_f64): Likewise.
+ (vst2q_lane_p8): Likewise.
+ (vst2q_lane_p16): Likewise.
+ (vst2q_lane_p64): Likewise.
+ (vst2q_lane_s8): Likewise.
+ (vst2q_lane_s16): Likewise.
+ (vst2q_lane_s32): Likewise.
+ (vst2q_lane_s64): Likewise.
+ (vst2q_lane_u8): Likewise.
+ (vst2q_lane_u16): Likewise.
+ (vst2q_lane_u32): Likewise.
+ (vst2q_lane_u64): Likewise.
+ (vst3_lane_f16): Likewise.
+ (vst3_lane_f32): Likewise.
+ (vst3_lane_f64): Likewise.
+ (vst3_lane_p8): Likewise.
+ (vst3_lane_p16): Likewise.
+ (vst3_lane_p64): Likewise.
+ (vst3_lane_s8): Likewise.
+ (vst3_lane_s16): Likewise.
+ (vst3_lane_s32): Likewise.
+ (vst3_lane_s64): Likewise.
+ (vst3_lane_u8): Likewise.
+ (vst3_lane_u16): Likewise.
+ (vst3_lane_u32): Likewise.
+ (vst3_lane_u64): Likewise.
+ (vst3q_lane_f16): Likewise.
+ (vst3q_lane_f32): Likewise.
+ (vst3q_lane_f64): Likewise.
+ (vst3q_lane_p8): Likewise.
+ (vst3q_lane_p16): Likewise.
+ (vst3q_lane_p64): Likewise.
+ (vst3q_lane_s8): Likewise.
+ (vst3q_lane_s16): Likewise.
+ (vst3q_lane_s32): Likewise.
+ (vst3q_lane_s64): Likewise.
+ (vst3q_lane_u8): Likewise.
+ (vst3q_lane_u16): Likewise.
+ (vst3q_lane_u32): Likewise.
+ (vst3q_lane_u64): Likewise.
+ (vst4_lane_f16): Likewise.
+ (vst4_lane_f32): Likewise.
+ (vst4_lane_f64): Likewise.
+ (vst4_lane_p8): Likewise.
+ (vst4_lane_p16): Likewise.
+ (vst4_lane_p64): Likewise.
+ (vst4_lane_s8): Likewise.
+ (vst4_lane_s16): Likewise.
+ (vst4_lane_s32): Likewise.
+ (vst4_lane_s64): Likewise.
+ (vst4_lane_u8): Likewise.
+ (vst4_lane_u16): Likewise.
+ (vst4_lane_u32): Likewise.
+ (vst4_lane_u64): Likewise.
+ (vst4q_lane_f16): Likewise.
+ (vst4q_lane_f32): Likewise.
+ (vst4q_lane_f64): Likewise.
+ (vst4q_lane_p8): Likewise.
+ (vst4q_lane_p16): Likewise.
+ (vst4q_lane_p64): Likewise.
+ (vst4q_lane_s8): Likewise.
+ (vst4q_lane_s16): Likewise.
+ (vst4q_lane_s32): Likewise.
+ (vst4q_lane_s64): Likewise.
+ (vst4q_lane_u8): Likewise.
+ (vst4q_lane_u16): Likewise.
+ (vst4q_lane_u32): Likewise.
+ (vst4q_lane_u64): Likewise.
+ (vtbl3_s8): Likewise.
+ (vtbl3_u8): Likewise.
+ (vtbl3_p8): Likewise.
+ (vtbl4_s8): Likewise.
+ (vtbl4_u8): Likewise.
+ (vtbl4_p8): Likewise.
+ (vld1_u8_x3): Likewise.
+ (vld1_s8_x3): Likewise.
+ (vld1_u16_x3): Likewise.
+ (vld1_s16_x3): Likewise.
+ (vld1_u32_x3): Likewise.
+ (vld1_s32_x3): Likewise.
+ (vld1_u64_x3): Likewise.
+ (vld1_s64_x3): Likewise.
+ (vld1_f16_x3): Likewise.
+ (vld1_f32_x3): Likewise.
+ (vld1_f64_x3): Likewise.
+ (vld1_p8_x3): Likewise.
+ (vld1_p16_x3): Likewise.
+ (vld1_p64_x3): Likewise.
+ (vld1q_u8_x3): Likewise.
+ (vld1q_s8_x3): Likewise.
+ (vld1q_u16_x3): Likewise.
+ (vld1q_s16_x3): Likewise.
+ (vld1q_u32_x3): Likewise.
+ (vld1q_s32_x3): Likewise.
+ (vld1q_u64_x3): Likewise.
+ (vld1q_s64_x3): Likewise.
+ (vld1q_f16_x3): Likewise.
+ (vld1q_f32_x3): Likewise.
+ (vld1q_f64_x3): Likewise.
+ (vld1q_p8_x3): Likewise.
+ (vld1q_p16_x3): Likewise.
+ (vld1q_p64_x3): Likewise.
+ (vld1_u8_x2): Likewise.
+ (vld1_s8_x2): Likewise.
+ (vld1_u16_x2): Likewise.
+ (vld1_s16_x2): Likewise.
+ (vld1_u32_x2): Likewise.
+ (vld1_s32_x2): Likewise.
+ (vld1_u64_x2): Likewise.
+ (vld1_s64_x2): Likewise.
+ (vld1_f16_x2): Likewise.
+ (vld1_f32_x2): Likewise.
+ (vld1_f64_x2): Likewise.
+ (vld1_p8_x2): Likewise.
+ (vld1_p16_x2): Likewise.
+ (vld1_p64_x2): Likewise.
+ (vld1q_u8_x2): Likewise.
+ (vld1q_s8_x2): Likewise.
+ (vld1q_u16_x2): Likewise.
+ (vld1q_s16_x2): Likewise.
+ (vld1q_u32_x2): Likewise.
+ (vld1q_s32_x2): Likewise.
+ (vld1q_u64_x2): Likewise.
+ (vld1q_s64_x2): Likewise.
+ (vld1q_f16_x2): Likewise.
+ (vld1q_f32_x2): Likewise.
+ (vld1q_f64_x2): Likewise.
+ (vld1q_p8_x2): Likewise.
+ (vld1q_p16_x2): Likewise.
+ (vld1q_p64_x2): Likewise.
+ (vld1_s8_x4): Likewise.
+ (vld1q_s8_x4): Likewise.
+ (vld1_s16_x4): Likewise.
+ (vld1q_s16_x4): Likewise.
+ (vld1_s32_x4): Likewise.
+ (vld1q_s32_x4): Likewise.
+ (vld1_u8_x4): Likewise.
+ (vld1q_u8_x4): Likewise.
+ (vld1_u16_x4): Likewise.
+ (vld1q_u16_x4): Likewise.
+ (vld1_u32_x4): Likewise.
+ (vld1q_u32_x4): Likewise.
+ (vld1_f16_x4): Likewise.
+ (vld1q_f16_x4): Likewise.
+ (vld1_f32_x4): Likewise.
+ (vld1q_f32_x4): Likewise.
+ (vld1_p8_x4): Likewise.
+ (vld1q_p8_x4): Likewise.
+ (vld1_p16_x4): Likewise.
+ (vld1q_p16_x4): Likewise.
+ (vld1_s64_x4): Likewise.
+ (vld1_u64_x4): Likewise.
+ (vld1_p64_x4): Likewise.
+ (vld1q_s64_x4): Likewise.
+ (vld1q_u64_x4): Likewise.
+ (vld1q_p64_x4): Likewise.
+ (vld1_f64_x4): Likewise.
+ (vld1q_f64_x4): Likewise.
+ (vld2_s64): Likewise.
+ (vld2_u64): Likewise.
+ (vld2_f64): Likewise.
+ (vld2_s8): Likewise.
+ (vld2_p8): Likewise.
+ (vld2_p64): Likewise.
+ (vld2_s16): Likewise.
+ (vld2_p16): Likewise.
+ (vld2_s32): Likewise.
+ (vld2_u8): Likewise.
+ (vld2_u16): Likewise.
+ (vld2_u32): Likewise.
+ (vld2_f16): Likewise.
+ (vld2_f32): Likewise.
+ (vld2q_s8): Likewise.
+ (vld2q_p8): Likewise.
+ (vld2q_s16): Likewise.
+ (vld2q_p16): Likewise.
+ (vld2q_p64): Likewise.
+ (vld2q_s32): Likewise.
+ (vld2q_s64): Likewise.
+ (vld2q_u8): Likewise.
+ (vld2q_u16): Likewise.
+ (vld2q_u32): Likewise.
+ (vld2q_u64): Likewise.
+ (vld2q_f16): Likewise.
+ (vld2q_f32): Likewise.
+ (vld2q_f64): Likewise.
+ (vld3_s64): Likewise.
+ (vld3_u64): Likewise.
+ (vld3_f64): Likewise.
+ (vld3_s8): Likewise.
+ (vld3_p8): Likewise.
+ (vld3_s16): Likewise.
+ (vld3_p16): Likewise.
+ (vld3_s32): Likewise.
+ (vld3_u8): Likewise.
+ (vld3_u16): Likewise.
+ (vld3_u32): Likewise.
+ (vld3_f16): Likewise.
+ (vld3_f32): Likewise.
+ (vld3_p64): Likewise.
+ (vld3q_s8): Likewise.
+ (vld3q_p8): Likewise.
+ (vld3q_s16): Likewise.
+ (vld3q_p16): Likewise.
+ (vld3q_s32): Likewise.
+ (vld3q_s64): Likewise.
+ (vld3q_u8): Likewise.
+ (vld3q_u16): Likewise.
+ (vld3q_u32): Likewise.
+ (vld3q_u64): Likewise.
+ (vld3q_f16): Likewise.
+ (vld3q_f32): Likewise.
+ (vld3q_f64): Likewise.
+ (vld3q_p64): Likewise.
+ (vld4_s64): Likewise.
+ (vld4_u64): Likewise.
+ (vld4_f64): Likewise.
+ (vld4_s8): Likewise.
+ (vld4_p8): Likewise.
+ (vld4_s16): Likewise.
+ (vld4_p16): Likewise.
+ (vld4_s32): Likewise.
+ (vld4_u8): Likewise.
+ (vld4_u16): Likewise.
+ (vld4_u32): Likewise.
+ (vld4_f16): Likewise.
+ (vld4_f32): Likewise.
+ (vld4_p64): Likewise.
+ (vld4q_s8): Likewise.
+ (vld4q_p8): Likewise.
+ (vld4q_s16): Likewise.
+ (vld4q_p16): Likewise.
+ (vld4q_s32): Likewise.
+ (vld4q_s64): Likewise.
+ (vld4q_u8): Likewise.
+ (vld4q_u16): Likewise.
+ (vld4q_u32): Likewise.
+ (vld4q_u64): Likewise.
+ (vld4q_f16): Likewise.
+ (vld4q_f32): Likewise.
+ (vld4q_f64): Likewise.
+ (vld4q_p64): Likewise.
+ (vld2_dup_s8): Likewise.
+ (vld2_dup_s16): Likewise.
+ (vld2_dup_s32): Likewise.
+ (vld2_dup_f16): Likewise.
+ (vld2_dup_f32): Likewise.
+ (vld2_dup_f64): Likewise.
+ (vld2_dup_u8): Likewise.
+ (vld2_dup_u16): Likewise.
+ (vld2_dup_u32): Likewise.
+ (vld2_dup_p8): Likewise.
+ (vld2_dup_p16): Likewise.
+ (vld2_dup_p64): Likewise.
+ (vld2_dup_s64): Likewise.
+ (vld2_dup_u64): Likewise.
+ (vld2q_dup_s8): Likewise.
+ (vld2q_dup_p8): Likewise.
+ (vld2q_dup_s16): Likewise.
+ (vld2q_dup_p16): Likewise.
+ (vld2q_dup_s32): Likewise.
+ (vld2q_dup_s64): Likewise.
+ (vld2q_dup_u8): Likewise.
+ (vld2q_dup_u16): Likewise.
+ (vld2q_dup_u32): Likewise.
+ (vld2q_dup_u64): Likewise.
+ (vld2q_dup_f16): Likewise.
+ (vld2q_dup_f32): Likewise.
+ (vld2q_dup_f64): Likewise.
+ (vld2q_dup_p64): Likewise.
+ (vld3_dup_s64): Likewise.
+ (vld3_dup_u64): Likewise.
+ (vld3_dup_f64): Likewise.
+ (vld3_dup_s8): Likewise.
+ (vld3_dup_p8): Likewise.
+ (vld3_dup_s16): Likewise.
+ (vld3_dup_p16): Likewise.
+ (vld3_dup_s32): Likewise.
+ (vld3_dup_u8): Likewise.
+ (vld3_dup_u16): Likewise.
+ (vld3_dup_u32): Likewise.
+ (vld3_dup_f16): Likewise.
+ (vld3_dup_f32): Likewise.
+ (vld3_dup_p64): Likewise.
+ (vld3q_dup_s8): Likewise.
+ (vld3q_dup_p8): Likewise.
+ (vld3q_dup_s16): Likewise.
+ (vld3q_dup_p16): Likewise.
+ (vld3q_dup_s32): Likewise.
+ (vld3q_dup_s64): Likewise.
+ (vld3q_dup_u8): Likewise.
+ (vld3q_dup_u16): Likewise.
+ (vld3q_dup_u32): Likewise.
+ (vld3q_dup_u64): Likewise.
+ (vld3q_dup_f16): Likewise.
+ (vld3q_dup_f32): Likewise.
+ (vld3q_dup_f64): Likewise.
+ (vld3q_dup_p64): Likewise.
+ (vld4_dup_s64): Likewise.
+ (vld4_dup_u64): Likewise.
+ (vld4_dup_f64): Likewise.
+ (vld4_dup_s8): Likewise.
+ (vld4_dup_p8): Likewise.
+ (vld4_dup_s16): Likewise.
+ (vld4_dup_p16): Likewise.
+ (vld4_dup_s32): Likewise.
+ (vld4_dup_u8): Likewise.
+ (vld4_dup_u16): Likewise.
+ (vld4_dup_u32): Likewise.
+ (vld4_dup_f16): Likewise.
+ (vld4_dup_f32): Likewise.
+ (vld4_dup_p64): Likewise.
+ (vld4q_dup_s8): Likewise.
+ (vld4q_dup_p8): Likewise.
+ (vld4q_dup_s16): Likewise.
+ (vld4q_dup_p16): Likewise.
+ (vld4q_dup_s32): Likewise.
+ (vld4q_dup_s64): Likewise.
+ (vld4q_dup_u8): Likewise.
+ (vld4q_dup_u16): Likewise.
+ (vld4q_dup_u32): Likewise.
+ (vld4q_dup_u64): Likewise.
+ (vld4q_dup_f16): Likewise.
+ (vld4q_dup_f32): Likewise.
+ (vld4q_dup_f64): Likewise.
+ (vld4q_dup_p64): Likewise.
+ (vld2_lane_u8): Likewise.
+ (vld2_lane_u16): Likewise.
+ (vld2_lane_u32): Likewise.
+ (vld2_lane_u64): Likewise.
+ (vld2_lane_s8): Likewise.
+ (vld2_lane_s16): Likewise.
+ (vld2_lane_s32): Likewise.
+ (vld2_lane_s64): Likewise.
+ (vld2_lane_f16): Likewise.
+ (vld2_lane_f32): Likewise.
+ (vld2_lane_f64): Likewise.
+ (vld2_lane_p8): Likewise.
+ (vld2_lane_p16): Likewise.
+ (vld2_lane_p64): Likewise.
+ (vld2q_lane_u8): Likewise.
+ (vld2q_lane_u16): Likewise.
+ (vld2q_lane_u32): Likewise.
+ (vld2q_lane_u64): Likewise.
+ (vld2q_lane_s8): Likewise.
+ (vld2q_lane_s16): Likewise.
+ (vld2q_lane_s32): Likewise.
+ (vld2q_lane_s64): Likewise.
+ (vld2q_lane_f16): Likewise.
+ (vld2q_lane_f32): Likewise.
+ (vld2q_lane_f64): Likewise.
+ (vld2q_lane_p8): Likewise.
+ (vld2q_lane_p16): Likewise.
+ (vld2q_lane_p64): Likewise.
+ (vld3_lane_u8): Likewise.
+ (vld3_lane_u16): Likewise.
+ (vld3_lane_u32): Likewise.
+ (vld3_lane_u64): Likewise.
+ (vld3_lane_s8): Likewise.
+ (vld3_lane_s16): Likewise.
+ (vld3_lane_s32): Likewise.
+ (vld3_lane_s64): Likewise.
+ (vld3_lane_f16): Likewise.
+ (vld3_lane_f32): Likewise.
+ (vld3_lane_f64): Likewise.
+ (vld3_lane_p8): Likewise.
+ (vld3_lane_p16): Likewise.
+ (vld3_lane_p64): Likewise.
+ (vld3q_lane_u8): Likewise.
+ (vld3q_lane_u16): Likewise.
+ (vld3q_lane_u32): Likewise.
+ (vld3q_lane_u64): Likewise.
+ (vld3q_lane_s8): Likewise.
+ (vld3q_lane_s16): Likewise.
+ (vld3q_lane_s32): Likewise.
+ (vld3q_lane_s64): Likewise.
+ (vld3q_lane_f16): Likewise.
+ (vld3q_lane_f32): Likewise.
+ (vld3q_lane_f64): Likewise.
+ (vld3q_lane_p8): Likewise.
+ (vld3q_lane_p16): Likewise.
+ (vld3q_lane_p64): Likewise.
+ (vld4_lane_u8): Likewise.
+ (vld4_lane_u16): Likewise.
+ (vld4_lane_u32): Likewise.
+ (vld4_lane_u64): Likewise.
+ (vld4_lane_s8): Likewise.
+ (vld4_lane_s16): Likewise.
+ (vld4_lane_s32): Likewise.
+ (vld4_lane_s64): Likewise.
+ (vld4_lane_f16): Likewise.
+ (vld4_lane_f32): Likewise.
+ (vld4_lane_f64): Likewise.
+ (vld4_lane_p8): Likewise.
+ (vld4_lane_p16): Likewise.
+ (vld4_lane_p64): Likewise.
+ (vld4q_lane_u8): Likewise.
+ (vld4q_lane_u16): Likewise.
+ (vld4q_lane_u32): Likewise.
+ (vld4q_lane_u64): Likewise.
+ (vld4q_lane_s8): Likewise.
+ (vld4q_lane_s16): Likewise.
+ (vld4q_lane_s32): Likewise.
+ (vld4q_lane_s64): Likewise.
+ (vld4q_lane_f16): Likewise.
+ (vld4q_lane_f32): Likewise.
+ (vld4q_lane_f64): Likewise.
+ (vld4q_lane_p8): Likewise.
+ (vld4q_lane_p16): Likewise.
+ (vld4q_lane_p64): Likewise.
+ (vqtbl2_s8): Likewise.
+ (vqtbl2_u8): Likewise.
+ (vqtbl2_p8): Likewise.
+ (vqtbl2q_s8): Likewise.
+ (vqtbl2q_u8): Likewise.
+ (vqtbl2q_p8): Likewise.
+ (vqtbl3_s8): Likewise.
+ (vqtbl3_u8): Likewise.
+ (vqtbl3_p8): Likewise.
+ (vqtbl3q_s8): Likewise.
+ (vqtbl3q_u8): Likewise.
+ (vqtbl3q_p8): Likewise.
+ (vqtbl4_s8): Likewise.
+ (vqtbl4_u8): Likewise.
+ (vqtbl4_p8): Likewise.
+ (vqtbl4q_s8): Likewise.
+ (vqtbl4q_u8): Likewise.
+ (vqtbl4q_p8): Likewise.
+ (vqtbx2_s8): Likewise.
+ (vqtbx2_u8): Likewise.
+ (vqtbx2_p8): Likewise.
+ (vqtbx2q_s8): Likewise.
+ (vqtbx2q_u8): Likewise.
+ (vqtbx2q_p8): Likewise.
+ (vqtbx3_s8): Likewise.
+ (vqtbx3_u8): Likewise.
+ (vqtbx3_p8): Likewise.
+ (vqtbx3q_s8): Likewise.
+ (vqtbx3q_u8): Likewise.
+ (vqtbx3q_p8): Likewise.
+ (vqtbx4_s8): Likewise.
+ (vqtbx4_u8): Likewise.
+ (vqtbx4_p8): Likewise.
+ (vqtbx4q_s8): Likewise.
+ (vqtbx4q_u8): Likewise.
+ (vqtbx4q_p8): Likewise.
+ (vst1_s64_x2): Likewise.
+ (vst1_u64_x2): Likewise.
+ (vst1_f64_x2): Likewise.
+ (vst1_s8_x2): Likewise.
+ (vst1_p8_x2): Likewise.
+ (vst1_s16_x2): Likewise.
+ (vst1_p16_x2): Likewise.
+ (vst1_s32_x2): Likewise.
+ (vst1_u8_x2): Likewise.
+ (vst1_u16_x2): Likewise.
+ (vst1_u32_x2): Likewise.
+ (vst1_f16_x2): Likewise.
+ (vst1_f32_x2): Likewise.
+ (vst1_p64_x2): Likewise.
+ (vst1q_s8_x2): Likewise.
+ (vst1q_p8_x2): Likewise.
+ (vst1q_s16_x2): Likewise.
+ (vst1q_p16_x2): Likewise.
+ (vst1q_s32_x2): Likewise.
+ (vst1q_s64_x2): Likewise.
+ (vst1q_u8_x2): Likewise.
+ (vst1q_u16_x2): Likewise.
+ (vst1q_u32_x2): Likewise.
+ (vst1q_u64_x2): Likewise.
+ (vst1q_f16_x2): Likewise.
+ (vst1q_f32_x2): Likewise.
+ (vst1q_f64_x2): Likewise.
+ (vst1q_p64_x2): Likewise.
+ (vst1_s64_x3): Likewise.
+ (vst1_u64_x3): Likewise.
+ (vst1_f64_x3): Likewise.
+ (vst1_s8_x3): Likewise.
+ (vst1_p8_x3): Likewise.
+ (vst1_s16_x3): Likewise.
+ (vst1_p16_x3): Likewise.
+ (vst1_s32_x3): Likewise.
+ (vst1_u8_x3): Likewise.
+ (vst1_u16_x3): Likewise.
+ (vst1_u32_x3): Likewise.
+ (vst1_f16_x3): Likewise.
+ (vst1_f32_x3): Likewise.
+ (vst1_p64_x3): Likewise.
+ (vst1q_s8_x3): Likewise.
+ (vst1q_p8_x3): Likewise.
+ (vst1q_s16_x3): Likewise.
+ (vst1q_p16_x3): Likewise.
+ (vst1q_s32_x3): Likewise.
+ (vst1q_s64_x3): Likewise.
+ (vst1q_u8_x3): Likewise.
+ (vst1q_u16_x3): Likewise.
+ (vst1q_u32_x3): Likewise.
+ (vst1q_u64_x3): Likewise.
+ (vst1q_f16_x3): Likewise.
+ (vst1q_f32_x3): Likewise.
+ (vst1q_f64_x3): Likewise.
+ (vst1q_p64_x3): Likewise.
+ (vst1_s8_x4): Likewise.
+ (vst1q_s8_x4): Likewise.
+ (vst1_s16_x4): Likewise.
+ (vst1q_s16_x4): Likewise.
+ (vst1_s32_x4): Likewise.
+ (vst1q_s32_x4): Likewise.
+ (vst1_u8_x4): Likewise.
+ (vst1q_u8_x4): Likewise.
+ (vst1_u16_x4): Likewise.
+ (vst1q_u16_x4): Likewise.
+ (vst1_u32_x4): Likewise.
+ (vst1q_u32_x4): Likewise.
+ (vst1_f16_x4): Likewise.
+ (vst1q_f16_x4): Likewise.
+ (vst1_f32_x4): Likewise.
+ (vst1q_f32_x4): Likewise.
+ (vst1_p8_x4): Likewise.
+ (vst1q_p8_x4): Likewise.
+ (vst1_p16_x4): Likewise.
+ (vst1q_p16_x4): Likewise.
+ (vst1_s64_x4): Likewise.
+ (vst1_u64_x4): Likewise.
+ (vst1_p64_x4): Likewise.
+ (vst1q_s64_x4): Likewise.
+ (vst1q_u64_x4): Likewise.
+ (vst1q_p64_x4): Likewise.
+ (vst1_f64_x4): Likewise.
+ (vst1q_f64_x4): Likewise.
+ (vst2_s64): Likewise.
+ (vst2_u64): Likewise.
+ (vst2_f64): Likewise.
+ (vst2_s8): Likewise.
+ (vst2_p8): Likewise.
+ (vst2_s16): Likewise.
+ (vst2_p16): Likewise.
+ (vst2_s32): Likewise.
+ (vst2_u8): Likewise.
+ (vst2_u16): Likewise.
+ (vst2_u32): Likewise.
+ (vst2_f16): Likewise.
+ (vst2_f32): Likewise.
+ (vst2_p64): Likewise.
+ (vst2q_s8): Likewise.
+ (vst2q_p8): Likewise.
+ (vst2q_s16): Likewise.
+ (vst2q_p16): Likewise.
+ (vst2q_s32): Likewise.
+ (vst2q_s64): Likewise.
+ (vst2q_u8): Likewise.
+ (vst2q_u16): Likewise.
+ (vst2q_u32): Likewise.
+ (vst2q_u64): Likewise.
+ (vst2q_f16): Likewise.
+ (vst2q_f32): Likewise.
+ (vst2q_f64): Likewise.
+ (vst2q_p64): Likewise.
+ (vst3_s64): Likewise.
+ (vst3_u64): Likewise.
+ (vst3_f64): Likewise.
+ (vst3_s8): Likewise.
+ (vst3_p8): Likewise.
+ (vst3_s16): Likewise.
+ (vst3_p16): Likewise.
+ (vst3_s32): Likewise.
+ (vst3_u8): Likewise.
+ (vst3_u16): Likewise.
+ (vst3_u32): Likewise.
+ (vst3_f16): Likewise.
+ (vst3_f32): Likewise.
+ (vst3_p64): Likewise.
+ (vst3q_s8): Likewise.
+ (vst3q_p8): Likewise.
+ (vst3q_s16): Likewise.
+ (vst3q_p16): Likewise.
+ (vst3q_s32): Likewise.
+ (vst3q_s64): Likewise.
+ (vst3q_u8): Likewise.
+ (vst3q_u16): Likewise.
+ (vst3q_u32): Likewise.
+ (vst3q_u64): Likewise.
+ (vst3q_f16): Likewise.
+ (vst3q_f32): Likewise.
+ (vst3q_f64): Likewise.
+ (vst3q_p64): Likewise.
+ (vst4_s64): Likewise.
+ (vst4_u64): Likewise.
+ (vst4_f64): Likewise.
+ (vst4_s8): Likewise.
+ (vst4_p8): Likewise.
+ (vst4_s16): Likewise.
+ (vst4_p16): Likewise.
+ (vst4_s32): Likewise.
+ (vst4_u8): Likewise.
+ (vst4_u16): Likewise.
+ (vst4_u32): Likewise.
+ (vst4_f16): Likewise.
+ (vst4_f32): Likewise.
+ (vst4_p64): Likewise.
+ (vst4q_s8): Likewise.
+ (vst4q_p8): Likewise.
+ (vst4q_s16): Likewise.
+ (vst4q_p16): Likewise.
+ (vst4q_s32): Likewise.
+ (vst4q_s64): Likewise.
+ (vst4q_u8): Likewise.
+ (vst4q_u16): Likewise.
+ (vst4q_u32): Likewise.
+ (vst4q_u64): Likewise.
+ (vst4q_f16): Likewise.
+ (vst4q_f32): Likewise.
+ (vst4q_f64): Likewise.
+ (vst4q_p64): Likewise.
+ (vtbx4_s8): Likewise.
+ (vtbx4_u8): Likewise.
+ (vtbx4_p8): Likewise.
+ (vld1_bf16_x2): Likewise.
+ (vld1q_bf16_x2): Likewise.
+ (vld1_bf16_x3): Likewise.
+ (vld1q_bf16_x3): Likewise.
+ (vld1_bf16_x4): Likewise.
+ (vld1q_bf16_x4): Likewise.
+ (vld2_bf16): Likewise.
+ (vld2q_bf16): Likewise.
+ (vld2_dup_bf16): Likewise.
+ (vld2q_dup_bf16): Likewise.
+ (vld3_bf16): Likewise.
+ (vld3q_bf16): Likewise.
+ (vld3_dup_bf16): Likewise.
+ (vld3q_dup_bf16): Likewise.
+ (vld4_bf16): Likewise.
+ (vld4q_bf16): Likewise.
+ (vld4_dup_bf16): Likewise.
+ (vld4q_dup_bf16): Likewise.
+ (vst1_bf16_x2): Likewise.
+ (vst1q_bf16_x2): Likewise.
+ (vst1_bf16_x3): Likewise.
+ (vst1q_bf16_x3): Likewise.
+ (vst1_bf16_x4): Likewise.
+ (vst1q_bf16_x4): Likewise.
+ (vst2_bf16): Likewise.
+ (vst2q_bf16): Likewise.
+ (vst3_bf16): Likewise.
+ (vst3q_bf16): Likewise.
+ (vst4_bf16): Likewise.
+ (vst4q_bf16): Likewise.
+ (vld2_lane_bf16): Likewise.
+ (vld2q_lane_bf16): Likewise.
+ (vld3_lane_bf16): Likewise.
+ (vld3q_lane_bf16): Likewise.
+ (vld4_lane_bf16): Likewise.
+ (vld4q_lane_bf16): Likewise.
+ (vst2_lane_bf16): Likewise.
+ (vst2q_lane_bf16): Likewise.
+ (vst3_lane_bf16): Likewise.
+ (vst3q_lane_bf16): Likewise.
+ (vst4_lane_bf16): Likewise.
+ (vst4q_lane_bf16): Likewise.
+ * config/aarch64/geniterators.sh: Modify iterator regex to
+ match new vector-tuple modes.
+ * config/aarch64/iterators.md (insn_count): Extend mode
+ attribute with vector-tuple type information.
+ (nregs): Likewise.
+ (Vendreg): Likewise.
+ (Vetype): Likewise.
+ (Vtype): Likewise.
+ (VSTRUCT_2D): New mode iterator.
+ (VSTRUCT_2DNX): Likewise.
+ (VSTRUCT_2DX): Likewise.
+ (VSTRUCT_2Q): Likewise.
+ (VSTRUCT_2QD): Likewise.
+ (VSTRUCT_3D): Likewise.
+ (VSTRUCT_3DNX): Likewise.
+ (VSTRUCT_3DX): Likewise.
+ (VSTRUCT_3Q): Likewise.
+ (VSTRUCT_3QD): Likewise.
+ (VSTRUCT_4D): Likewise.
+ (VSTRUCT_4DNX): Likewise.
+ (VSTRUCT_4DX): Likewise.
+ (VSTRUCT_4Q): Likewise.
+ (VSTRUCT_4QD): Likewise.
+ (VSTRUCT_D): Likewise.
+ (VSTRUCT_Q): Likewise.
+ (VSTRUCT_QD): Likewise.
+ (VSTRUCT_ELT): New mode attribute.
+ (vstruct_elt): Likewise.
+ * genmodes.c (VECTOR_MODE): Add default prefix and order
+ parameters.
+ (VECTOR_MODE_WITH_PREFIX): Define.
+ (make_vector_mode): Add mode prefix and order parameters.
+
+2021-11-04 Jonathan Wright <jonathan.wright@arm.com>
+
+ * expmed.c (extract_bit_field_1): Ensure modes are tieable.
+
+2021-11-04 Jonathan Wright <jonathan.wright@arm.com>
+
+ * expr.c (emit_group_load_1): Remove historic workaround.
+
+2021-11-04 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-builtins.c (aarch64_init_simd_builtins):
+ Factor out main loop to...
+ (aarch64_init_simd_builtin_functions): This new function.
+ (register_tuple_type): Define.
+ (aarch64_scalar_builtin_type_p): Define.
+ (handle_arm_neon_h): Define.
+ * config/aarch64/aarch64-c.c (aarch64_pragma_aarch64): Handle
+ pragma for arm_neon.h.
+ * config/aarch64/aarch64-protos.h (aarch64_advsimd_struct_mode_p):
+ Declare.
+ (handle_arm_neon_h): Likewise.
+ * config/aarch64/aarch64.c (aarch64_advsimd_struct_mode_p):
+ Remove static modifier.
+ * config/aarch64/arm_neon.h (target): Remove Neon vector
+ structure type definitions.
+
+2021-11-04 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/102943
+ * gimple-range-path.cc (path_range_query::range_on_path_entry):
+ Prefer range_of_expr unless there are no statements in the BB.
+
+2021-11-04 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/102943
+ * tree-ssa-threadbackward.c (back_threader::find_paths_to_names):
+ Avoid duplicate calculation of paths.
+
+2021-11-04 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/102943
+ * gimple-range-path.cc (path_range_query::compute_phi_relations):
+ Only compute relations for SSA names in the import list.
+ (path_range_query::compute_outgoing_relations): Same.
+ * gimple-range-path.h (path_range_query::import_p): New.
+
+2021-11-04 Richard Biener <rguenther@suse.de>
+
+ PR rtl-optimization/103075
+ * simplify-rtx.c (exact_int_to_float_conversion_p): Return
+ false for a VOIDmode operand.
+
+2021-11-04 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_vector_costs): Make member
+ variables private and add "m_" to their names. Remove is_loop.
+ (aarch64_record_potential_advsimd_unrolling): Replace with...
+ (aarch64_vector_costs::record_potential_advsimd_unrolling): ...this.
+ (aarch64_analyze_loop_vinfo): Replace with...
+ (aarch64_vector_costs::analyze_loop_vinfo): ...this.
+ Move initialization of (m_)vec_flags to add_stmt_cost.
+ (aarch64_analyze_bb_vinfo): Delete.
+ (aarch64_count_ops): Replace with...
+ (aarch64_vector_costs::count_ops): ...this.
+ (aarch64_vector_costs::add_stmt_cost): Set m_vec_flags,
+ using m_costing_for_scalar to test whether we're costing
+ scalar or vector code.
+ (aarch64_adjust_body_cost_sve): Replace with...
+ (aarch64_vector_costs::adjust_body_cost_sve): ...this.
+ (aarch64_adjust_body_cost): Replace with...
+ (aarch64_vector_costs::adjust_body_cost): ...this.
+ (aarch64_vector_costs::finish_cost): Use m_vinfo instead of is_loop.
+
+2021-11-04 Richard Sandiford <richard.sandiford@arm.com>
+
+ * target.def (targetm.vectorize.init_cost): Replace with...
+ (targetm.vectorize.create_costs): ...this.
+ (targetm.vectorize.add_stmt_cost): Delete.
+ (targetm.vectorize.finish_cost): Likewise.
+ (targetm.vectorize.destroy_cost_data): Likewise.
+ * doc/tm.texi.in (TARGET_VECTORIZE_INIT_COST): Replace with...
+ (TARGET_VECTORIZE_CREATE_COSTS): ...this.
+ (TARGET_VECTORIZE_ADD_STMT_COST): Delete.
+ (TARGET_VECTORIZE_FINISH_COST): Likewise.
+ (TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
+ * doc/tm.texi: Regenerate.
+ * tree-vectorizer.h (vec_info::vec_info): Remove target_cost_data
+ parameter.
+ (vec_info::target_cost_data): Change from a void * to a vector_costs *.
+ (vector_costs): New class.
+ (init_cost): Take a vec_info and return a vector_costs.
+ (dump_stmt_cost): Remove data parameter.
+ (add_stmt_cost): Replace vinfo and data parameters with a vector_costs.
+ (add_stmt_costs): Likewise.
+ (finish_cost): Replace data parameter with a vector_costs.
+ (destroy_cost_data): Delete.
+ * tree-vectorizer.c (dump_stmt_cost): Remove data argument and
+ don't print it.
+ (vec_info::vec_info): Remove the target_cost_data parameter and
+ initialize the member variable to null instead.
+ (vec_info::~vec_info): Delete target_cost_data instead of calling
+ destroy_cost_data.
+ (vector_costs::add_stmt_cost): New function.
+ (vector_costs::finish_cost): Likewise.
+ (vector_costs::record_stmt_cost): Likewise.
+ (vector_costs::adjust_cost_for_freq): Likewise.
+ * tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Update
+ call to vec_info::vec_info.
+ (vect_compute_single_scalar_iteration_cost): Update after above
+ changes to costing interface.
+ (vect_analyze_loop_operations): Likewise.
+ (vect_estimate_min_profitable_iters): Likewise.
+ (vect_analyze_loop_2): Initialize LOOP_VINFO_TARGET_COST_DATA
+ at the start_over point, where it needs to be recreated after
+ trying without slp. Update retry code accordingly.
+ * tree-vect-slp.c (_bb_vec_info::_bb_vec_info): Update call
+ to vec_info::vec_info.
+ (vect_slp_analyze_operation): Update after above changes to costing
+ interface.
+ (vect_bb_vectorization_profitable_p): Likewise.
+ * targhooks.h (default_init_cost): Replace with...
+ (default_vectorize_create_costs): ...this.
+ (default_add_stmt_cost): Delete.
+ (default_finish_cost, default_destroy_cost_data): Likewise.
+ * targhooks.c (default_init_cost): Replace with...
+ (default_vectorize_create_costs): ...this.
+ (default_add_stmt_cost): Delete, moving logic to vector_costs instead.
+ (default_finish_cost, default_destroy_cost_data): Delete.
+ * config/aarch64/aarch64.c (aarch64_vector_costs): Inherit from
+ vector_costs. Add a constructor.
+ (aarch64_init_cost): Replace with...
+ (aarch64_vectorize_create_costs): ...this.
+ (aarch64_add_stmt_cost): Replace with...
+ (aarch64_vector_costs::add_stmt_cost): ...this. Use record_stmt_cost
+ to adjust the cost for inner loops.
+ (aarch64_finish_cost): Replace with...
+ (aarch64_vector_costs::finish_cost): ...this.
+ (aarch64_destroy_cost_data): Delete.
+ (TARGET_VECTORIZE_INIT_COST): Replace with...
+ (TARGET_VECTORIZE_CREATE_COSTS): ...this.
+ (TARGET_VECTORIZE_ADD_STMT_COST): Delete.
+ (TARGET_VECTORIZE_FINISH_COST): Likewise.
+ (TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
+ * config/i386/i386.c (ix86_vector_costs): New structure.
+ (ix86_init_cost): Replace with...
+ (ix86_vectorize_create_costs): ...this.
+ (ix86_add_stmt_cost): Replace with...
+ (ix86_vector_costs::add_stmt_cost): ...this. Use adjust_cost_for_freq
+ to adjust the cost for inner loops.
+ (ix86_finish_cost, ix86_destroy_cost_data): Delete.
+ (TARGET_VECTORIZE_INIT_COST): Replace with...
+ (TARGET_VECTORIZE_CREATE_COSTS): ...this.
+ (TARGET_VECTORIZE_ADD_STMT_COST): Delete.
+ (TARGET_VECTORIZE_FINISH_COST): Likewise.
+ (TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
+ * config/rs6000/rs6000.c (TARGET_VECTORIZE_INIT_COST): Replace with...
+ (TARGET_VECTORIZE_CREATE_COSTS): ...this.
+ (TARGET_VECTORIZE_ADD_STMT_COST): Delete.
+ (TARGET_VECTORIZE_FINISH_COST): Likewise.
+ (TARGET_VECTORIZE_DESTROY_COST_DATA): Likewise.
+ (rs6000_cost_data): Inherit from vector_costs.
+ Add a constructor. Drop loop_info, cost and costing_for_scalar
+ in favor of the corresponding vector_costs member variables.
+ Add "m_" to the names of the remaining member variables and
+ initialize them.
+ (rs6000_density_test): Replace with...
+ (rs6000_cost_data::density_test): ...this.
+ (rs6000_init_cost): Replace with...
+ (rs6000_vectorize_create_costs): ...this.
+ (rs6000_update_target_cost_per_stmt): Replace with...
+ (rs6000_cost_data::update_target_cost_per_stmt): ...this.
+ (rs6000_add_stmt_cost): Replace with...
+ (rs6000_cost_data::add_stmt_cost): ...this. Use adjust_cost_for_freq
+ to adjust the cost for inner loops.
+ (rs6000_adjust_vect_cost_per_loop): Replace with...
+ (rs6000_cost_data::adjust_vect_cost_per_loop): ...this.
+ (rs6000_finish_cost): Replace with...
+ (rs6000_cost_data::finish_cost): ...this. Group loop code
+ into a single if statement and pass the loop_vinfo down to
+ subroutines.
+ (rs6000_destroy_cost_data): Delete.
+
+2021-11-04 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/103062
+ PR tree-optimization/103062
+ * value-pointer-equiv.cc (ssa_equiv_stack::ssa_equiv_stack):
+ Increase size of allocation by 1.
+ (ssa_equiv_stack::push_replacement): Grow as needed.
+ (ssa_equiv_stack::get_replacement): Same.
+ (pointer_equiv_analyzer::pointer_equiv_analyzer): Same.
+ (pointer_equiv_analyzer::~pointer_equiv_analyzer): Remove delete.
+ (pointer_equiv_analyzer::set_global_equiv): Grow as needed.
+ (pointer_equiv_analyzer::get_equiv): Same.
+ (pointer_equiv_analyzer::get_equiv_expr): Remove const.
+ * value-pointer-equiv.h (class pointer_equiv_analyzer): Remove
+ const markers. Use auto_vec instead of tree *.
+
+2021-11-04 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-sccvn.c (vn_nary_op_insert_into): Remove always
+ true parameter and inline valueization.
+ (vn_nary_op_lookup_1): Inline valueization from ...
+ (vn_nary_op_compute_hash): ... here and remove it here.
+ * tree-ssa-pre.c (phi_translate_1): Do not valueize
+ before vn_nary_lookup_pieces.
+ (get_representative_for): Mark created SSA representatives
+ as visited.
+
+2021-11-04 Richard Sandiford <richard.sandiford@arm.com>
+
+ * simplify-rtx.c (simplify_context::simplify_gen_vec_select): Assert
+ that the operand has a vector mode. Use subreg_lowpart_offset
+ to test whether an index corresponds to the low part.
+
+2021-11-04 Richard Sandiford <richard.sandiford@arm.com>
+
+ * read-rtl.c: Remove dead !GENERATOR_FILE block.
+ * read-rtl-function.c (function_reader::consolidate_singletons):
+ Generate canonical CONST_VECTORs.
+
+2021-11-04 liuhongt <hongtao.liu@intel.com>
+
+ PR target/101989
+ * config/i386/predicates.md (reg_or_notreg_operand): Rename to ..
+ (regmem_or_bitnot_regmem_operand): .. and extend to handle
+ memory_operand.
+ * config/i386/sse.md (*<avx512>_vpternlog<mode>_1): Force_reg
+ the operands which are required to be register_operand.
+ (*<avx512>_vpternlog<mode>_2): Ditto.
+ (*<avx512>_vpternlog<mode>_3): Ditto.
+ (*<avx512>_vternlog<mode>_all): Disallow embeded broadcast for
+ vector HFmodes since it's not a real AVX512FP16 instruction.
+
+2021-11-04 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102464
+ * match.pd: simplify (trunc)copysign((extend)a, (extend)b) to
+ .COPYSIGN (a,b) when a and b are same type as the truncation
+ type and has less precision than extend type.
+
+2021-11-04 Richard Biener <rguenther@suse.de>
+
+ * doc/generic.texi: Update TARGET_MEM_REF and MEM_REF
+ documentation.
+
+2021-11-04 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/sse.md (VI2_AVX512VNNIBW): New mode iterator.
+ (VI1_AVX512VNNI): Likewise.
+ (SDOT_VPDP_SUF): New mode_attr.
+ (VI1SI): Likewise.
+ (vi1si): Likewise.
+ (sdot_prod<mode>): Use VI2_AVX512F iterator, expand to
+ vpdpwssd when VNNI targets available.
+ (usdot_prod<mode>): New expander for vector QImode.
+
+2021-11-04 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/amxtileintrin.h (_tile_loadd_internal): Add
+ parentheses to base and stride.
+ (_tile_stream_loadd_internal): Likewise.
+ (_tile_stored_internal): Likewise.
+
+2021-11-03 Maciej W. Rozycki <macro@embecosm.com>
+
+ * config/riscv/riscv.c (riscv_class_max_nregs): Swap the
+ arguments to `reg_class_subset_p'.
+
+2021-11-03 Joseph Myers <joseph@codesourcery.com>
+
+ PR c/103031
+ * fold-const.c (fold_init): New function.
+ * fold-const.h (fold_init): New prototype.
+
+2021-11-03 Andrew MacLeod <amacleod@redhat.com>
+
+ * params.opt (param_vrp2_mode): Make ranger the default for VRP2.
+
+2021-11-03 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-fold.cc (fold_using_range::range_of_phi): Don't import
+ a range from edge if arg == phidef.
+
+2021-11-03 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-fold.cc (fold_using_range::range_of_builtin_call): Test
+ for constant before any other processing.
+
+2021-11-03 Andrew MacLeod <amacleod@redhat.com>
+
+ * flag-types.h (RANGER_DEBUG_ALL): Fix values.
+
+2021-11-03 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range.cc (gimple_ranger::gimple_ranger): Initialize current_bb.
+ (gimple_ranger::range_of_expr): Pick up range_on_entry when there is
+ no explcit context and current_bb is set.
+ (gimple_ranger::fold_stmt): New.
+ * gimple-range.h (current_bb, fold_stmt): New.
+ * tree-vrp.c (rvrp_folder::fold_stmt): Call ranger's fold_stmt.
+
+2021-11-03 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102970
+ * tree-ssa-pre.c (phi_translate_1): Drop clique and base
+ when translating a MEM_REF over a backedge.
+
+2021-11-03 Philipp Tomsich <philipp.tomsich@vrull.eu>
+
+ * config/aarch64/aarch64-cores.def (AARCH64_CORE): New Ampere-1 core.
+ * config/aarch64/aarch64-tune.md: Regenerate.
+ * config/aarch64/aarch64-cost-tables.h: Add extra costs for Ampere-1.
+ * config/aarch64/aarch64.c: Add tuning structures for Ampere-1.
+ * doc/invoke.texi: Add documentation for Ampere-1 core.
+
+2021-11-03 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/aarch64/aarch64.md (movsi): Add alternative for GOT accesses.
+ (movdi): Likewise.
+ (ldr_got_small_<mode>): Remove pattern.
+ (ldr_got_small_sidi): Likewise.
+ * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Keep
+ GOT accesses as moves.
+ (aarch64_print_operand): Correctly print got_lo12 in L specifier.
+ (aarch64_mov_operand_p): Make GOT accesses valid move operands.
+ * config/aarch64/constraints.md: Add new constraint Usw for GOT access.
+
+2021-11-03 Martin Liska <mliska@suse.cz>
+
+ * gcov.c (read_line): Remove dead variable.
+
+2021-11-03 Martin Liska <mliska@suse.cz>
+
+ PR bootstrap/102828
+ * ipa-fnsummary.c (edge_predicate_pool): Rename predicate class to ipa_predicate.
+ (ipa_fn_summary::account_size_time): Likewise.
+ (edge_set_predicate): Likewise.
+ (set_hint_predicate): Likewise.
+ (add_freqcounting_predicate): Likewise.
+ (evaluate_conditions_for_known_args): Likewise.
+ (evaluate_properties_for_edge): Likewise.
+ (remap_freqcounting_preds_after_dup): Likewise.
+ (ipa_fn_summary_t::duplicate): Likewise.
+ (set_cond_stmt_execution_predicate): Likewise.
+ (set_switch_stmt_execution_predicate): Likewise.
+ (compute_bb_predicates): Likewise.
+ (will_be_nonconstant_expr_predicate): Likewise.
+ (will_be_nonconstant_predicate): Likewise.
+ (phi_result_unknown_predicate): Likewise.
+ (predicate_for_phi_result): Likewise.
+ (analyze_function_body): Likewise.
+ (compute_fn_summary): Likewise.
+ (summarize_calls_size_and_time): Likewise.
+ (estimate_calls_size_and_time): Likewise.
+ (ipa_call_context::estimate_size_and_time): Likewise.
+ (remap_edge_summaries): Likewise.
+ (remap_freqcounting_predicate): Likewise.
+ (ipa_merge_fn_summary_after_inlining): Likewise.
+ (ipa_update_overall_fn_summary): Likewise.
+ (read_ipa_call_summary): Likewise.
+ (inline_read_section): Likewise.
+ * ipa-fnsummary.h (struct ipa_freqcounting_predicate): Likewise.
+ * ipa-predicate.c (predicate::add_clause): Likewise.
+ (ipa_predicate::add_clause): Likewise.
+ (predicate::or_with): Likewise.
+ (ipa_predicate::or_with): Likewise.
+ (predicate::evaluate): Likewise.
+ (ipa_predicate::evaluate): Likewise.
+ (predicate::probability): Likewise.
+ (ipa_predicate::probability): Likewise.
+ (dump_condition): Likewise.
+ (dump_clause): Likewise.
+ (predicate::dump): Likewise.
+ (ipa_predicate::dump): Likewise.
+ (predicate::debug): Likewise.
+ (ipa_predicate::debug): Likewise.
+ (predicate::remap_after_duplication): Likewise.
+ (ipa_predicate::remap_after_duplication): Likewise.
+ (predicate::remap_after_inlining): Likewise.
+ (ipa_predicate::remap_after_inlining): Likewise.
+ (predicate::stream_in): Likewise.
+ (ipa_predicate::stream_in): Likewise.
+ (predicate::stream_out): Likewise.
+ (ipa_predicate::stream_out): Likewise.
+ (add_condition): Likewise.
+ * ipa-predicate.h (class predicate): Likewise.
+ (class ipa_predicate): Likewise.
+ (add_condition): Likewise.
+
+2021-11-03 Richard Biener <rguenther@suse.de>
+
+ * bitmap.h (bitmap_bit_p): Change the return type to bool.
+ * bitmap.c (bitmap_bit_p): Likewise.
+ * sbitmap.h (bitmap_bit_p): Likewise.
+ (bitmap_set_bit): Return whether the bit changed.
+ (bitmap_clear_bit): Likewise.
+ * tree-ssa.c (verify_vssa): Make use of the changed state
+ from bitmap_set_bit.
+
+2021-11-03 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/103033
+ * internal-fn.c (expand_DEFERRED_INIT): Elide the
+ native_interpret_expr path in favor of folding the
+ VIEW_CONVERT_EXPR generated when punning the RHS.
+
+2021-11-03 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * config/s390/s390.c (s390_loop_unroll_adjust): In case of early
+ exit free bbs.
+
+2021-11-03 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103040
+ * ipa-modref.c (callee_to_caller_flags): New function.
+ (modref_eaf_analysis::analyze_ssa_name): Use it.
+ (ipa_merge_modref_summary_after_inlining): Fix whitespace.
+
+2021-11-02 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c (modref_eaf_analysis::analyze_ssa_name): Revert
+ accidental commit.
+
+2021-11-02 Roger Sayle <roger@nextmovesoftware.com>
+ Uroš Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (<any_rotate>ti3): Provide expansion for
+ rotations by non-constant amounts.
+
+2021-11-02 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.c: Fix anonymous namespace placement.
+ (class modref_eaf_analysis): New class.
+ (analyze_ssa_name_flags): Turn to ...
+ (modref_eaf_analysis::analyze_ssa_name): ... this one.
+ (merge_call_lhs_flags): Turn to ...
+ (modref_eaf_analysis::merge_call_lhs_flags): .. this one
+ (modref_eaf_analysis::merge_with_ssa_name): New member function.
+ (record_escape_points): Turn to ...
+ (modref_eaf_analysis::record_escape_points): ... this one.
+ (analyze_parms): Updat
+ (ipa_merge_modref_summary_after_inlining): Move to the end of file.
+
+2021-11-02 Jan Hubicka <hubicka@ucw.cz>
+
+ * gimple.c (gimple_call_static_chain_flags): New function.
+ * gimple.h (gimple_call_static_chain_flags): Declare
+ * ipa-modref.c (modref_summary::modref_summary): Initialize
+ static_chain_flags.
+ (modref_summary_lto::modref_summary_lto): Likewise.
+ (modref_summary::useful_p): Test static_chain_flags.
+ (modref_summary_lto::useful_p): Likewise.
+ (struct modref_summary_lto): Add static_chain_flags.
+ (modref_summary::dump): Dump static_chain_flags.
+ (modref_summary_lto::dump): Likewise.
+ (struct escape_point): Add static_cahin_arg.
+ (analyze_ssa_name_flags): Use gimple_call_static_chain_flags.
+ (analyze_parms): Handle static chains.
+ (modref_summaries::duplicate): Duplicate static_chain_flags.
+ (modref_summaries_lto::duplicate): Likewise.
+ (modref_write): Stream static_chain_flags.
+ (read_section): Likewise.
+ (modref_merge_call_site_flags): Handle static_chain_flags.
+ * ipa-modref.h (struct modref_summary): Add static_chain_flags.
+ * tree-ssa-structalias.c (handle_rhs_call): Use
+ gimple_static_chain_flags.
+
+2021-11-02 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103029
+ * tree-vect-loop-manip.c (vect_loop_versioning): Ensure
+ the PHI nodes in the loop maintain their original operand
+ order.
+
+2021-11-02 Jan Hubicka <hubicka@ucw.cz>
+
+ * tree-core.h (EAF_NOT_RETURNED_DIRECTLY): New flag.
+ (EAF_NOREAD): Renumber.
+ * ipa-modref.c (dump_eaf_flags): Dump EAF_NOT_RETURNED_DIRECTLY.
+ (remove_useless_eaf_flags): Handle EAF_NOT_RETURNED_DIRECTLY
+ (deref_flags): Likewise.
+ (modref_lattice::init): Likewise.
+ (modref_lattice::merge): Likewise.
+ (merge_call_lhs_flags): Likewise.
+ (analyze_ssa_name_flags): Likewise.
+ (modref_merge_call_site_flags): Likewise.
+ * tree-ssa-structalias.c (handle_call_arg): Likewise.
+
+2021-11-02 Maciej W. Rozycki <macro@embecosm.com>
+
+ * config/riscv/riscv.c (riscv_rtx_costs): Correct a CONST_INT_P
+ check and remove an unused local variable with shNadd/shNadd.uw
+ pattern handling.
+
+2021-11-02 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/103007
+ * tree-vect-slp-patterns.c (complex_fms_pattern::matches): Add elem
+ check.
+
+2021-11-02 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/103038
+ * fold-const.c (native_interpret_expr): Handle OFFSET_TYPE.
+ (can_native_interpret_type_p): Likewise.
+ * internal-fn.c (expand_DEFERRED_INIT): View-convert the
+ RHS if the LHS is an SSA name.
+
+2021-11-02 Richard Sandiford <richard.sandiford@arm.com>
+
+ * langhooks.h (lang_hooks_for_types::simulate_record_decl): New hook.
+ * langhooks-def.h (lhd_simulate_record_decl): Declare.
+ (LANG_HOOKS_SIMULATE_RECORD_DECL): Define.
+ (LANG_HOOKS_FOR_TYPES_INITIALIZER): Include it.
+ * langhooks.c (lhd_simulate_record_decl): New function.
+
+2021-11-02 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/103020
+ * config/i386/i386.c (ix86_vector_mode_supported_p): Reject vector
+ modes with TImode inner mode if 32-bit.
+
+2021-11-02 liuhongt <hongtao.liu@intel.com>
+
+ * doc/sourcebuild.texi (vect_slp_v4qi_store_unalign,
+ vect_slp_v2hi_store_unalign, vect_slp_v4hi_store_unalign,
+ vect_slp_v4si_store_unalign): Document efficient target.
+ (vect_slp_v4qi_store_unalign_1, vect_slp_v8qi_store_unalign_1,
+ vect_slp_v16qi_store_unalign_1): Ditto.
+ (vect_slp_v2hi_store_align,vect_slp_v2qi_store_align,
+ vect_slp_v2si_store_align, vect_slp_v4qi_store_align): Ditto.
+ (struct_4char_block_move, struct_8char_block_move,
+ struct_16char_block_move): Ditto.
+
+2021-11-02 Roger Sayle <roger@nextmovesoftware.com>
+ Jakub Jelinek <jakub@redhat.com>
+
+ PR target/102986
+ * config/i386/i386-expand.c (ix86_expand_v1ti_to_ti,
+ ix86_expand_ti_to_v1ti): New helper functions.
+ (ix86_expand_v1ti_shift): Check if the amount operand is an
+ integer constant, and expand as a TImode shift if it isn't.
+ (ix86_expand_v1ti_rotate): Check if the amount operand is an
+ integer constant, and expand as a TImode rotate if it isn't.
+ (ix86_expand_v1ti_ashiftrt): New function to expand arithmetic
+ right shifts of V1TImode quantities.
+ * config/i386/i386-protos.h (ix86_expand_v1ti_ashift): Prototype.
+ * config/i386/sse.md (ashlv1ti3, lshrv1ti3): Change constraints
+ to QImode general_operand, and let the helper functions lower
+ shifts by non-constant operands, as TImode shifts. Make
+ conditional on TARGET_64BIT.
+ (ashrv1ti3): New expander calling ix86_expand_v1ti_ashiftrt.
+ (rotlv1ti3, rotrv1ti3): Change shift operand to QImode.
+ Make conditional on TARGET_64BIT.
+
+2021-11-02 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * config/s390/s390.md ("*cc_to_int", "tabort", "*tabort_1",
+ "*tabort_1_plus"): Remove operands non-null check.
+
+2021-11-01 Martin Liska <mliska@suse.cz>
+
+ * opt-functions.awk: Add new sanity checking.
+ * optc-gen.awk: Add new argument to integer_range_info.
+ * params.opt: Update 2 params which have negative IntegerRange.
+
+2021-11-01 qing zhao <qing.zhao@oracle.com>
+
+ * gimplify.c (gimplify_decl_expr): Do not add call to
+ __builtin_clear_padding when a variable is a gimple register
+ or it might not have padding.
+ (gimplify_init_constructor): Likewise.
+
+2021-11-01 Tamar Christina <tamar.christina@arm.com>
+
+ * config/arm/aarch-common-protos.h (struct vector_cost_table): Add
+ movi, dup and extract costing fields.
+ * config/aarch64/aarch64-cost-tables.h (qdf24xx_extra_costs,
+ thunderx_extra_costs, thunderx2t99_extra_costs,
+ thunderx3t110_extra_costs, tsv110_extra_costs, a64fx_extra_costs): Use
+ them.
+ * config/arm/aarch-cost-tables.h (generic_extra_costs,
+ cortexa53_extra_costs, cortexa57_extra_costs, cortexa76_extra_costs,
+ exynosm1_extra_costs, xgene1_extra_costs): Likewise
+ * config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>): Add r->w dup.
+ * config/aarch64/aarch64.c (aarch64_rtx_costs): Add extra costs.
+
+2021-11-01 Tamar Christina <tamar.christina@arm.com>
+
+ * cse.c (add_to_set): New.
+ (find_sets_in_insn): Register constants in sets.
+ (canonicalize_insn): Use auto_vec instead.
+ (cse_insn): Try materializing using vec_dup.
+ * rtl.h (simplify_context::simplify_gen_vec_select,
+ simplify_gen_vec_select): New.
+ * simplify-rtx.c (simplify_context::simplify_gen_vec_select): New.
+
+2021-11-01 David Malcolm <dmalcolm@redhat.com>
+
+ * common.opt (fdiagnostics-escape-format=): New.
+ (diagnostics_escape_format): New enum.
+ (DIAGNOSTICS_ESCAPE_FORMAT_UNICODE): New enum value.
+ (DIAGNOSTICS_ESCAPE_FORMAT_BYTES): Likewise.
+ * diagnostic-format-json.cc (json_end_diagnostic): Add
+ "escape-source" attribute.
+ * diagnostic-show-locus.c
+ (exploc_with_display_col::exploc_with_display_col): Replace
+ "tabstop" param with a cpp_char_column_policy and add an "aspect"
+ param. Use these to compute m_display_col accordingly.
+ (struct char_display_policy): New struct.
+ (layout::m_policy): New field.
+ (layout::m_escape_on_output): New field.
+ (def_policy): New function.
+ (make_range): Update for changes to exploc_with_display_col ctor.
+ (default_print_decoded_ch): New.
+ (width_per_escaped_byte): New.
+ (escape_as_bytes_width): New.
+ (escape_as_bytes_print): New.
+ (escape_as_unicode_width): New.
+ (escape_as_unicode_print): New.
+ (make_policy): New.
+ (layout::layout): Initialize new fields. Update m_exploc ctor
+ call for above change to ctor.
+ (layout::maybe_add_location_range): Update for changes to
+ exploc_with_display_col ctor.
+ (layout::calculate_x_offset_display): Update for change to
+ cpp_display_width.
+ (layout::print_source_line): Pass policy
+ to cpp_display_width_computation. Capture cpp_decoded_char when
+ calling process_next_codepoint. Move printing of source code to
+ m_policy.m_print_cb.
+ (line_label::line_label): Pass in policy rather than context.
+ (layout::print_any_labels): Update for change to line_label ctor.
+ (get_affected_range): Pass in policy rather than context, updating
+ calls to location_compute_display_column accordingly.
+ (get_printed_columns): Likewise, also for cpp_display_width.
+ (correction::correction): Pass in policy rather than tabstop.
+ (correction::compute_display_cols): Pass m_policy rather than
+ m_tabstop to cpp_display_width.
+ (correction::m_tabstop): Replace with...
+ (correction::m_policy): ...this.
+ (line_corrections::line_corrections): Pass in policy rather than
+ context.
+ (line_corrections::m_context): Replace with...
+ (line_corrections::m_policy): ...this.
+ (line_corrections::add_hint): Update to use m_policy rather than
+ m_context.
+ (line_corrections::add_hint): Likewise.
+ (layout::print_trailing_fixits): Likewise.
+ (selftest::test_display_widths): New.
+ (selftest::test_layout_x_offset_display_utf8): Update to use
+ policy rather than tabstop.
+ (selftest::test_one_liner_labels_utf8): Add test of escaping
+ source lines.
+ (selftest::test_diagnostic_show_locus_one_liner_utf8): Update to
+ use policy rather than tabstop.
+ (selftest::test_overlapped_fixit_printing): Likewise.
+ (selftest::test_overlapped_fixit_printing_utf8): Likewise.
+ (selftest::test_overlapped_fixit_printing_2): Likewise.
+ (selftest::test_tab_expansion): Likewise.
+ (selftest::test_escaping_bytes_1): New.
+ (selftest::test_escaping_bytes_2): New.
+ (selftest::diagnostic_show_locus_c_tests): Call the new tests.
+ * diagnostic.c (diagnostic_initialize): Initialize
+ context->escape_format.
+ (convert_column_unit): Update to use default character width policy.
+ (selftest::test_diagnostic_get_location_text): Likewise.
+ * diagnostic.h (enum diagnostics_escape_format): New enum.
+ (diagnostic_context::escape_format): New field.
+ * doc/invoke.texi (-fdiagnostics-escape-format=): New option.
+ (-fdiagnostics-format=): Add "escape-source" attribute to examples
+ of JSON output, and document it.
+ * input.c (location_compute_display_column): Pass in "policy"
+ rather than "tabstop", passing to
+ cpp_byte_column_to_display_column.
+ (selftest::test_cpp_utf8): Update to use cpp_char_column_policy.
+ * input.h (class cpp_char_column_policy): New forward decl.
+ (location_compute_display_column): Pass in "policy" rather than
+ "tabstop".
+ * opts.c (common_handle_option): Handle
+ OPT_fdiagnostics_escape_format_.
+ * selftest.c (temp_source_file::temp_source_file): New ctor
+ overload taking a size_t.
+ * selftest.h (temp_source_file::temp_source_file): Likewise.
+
+2021-11-01 Aldy Hernandez <aldyh@redhat.com>
+
+ * dbgcnt.def: Add debug counter for back_thread[12] and
+ back_threadfull[12].
+ * passes.def: Pass "first" argument to each back threading pass.
+ * tree-ssa-threadbackward.c (back_threader::back_threader): Add
+ first argument.
+ (back_threader::debug_counter): New.
+ (back_threader::maybe_register_path): Call debug_counter.
+
+2021-11-01 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (BT_NONE): New.
+ (BT_SPEED): New.
+ (BT_RESOLVE): New.
+ (back_threader::back_threader): Add flags.
+ Move loop initialization here.
+ (back_threader::~back_threader): New.
+ (back_threader::find_taken_edge_switch): Change solver and ranger
+ to pointers.
+ (back_threader::find_taken_edge_cond): Same.
+ (back_threader::find_paths_to_names): Same.
+ (back_threader::find_paths): Same.
+ (back_threader::dump): Same.
+ (try_thread_blocks): Merge into thread_blocks.
+ (back_threader::thread_blocks): New.
+ (do_early_thread_jumps): Merge into thread_blocks.
+ (do_thread_jumps): Merge into thread_blocks.
+ (back_threader::thread_through_all_blocks): Remove.
+
+2021-11-01 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/103003
+ * value-relation.cc (dom_oracle::register_relation): If the 2
+ ssa names are the same, don't register any relation.
+
+2021-11-01 Dan Li <ashimida@linux.alibaba.com>
+
+ * config/aarch64/aarch64.c (aarch64_expand_epilogue): Remove
+ redundant check for calls_eh_return.
+ * config/aarch64/aarch64.md (*do_return): Likewise.
+
+2021-11-01 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ * cfghooks.c (cfg_hook_duplicate_loop_to_header_edge): Rename
+ duplicate_loop_to_header_edge to
+ duplicate_loop_body_to_header_edge.
+ (cfg_hook_duplicate_loop_body_to_header_edge): Likewise.
+ * cfghooks.h (struct cfg_hooks): Likewise.
+ (cfg_hook_duplicate_loop_body_to_header_edge): Likewise.
+ * cfgloopmanip.c (duplicate_loop_body_to_header_edge): Likewise.
+ (clone_loop_to_header_edge): Likewise.
+ * cfgloopmanip.h (duplicate_loop_body_to_header_edge): Likewise.
+ * cfgrtl.c (struct cfg_hooks): Likewise.
+ * doc/loop.texi: Likewise.
+ * loop-unroll.c (unroll_loop_constant_iterations): Likewise.
+ (unroll_loop_runtime_iterations): Likewise.
+ (unroll_loop_stupid): Likewise.
+ (apply_opt_in_copies): Likewise.
+ * tree-cfg.c (struct cfg_hooks): Likewise.
+ * tree-ssa-loop-ivcanon.c (try_unroll_loop_completely): Likewise.
+ (try_peel_loop): Likewise.
+ * tree-ssa-loop-manip.c (copy_phi_node_args): Likewise.
+ (gimple_duplicate_loop_body_to_header_edge): Likewise.
+ (tree_transform_and_unroll_loop): Likewise.
+ * tree-ssa-loop-manip.h (gimple_duplicate_loop_body_to_header_edge):
+ Likewise.
+
+2021-11-01 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ * cfgloopmanip.c (loop_version): Refactor loopify to
+ loop_version. Move condition generation after loopify.
+ (loopify): Delete.
+ * cfgloopmanip.h (loopify): Delete.
+
+2021-10-31 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-fnsummary.c: Include tree-dfa.h.
+ (points_to_local_or_readonly_memory_p): Return true on return
+ slot writes.
+ * ipa-modref.c (analyze_ssa_name_flags): Fix handling of copy
+ statement.
+
+2021-10-30 Tobias Burnus <tobias@codesourcery.com>
+
+ PR middle-end/102972
+ * omp-low.c (omp_runtime_api_call): Use DECL_ASSEMBLER_NAME to get
+ internal Fortran name; new permit_num_teams arg to permit
+ omp_get_num_teams and omp_get_team_num.
+ (scan_omp_1_stmt): Update call to it, add missing call for
+ reverse offload, and check for strictly nested API calls in teams.
+
+2021-10-30 Jakub Jelinek <jakub@redhat.com>
+
+ * gimplify.c (gimplify_omp_for): Diagnose threadprivate iterators.
+
+2021-10-29 David Malcolm <dmalcolm@redhat.com>
+
+ * selftest.c (assert_streq): Add newlines when emitting non-equal
+ non-NULL strings.
+
+2021-10-29 David Malcolm <dmalcolm@redhat.com>
+
+ * Makefile.in: Fix syntax for reference to LIBDEPS in
+ gengtype link rule.
+
+2021-10-29 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
+
+ * doc/install.texi: Bump required minimum DejaGnu version.
+
+2021-10-29 Aldy Hernandez <aldyh@redhat.com>
+ Andrew MacLeod <amacleod@redhat.com>
+
+ * value-relation.cc (path_oracle::killing_def): Add a
+ self-equivalence so we don't look to the root oracle.
+
+2021-10-29 Aldy Hernandez <aldyh@redhat.com>
+
+ * passes.def: Replace the pass_thread_jumps before VRP* with
+ pass_thread_jumps_full. Remove all pass_vrp_threader instances.
+ * tree-ssa-threadbackward.c (pass_data_thread_jumps_full):
+ Remove hyphen from "thread-full" name.
+
+2021-10-29 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/102983
+ * gimple-range-cache.h (propagate_updated_value): Make public.
+ * gimple-range.cc (gimple_ranger::range_of_stmt): Propagate exports
+ when processing gcond stmts.
+
+2021-10-29 Jan Hubicka <hubicka@ucw.cz>
+
+ * gimple.c (gimple_call_retslot_flags): New function.
+ * gimple.h (gimple_call_retslot_flags): Declare.
+ * ipa-modref.c: Include tree-cfg.h.
+ (struct escape_entry): Turn parm_index to signed.
+ (modref_summary_lto::modref_summary_lto): Add retslot_flags.
+ (modref_summary::modref_summary): Initialize retslot_flags.
+ (struct modref_summary_lto): Likewise.
+ (modref_summary::useful_p): Check retslot_flags.
+ (modref_summary_lto::useful_p): Likewise.
+ (modref_summary::dump): Dump retslot_flags.
+ (modref_summary_lto::dump): Likewise.
+ (struct escape_point): Add hidden_args enum.
+ (analyze_ssa_name_flags): Ignore return slot return;
+ use gimple_call_retslot_flags.
+ (record_escape_points): Break out from ...
+ (analyze_parms): ... here; handle retslot_flags.
+ (modref_summaries::duplicate): Duplicate retslot_flags.
+ (modref_summaries_lto::duplicate): Likewise.
+ (modref_write_escape_summary): Stream parm_index as signed.
+ (modref_read_escape_summary): Likewise.
+ (modref_write): Stream retslot_flags.
+ (read_section): Likewise.
+ (struct escape_map): Fix typo in comment.
+ (update_escape_summary_1): Fix whitespace.
+ (ipa_merge_modref_summary_after_inlining): Drop retslot_flags.
+ (modref_merge_call_site_flags): Merge retslot_flags.
+ * ipa-modref.h (struct modref_summary): Add retslot_flags.
+ * tree-ssa-structalias.c (handle_rhs_call): Handle retslot_flags.
+
+2021-10-29 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/102977
+ * tree-vect-slp-patterns.c (vect_match_call_p): Remove.
+ (vect_detect_pair_op): Add crosslane check.
+ (vect_match_call_complex_mla): Remove.
+ (class complex_mul_pattern): Update comment.
+ (complex_mul_pattern::matches): Update detection.
+ (class complex_fma_pattern): Remove.
+ (complex_fma_pattern::matches): Remove.
+ (complex_fma_pattern::recognize): Remove.
+ (complex_fma_pattern::build): Remove.
+ (class complex_fms_pattern): Update comment.
+ (complex_fms_pattern::matches): Remove.
+ (complex_operations_pattern::recognize): Remove complex_fma_pattern
+
+2021-10-29 Jakub Jelinek <jakub@redhat.com>
+
+ * gimple-fold.c (gimple_fold_builtin_memset): Copy over location from
+ call to store.
+
+2021-10-29 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ PR target/102868
+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Add
+ patterns match and emit for VSX xxpermdi.
+
+2021-10-29 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102464
+ * config/i386/i386-builtin-types.def (V8HF_FTYPE_V8HF): New
+ function type.
+ (V16HF_FTYPE_V16HF): Ditto.
+ (V32HF_FTYPE_V32HF): Ditto.
+ (V8HF_FTYPE_V8HF_ROUND): Ditto.
+ (V16HF_FTYPE_V16HF_ROUND): Ditto.
+ (V32HF_FTYPE_V32HF_ROUND): Ditto.
+ * config/i386/i386-builtin.def ( IX86_BUILTIN_FLOORPH,
+ IX86_BUILTIN_CEILPH, IX86_BUILTIN_TRUNCPH,
+ IX86_BUILTIN_FLOORPH256, IX86_BUILTIN_CEILPH256,
+ IX86_BUILTIN_TRUNCPH256, IX86_BUILTIN_FLOORPH512,
+ IX86_BUILTIN_CEILPH512, IX86_BUILTIN_TRUNCPH512): New builtin.
+ * config/i386/i386-builtins.c
+ (ix86_builtin_vectorized_function): Enable vectorization for
+ HFmode FLOOR/CEIL/TRUNC operation.
+ * config/i386/i386-expand.c (ix86_expand_args_builtin): Handle
+ new builtins.
+ * config/i386/sse.md (rint<mode>2, nearbyint<mode>2): Extend
+ to vector HFmodes.
+
+2021-10-28 Aldy Hernandez <aldyh@redhat.com>
+ Andrew MacLeod <amacleod@redhat.com>
+
+ * value-relation.cc (path_oracle::killing_def): Walk the
+ equivalency list and remove SSA from any equivalencies.
+
+2021-10-28 Stafford Horne <shorne@gmail.com>
+
+ * config/or1k/or1k.h (PROFILE_HOOK): Add return address argument
+ to _mcount.
+
+2021-10-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/102951
+ * fold-const.h (address_compare): Declare.
+ * fold-const.c (address_compare): New function.
+ * match.pd (cmp (convert1?@2 addr@0) (convert2? addr@1)): Use
+ address_compare helper.
+ (minmax cmp (convert1?@2 addr@0) (convert2?@3 addr@1)): New
+ simplification.
+
+2021-10-28 Andrew MacLeod <amacleod@redhat.com>
+
+ * vr-values.c (simplify_using_ranges::fold_cond): Change fold message.
+
+2021-10-28 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/102940
+ * tree-vrp.c (execute_ranger_vrp): Reset scev.
+
+2021-10-28 Richard Purdie <richard.purdie@linuxfoundation.org>
+
+ * config/nios2/linux.h (MUSL_DYNAMIC_LINKER): Add musl linker
+
+2021-10-28 Richard Purdie <richard.purdie@linuxfoundation.org>
+
+ * configure: Regenerate.
+ * configure.ac: Use CPPFLAGS_FOR_BUILD for GMPINC
+
+2021-10-28 Eric Botcazou <ebotcazou@adacore.com>
+
+ * doc/invoke.texi (%X): Remove obsolete reference to -Wl.
+
+2021-10-28 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/84407
+ * fold-const.c (fold_convert_const): Avoid int to float
+ constant folding with -frounding-math and inexact result.
+ * simplify-rtx.c (simplify_const_unary_operation): Likewise
+ for both float and unsigned_float.
+
+2021-10-28 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c
+ (back_threader::find_taken_edge_switch): Use find_case_label_range
+ instead of find_taken_edge.
+
+2021-10-28 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (class back_threader_registry):
+ Inherit from back_jt_path_registry.
+ (back_threader_registry::thread_through_all_blocks): Remove.
+ (back_threader_registry::register_path): Remove
+ m_lowlevel_registry prefix.
+
+2021-10-28 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/57245
+ * fold-const.c (fold_convert_const_real_from_real): Honor
+ -frounding-math if the conversion is not exact.
+ * simplify-rtx.c (simplify_const_unary_operation): Do not
+ simplify FLOAT_TRUNCATE with sign dependent rounding.
+
+2021-10-28 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102949
+ * tree-vect-stmts.c (ensure_base_align): Look at the
+ dr_info of a group leader and assert we are looking at
+ one with analyzed alignment.
+
+2021-10-28 Kewen Lin <linkw@linux.ibm.com>
+
+ PR target/102767
+ * config/rs6000/rs6000.c (rs6000_builtin_vectorization_cost): Consider
+ V1T1 mode for unaligned load and store.
+
+2021-10-28 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/riscv.md (zero_extendsidi2_internal): Allow ZBB
+ use this pattern.
+
+2021-10-28 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/arch-canonicalize (CANONICAL_ORDER): Add `i` to
+ CANONICAL_ORDER.
+
+2021-10-28 Alexandre Oliva <oliva@adacore.com>
+
+ * common.opt (fharden-compares): New.
+ (fharden-conditional-branches): New.
+ * doc/invoke.texi: Document new options.
+ * gimple-harden-conditionals.cc: New.
+ * Makefile.in (OBJS): Build it.
+ * passes.def: Add new passes.
+ * tree-pass.h (make_pass_harden_compares): Declare.
+ (make_pass_harden_conditional_branches): Declare.
+
+2021-10-28 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ PR target/94613
+ * config/rs6000/altivec.md: Add vsx register constraints.
+ * config/rs6000/vsx.md (vsx_xxsel<mode>): Delete.
+ (vsx_xxsel<mode>2): Likewise.
+ (vsx_xxsel<mode>3): Likewise.
+ (vsx_xxsel<mode>4): Likewise.
+
+2021-10-28 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ PR target/94613
+ * config/rs6000/altivec.md (*altivec_vsel<mode>): Change to ...
+ (altivec_vsel<mode>): ... this and update define.
+ (*altivec_vsel<mode>_uns): Delete.
+ (altivec_vsel<mode>2): New define_insn.
+ (altivec_vsel<mode>3): Likewise.
+ (altivec_vsel<mode>4): Likewise.
+ * config/rs6000/rs6000-call.c (altivec_expand_vec_sel_builtin): New.
+ (altivec_expand_builtin): Call altivec_expand_vec_sel_builtin to expand
+ vel_sel.
+ * config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Use bit-wise
+ selection instead of per element.
+ * config/rs6000/vector.md:
+ * config/rs6000/vsx.md (*vsx_xxsel<mode>): Change to ...
+ (vsx_xxsel<mode>): ... this and update define.
+ (*vsx_xxsel<mode>_uns): Delete.
+ (vsx_xxsel<mode>2): New define_insn.
+ (vsx_xxsel<mode>3): Likewise.
+ (vsx_xxsel<mode>4): Likewise.
+
+2021-10-28 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/i386.c (use_rsqrt_p): Add mode parameter, enable
+ HFmode rsqrt without TARGET_SSE_MATH.
+ (ix86_optab_supported_p): Refactor rint, adjust floor, ceil,
+ btrunc condition to be restricted by -ftrapping-math, adjust
+ use_rsqrt_p function call.
+ * config/i386/i386.md (rcphf2): New define_insn.
+ (rsqrthf2): Likewise.
+ * config/i386/sse.md (div<mode>3): Change VF2H to VF2.
+ (div<mode>3): New expander for HF mode.
+ (rsqrt<mode>2): Likewise.
+ (*avx512fp16_vmrcpv8hf2): New define_insn for rpad pass.
+ (*avx512fp16_vmrsqrtv8hf2): Likewise.
+
+2021-10-27 Saagar Jha <saagar@saagarjha.com>
+
+ * config.gcc: Adjust for Darwin21.
+ * config/darwin-c.c (macosx_version_as_macro): Likewise.
+ * config/darwin-driver.c (validate_macosx_version_min):
+ Likewise.
+ (darwin_find_version_from_kernel): Likewise.
+
+2021-10-27 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc
+ (path_range_query::range_defined_in_block): Call killing_def.
+
+2021-10-27 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-fold.cc (fold_using_range::range_of_range_op): Dump
+ operands as well as relation.
+ * gimple-range-path.cc
+ (path_range_query::compute_ranges_in_block): Compute PHI relations
+ first. Compute outgoing relations at the end.
+ (path_range_query::compute_ranges): Remove call to compute_relations.
+ (path_range_query::compute_relations): Remove.
+ (path_range_query::maybe_register_phi_relation): New.
+ (path_range_query::compute_phi_relations): Abstract out
+ registering one PHI relation to...
+ (path_range_query::compute_outgoing_relations): ...here.
+ * gimple-range-path.h (class path_range_query): Remove
+ compute_relations.
+ Add maybe_register_phi_relation.
+
+2021-10-27 Aldy Hernandez <aldyh@redhat.com>
+ Andrew MacLeod <amacleod@redhat.com>
+
+ * value-relation.cc (path_oracle::killing_def): Kill second
+ order relations.
+
+2021-10-27 Martin Jambor <mjambor@suse.cz>
+
+ * ipa-cp.c (good_cloning_opportunity_p): Decide whether to use
+ profile feedback depending on their local availability.
+
+2021-10-27 Martin Jambor <mjambor@suse.cz>
+
+ * params.opt (param_ipa_cp_profile_count_base): New parameter.
+ * doc/invoke.texi (Optimize Options): Add entry for
+ ipa-cp-profile-count-base.
+ * ipa-cp.c (max_count): Replace with base_count, replace all
+ occurrences too, unless otherwise stated.
+ (ipcp_cloning_candidate_p): identify mostly-directly called
+ functions based on their counts, not max_count.
+ (compare_edge_profile_counts): New function.
+ (ipcp_propagate_stage): Instead of setting max_count, find the
+ appropriate edge count in a sorted vector of counts of eligible
+ edges and make it the base_count.
+
+2021-10-27 Martin Jambor <mjambor@suse.cz>
+
+ * ipa-cp.c (struct caller_statistics): New fields rec_count_sum,
+ n_nonrec_calls and itself, document all fields.
+ (init_caller_stats): Initialize the above new fields.
+ (gather_caller_stats): Gather self-recursive counts and calls number.
+ (get_info_about_necessary_edges): Gather counts of self-recursive and
+ other edges bringing in the requested value separately.
+ (dump_profile_updates): Rework to dump info about a single node only.
+ (lenient_count_portion_handling): New function.
+ (struct gather_other_count_struct): New type.
+ (gather_count_of_non_rec_edges): New function.
+ (struct desc_incoming_count_struct): New type.
+ (analyze_clone_icoming_counts): New function.
+ (adjust_clone_incoming_counts): Likewise.
+ (update_counts_for_self_gen_clones): Likewise.
+ (update_profiling_info): Rewritten.
+ (update_specialized_profile): Adjust call to dump_profile_updates.
+ (create_specialized_node): Do not update profiling info.
+ (decide_about_value): New parameter self_gen_clones, either push new
+ clones into it or updat their profile counts. For self-recursively
+ generated values, use a portion of the node count instead of count
+ from self-recursive edges to estimate goodness.
+ (decide_whether_version_node): Gather clones for self-generated values
+ in a new vector, update their profiles at once at the end.
+
+2021-10-27 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.c (vect_transform_loops): New function,
+ split out from ...
+ (try_vectorize_loop_1): ... here. Simplify as epilogues
+ are now fully handled in the split part.
+
+2021-10-27 Jakub Jelinek <jakub@redhat.com>
+
+ * omp-expand.c (expand_omp_for_init_counts): Handle non-rectangular
+ iterators with pointer types.
+ (expand_omp_for_init_vars, extract_omp_for_update_vars): Likewise.
+
+2021-10-26 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/102238
+ PR tree-optimization/102919
+ * gimple-ssa-sprintf.c (get_string_length): Add an argument.
+ (array_elt_at_offset): Move to pointer-query.
+ (set_aggregate_size_and_offset): New function.
+ (field_at_offset): Move to pointer-query.
+ (get_origin_and_offset): Rename...
+ (get_origin_and_offset_r): this. Add an argument. Make aggregate
+ handling more robust.
+ (get_origin_and_offset): New.
+ (alias_offset): Add an argument.
+ (format_string): Use subobject size determined by get_origin_and_offset.
+ * pointer-query.cc (field_at_offset): Move from gimple-ssa-sprintf.c.
+ Improve/correct handling of aggregates.
+ (array_elt_at_offset): Same.
+ * pointer-query.h (field_at_offset): Declare.
+ (array_elt_at_offset): Declare.
+
+2021-10-26 Martin Sebor <msebor@redhat.com>
+
+ * builtins.c (check_strncat_sizes): Pass access_data ctor additional
+ arguments.
+ (expand_builtin_memcmp): Move code to gimple-ssa-warn-access.cc.
+ (expand_builtin_fork_or_exec): Same.
+ * gimple-array-bounds.cc (array_bounds_checker::check_mem_ref): Pass
+ compute_objsize additional arguments.
+ (inbounds_memaccess_p): Same.
+ (array_bounds_checker::check_array_bounds): Add an assert. Stash
+ statement in a member.
+ (check_array_bounds_dom_walker::before_dom_children): Same.
+ * gimple-array-bounds.h (array_bounds_checker::m_stmt): New member.
+ * gimple-ssa-sprintf.c (get_destination_size): Add an argument.
+ (handle_printf_call): Pass a new argument.
+ * gimple-ssa-warn-access.cc (get_size_range): Add an argument.
+ (check_access): Add an argument and pass it along to callees.
+ (check_read_access): Make a member function.
+ (pass_waccess::check_strcat): Pass access_data ctor additional
+ arguments.
+ (pass_waccess::check_strncat): Same.
+ (pass_waccess::check_stxcpy): Same.
+ (pass_waccess::check_stxncpy): Same.
+ (pass_waccess::check_strncmp): Same.
+ (pass_waccess::check_read_access): Same.
+ (pass_waccess::check_builtin): Same.
+ (pass_waccess::maybe_check_access_sizes): Same.
+ (pass_waccess::maybe_check_dealloc_call): Same.
+ * gimple-ssa-warn-access.h (check_read_access): Declare a new
+ member function.
+ * pointer-query.cc (compute_objsize_r): Add an argument.
+ (gimple_call_return_array): Same.
+ (gimple_call_alloc_size): Same.
+ (access_ref::access_ref): Same.
+ (access_ref::get_ref): Same.
+ (pointer_query::get_ref): Same.
+ (handle_min_max_size): Pass an arguments to callees.
+ (handle_array_ref): Add an argument.
+ (handle_mem_ref): Same.
+ (compute_objsize): Same.
+ * pointer-query.h (struct access_ref): Adjust signatures.
+ (struct access_data): Same.
+ (gimple_call_alloc_size): Add an argument.
+ (gimple_parm_array_size): Same.
+ (compute_objsize): Same.
+ * tree-ssa-strlen.c (strlen_pass::adjust_last_stmt): Pass an additional
+ argument to compute_objsize.
+ (strlen_pass::maybe_warn_overflow): Same.
+ (maybe_diag_stxncpy_trunc): Same.
+
+2021-10-26 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/102453
+ * gimple-ssa-warn-access.cc (pass_waccess::check_atomic_builtin): New.
+ (pass_waccess::check_atomic_builtin): Call it.
+
+2021-10-26 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR rtl-optimization/102842
+ * lra-constraints.c (match_reload): Ignore out in checking values
+ of outs.
+ (curr_insn_transform): Collect outputs before doing reloads of operands.
+
+2021-10-26 Paul A. Clarke <pc@us.ibm.com>
+
+ PR target/102719
+ * config/rs6000/x86intrin.h: Move some included headers to new
+ headers. Include new immintrin.h instead of those headers.
+ * config/rs6000/immintrin.h: New.
+ * config/rs6000/x86gprintrin.h: New.
+ * config.gcc (powerpc*-*-*): Add new headers to extra_headers.
+
+2021-10-26 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (vect_create_addr_base_for_vector_ref):
+ Remove byte_offset parameter.
+ (vect_create_data_ref_ptr): Likewise.
+ * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref):
+ Likewise.
+ (vect_create_data_ref_ptr): Likewise.
+ * tree-vect-stmts.c (vectorizable_store): Adjust.
+ (vectorizable_load): Likewise.
+
+2021-10-26 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/96109
+ * tree-vectorizer.h (dr_misalignment): Add optional offset
+ parameter.
+ * tree-vect-data-refs.c (dr_misalignment): Likewise. Remove
+ offset applied for negative stride accesses.
+ (vect_enhance_data_refs_alignment): Compute negative stride
+ access offset and pass it to dr_misalignment.
+ * tree-vect-stmts.c (get_negative_load_store_type): Pass
+ negative offset to dr_misalignment.
+ (get_group_load_store_type): Likewise.
+ (get_load_store_type): Likewise.
+ (vectorizable_store): Remove asserts about alignment.
+ (vectorizable_load): Likewise.
+
+2021-10-26 Kewen Lin <linkw@linux.ibm.com>
+
+ PR tree-optimization/102897
+ * tree-ssa-forwprop.c (simplify_permutation): Remove a wrong assertion.
+
+2021-10-26 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref):
+ Take offset in bytes.
+ (vect_create_data_ref_ptr): Likewise.
+ * tree-vect-loop-manip.c (get_misalign_in_elems): Multiply
+ offset by element size.
+ (vect_create_cond_for_align_checks): Likewise.
+ * tree-vect-stmts.c (get_negative_load_store_type): Likewise.
+ (vectorizable_load): Remove duplicate leftover from merge
+ conflict.
+
+2021-10-26 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/i386/i386-expand.c (ix86_expand_v1ti_shift): New helper
+ function to expand V1TI mode logical shifts by integer constants.
+ (ix86_expand_v1ti_rotate): New helper function to expand V1TI
+ mode rotations by integer constants.
+ * config/i386/i386-protos.h (ix86_expand_v1ti_shift,
+ ix86_expand_v1ti_rotate): Prototype new functions here.
+ * config/i386/sse.md (ashlv1ti3, lshrv1ti3, rotlv1ti3, rotrv1ti3):
+ New TARGET_SSE2 expanders to implement V1TI shifts and rotations.
+
+2021-10-26 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (back_threader::maybe_register_path):
+ Avoid threading circular paths.
+
+2021-10-26 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (back_threader::resolve_phi):
+ Attempt to resolve all incoming paths to a PHI.
+ (back_threader::resolve_def): Always return true for PHIs.
+
+2021-10-26 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (back_threader::find_paths_to_names):
+ Always try to resolve path without looking back.
+ * tree-ssa-threadupdate.c (dump_jump_thread): Indidicate whether
+ edge is a back edge.
+
+2021-10-26 Kewen Lin <linkw@linux.ibm.com>
+
+ PR tree-optimization/102789
+ * tree-vect-loop-manip.c (vect_update_inits_of_drs): Do not
+ update inits of simd_lane_access.
+
+2021-10-25 Andrew MacLeod <amacleod@redhat.com>
+
+ * tree-vrp.c (vrp_simplify_cond_using_ranges): Add return type and
+ move to vr-values.c.
+ (simplify_casted_conds): Move to vrp_folder class.
+ (execute_vrp): Call via vrp_folder now.
+ * vr-values.c (simplify_cond_using_ranges_1): Call simplify_casted_cond.
+ (simplify_using_ranges::simplify_casted_cond): Relocate from tree-vrp.c.
+ * vr-values.h (simplify_casted_cond): Add prototype.
+
+2021-10-25 Andrew MacLeod <amacleod@redhat.com>
+
+ * tree-vrp.c (rvrp_folder::fold_stmt): If simplification fails, try
+ to fold anyway.
+
+2021-10-25 Paul A. Clarke <pc@us.ibm.com>
+
+ * config/rs6000/smmintrin.h (_mm_testz_si128): Add "extern" to
+ function signature.
+ (_mm_testc_si128): Likewise.
+ (_mm_testnzc_si128): Likewise.
+ (_mm_blend_ps): Likewise.
+ (_mm_blendv_ps): Likewise.
+ (_mm_blend_pd): Likewise.
+ (_mm_blendv_pd): Likewise.
+ (_mm_ceil_pd): Likewise.
+ (_mm_ceil_sd): Likewise.
+ (_mm_ceil_ps): Likewise.
+ (_mm_ceil_ss): Likewise.
+ (_mm_floor_pd): Likewise.
+ (_mm_floor_sd): Likewise.
+ (_mm_floor_ps): Likewise.
+ (_mm_floor_ss): Likewise.
+ (_mm_minpos_epu16): Likewise.
+ (_mm_mul_epi32): Likewise.
+ (_mm_cvtepi8_epi16): Likewise.
+ (_mm_packus_epi32): Likewise.
+ (_mm_cmpgt_epi64): Likewise.
+
+2021-10-25 Roger Sayle <roger@nextmovesoftware.com>
+
+ * simplify-rtx.c (simplify_binary_operation_1) [SS_ASHIFT]: Simplify
+ shifts of the mode's smin_value and smax_value when the bit count
+ operand doesn't have side-effects.
+ [US_ASHIFT]: Likewise, simplify shifts of the mode's umax_value
+ when the bit count operand doesn't have side-effects.
+ (simplify_const_binary_operation) [SS_ASHIFT, US_ASHIFT]: Perform
+ compile-time evaluation of saturating left shifts with constant
+ arguments.
+
+2021-10-25 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range.cc (gimple_ranger::export_global_ranges): Remove check
+ for TDF_DETAILS.
+
+2021-10-25 Andrew MacLeod <amacleod@redhat.com>
+
+ * flag-types.h (enum ranger_debug): Adjust values.
+ * params.opt (ranger_debug): Ditto.
+
+2021-10-25 Martin Jambor <mjambor@suse.cz>
+
+ PR tree-optimization/102886
+ * tree-sra.c (totally_scalarize_subtree): Fix the out of
+ access-condition.
+
+2021-10-25 Andrew Pinski <apinski@marvell.com>
+
+ * tree-ssa-dce.c (simple_dce_from_worklist):
+ Check stmt_unremovable_because_of_non_call_eh_p also
+ before removing the statement.
+
+2021-10-25 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102905
+ * tree-vect-data-refs.c (vect_enhance_data_refs_alignment):
+ Use vect_supportable_dr_alignment again to determine whether
+ an access is supported when not aligned.
+
+2021-10-25 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/riscv.c (riscv_rtx_costs): Handle cost model
+ for zbs extension.
+
+2021-10-25 Jim Wilson <jimw@sifive.com>
+ Kito Cheng <kito.cheng@sifive.com>
+ Jia-Wei Chen <jiawei@iscas.ac.cn>
+ Shi-Hua Liao <shihua@iscas.ac.cn>
+
+ * config/riscv/bitmanip.md (shiftm1): New.
+ (*bset<mode>): Ditto.
+ (*bset<mode>_mask): Ditto.
+ (*bset<mode>_1): Ditto.
+ (*bset<mode>_1_mask): Ditto.
+ (*bseti<mode>): Ditto.
+ (*bclr<mode>): Ditto.
+ (*bclri<mode>): Ditto.
+ (*binv<mode>): Ditto.
+ (*binvi<mode>): Ditto.
+ (*bext<mode>): Ditto.
+ (*bexti): Ditto.
+ * config/riscv/predicates.md (splittable_const_int_operand):
+ Handle bseti.
+ (single_bit_mask_operand): New.
+ (not_single_bit_mask_operand): Ditto.
+ (const31_operand): Ditto.
+ (const63_operand): Ditto.
+ * config/riscv/riscv.c (riscv_build_integer_1): Handle bseti.
+ (riscv_output_move): Ditto.
+ (riscv_print_operand): Handle new operand type: T and S.
+ * config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): New.
+
+2021-10-25 Jim Wilson <jimw@sifive.com>
+
+ * config/riscv/riscv.c (riscv_build_integer_1): Build integer
+ with rotate.
+
+2021-10-25 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/riscv.c (riscv_extend_cost): Handle cost model
+ for zbb extension.
+ (riscv_rtx_costs): Ditto.
+
+2021-10-25 Jim Wilson <jimw@sifive.com>
+ Kito Cheng <kito.cheng@sifive.com>
+ Jia-Wei Chen <jiawei@iscas.ac.cn>
+
+ * config/riscv/bitmanip.md (bitmanip_bitwise): New.
+ (bitmanip_minmax): New.
+ (clz_ctz_pcnt): New.
+ (bitmanip_optab): New.
+ (bitmanip_insn): New.
+ (*<optab>_not<mode>): New.
+ (*xor_not<mode>): New.
+ (<bitmanip_optab>si2): New.
+ (*<bitmanip_optab>disi2): New.
+ (<bitmanip_optab>di2): New.
+ (*zero_extendhi<GPR:mode>2_bitmanip): New.
+ (*extend<SHORT:mode><SUPERQI:mode>2_zbb): New.
+ (*zero_extendhi<GPR:mode>2_zbb): New.
+ (rotrsi3): New.
+ (rotrdi3): New.
+ (rotrsi3_sext): New.
+ (rotlsi3): New.
+ (rotldi3): New.
+ (rotlsi3_sext): New.
+ (bswap<mode>2): New.
+ (<bitmanip_optab><mode>3): New.
+ * config/riscv/riscv.md (type): Add rotate.
+ (zero_extendhi<GPR:mode>2): Change to define_expand pattern.
+ (*zero_extendhi<GPR:mode>2): New.
+ (extend<SHORT:mode><SUPERQI:mode>2): Change to define_expand pattern.
+ (*extend<SHORT:mode><SUPERQI:mode>2): New.
+
+2021-10-25 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/riscv.c (riscv_extend_cost): Handle cost model
+ for zba extension.
+ (riscv_rtx_costs): Ditto.
+
+2021-10-25 Jim Wilson <jimw@sifive.com>
+ Kito Cheng <kito.cheng@sifive.com>
+ Jia-Wei Chen <jiawei@iscas.ac.cn>
+
+ * config/riscv/bitmanip.md (*zero_extendsidi2_bitmanip): New.
+ (*shNadd): Ditto.
+ (*shNadduw): Ditto.
+ (*add.uw): Ditto.
+ (*slliuw): Ditto.
+ (riscv_rtx_costs): Ditto.
+ * config/riscv/riscv.md: Include bitmanip.md
+ (type): Add bitmanip bype.
+ (zero_extendsidi2): Change to define_expand pattern.
+ (*zero_extendsidi2_internal): New.
+ (zero_extendsidi2_shifted): Disable for ZBA.
+
+2021-10-25 Kito Cheng <kito.cheng@sifive.com>
+
+ * common/config/riscv/riscv-common.c (riscv_ext_version_table):
+ Add zba, zbb, zbc and zbs.
+ (riscv_ext_flag_table): Ditto.
+ * config/riscv/riscv-opts.h (MASK_ZBA): New.
+ (MASK_ZBB): Ditto.
+ (MASK_ZBC): Ditto.
+ (MASK_ZBS): Ditto.
+ (TARGET_ZBA): Ditto.
+ (TARGET_ZBB): Ditto.
+ (TARGET_ZBC): Ditto.
+ (TARGET_ZBS): Ditto.
+ * config/riscv/riscv.opt (riscv_zb_subext): New.
+
+2021-10-25 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102464
+ * match.pd: Simplify (_Float16) sqrtf((float) a) to .SQRT(a)
+ when direct_internal_fn_supported_p, similar for sqrt/sqrtl.
+
+2021-10-25 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102920
+ * tree-ssa-sccvn.h (expressions_equal_p): Add argument
+ controlling VN_TOP matching behavior.
+ * tree-ssa-sccvn.c (expressions_equal_p): Likewise.
+ (vn_phi_eq): Do not optimistically match VN_TOP.
+
+2021-10-25 konglin1 <lingling.kong@intel.com>
+
+ * config/i386/sse.md (fma_<mode>_fadd_fmul): Add new
+ define_insn_and_split.
+ (fma_<mode>_fadd_fcmul):Likewise
+ (fma_<complexopname>_<mode>_fma_zero):Likewise
+
+2021-10-24 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa-d.c (pa_d_handle_target_float_abi): Don't check
+ TARGET_DISABLE_FPREGS.
+ * config/pa/pa.c (fix_range): Use MASK_SOFT_FLOAT instead of
+ MASK_DISABLE_FPREGS.
+ (hppa_rtx_costs): Don't check TARGET_DISABLE_FPREGS. Adjust
+ cost of hardware integer multiplication.
+ (pa_conditional_register_usage): Don't check TARGET_DISABLE_FPREGS.
+ * config/pa/pa.h (INT14_OK_STRICT): Likewise.
+ * config/pa/pa.md: Don't check TARGET_DISABLE_FPREGS. Check
+ TARGET_SOFT_FLOAT in patterns that use xmpyu instruction.
+ * config/pa/pa.opt (mdisable-fpregs): Change target mask to
+ SOFT_FLOAT. Revise comment.
+ (msoft-float): New option.
+
+2021-10-24 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.md: Don't use 'G' constraint in integer move patterns.
+
+2021-10-24 Gerald Pfeifer <gerald@pfeifer.com>
+
+ * doc/install.texi (Specific): Remove obsolete details
+ around GNU/Linux on Itanium.
+ (Specific): Remove reference to Windows for Itanium.
+
+2021-10-23 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
+
+ * config/i386/x86-tune-sched-bd.c (dispatch_group): Commentary
+ typo fix.
+
+2021-10-23 Jan Hubicka <hubicka@ucw.cz>
+
+ * tree-ssa-structalias.c (compute_points_to_sets): Cleanup.
+
+2021-10-23 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/i386/sse.md (<any_logic>v1ti3): New define_insn to
+ implement V1TImode AND, IOR and XOR on TARGET_SSE2 (and above).
+ (one_cmplv1ti2): New define expand.
+
+2021-10-22 Eric Gallager <egallager@gcc.gnu.org>
+
+ PR other/102663
+ * Makefile.in: Handle dvidir and install-dvi target.
+ * configure: Regenerate.
+ * configure.ac: Add install-dvi to target_list.
+
+2021-10-22 Gerald Pfeifer <gerald@pfeifer.com>
+
+ * doc/install.texi (Binaries): Convert mingw-w64.org to https.
+ (Specific): Ditto.
+
+2021-10-22 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102893
+ * tree-ssa-dce.c (find_obviously_necessary_stmts): Fix the
+ test for an exit edge.
+
+2021-10-22 Aldy Hernandez <aldyh@redhat.com>
+ Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::compute_phi_relations):
+ Kill any global relations we may know before registering a new
+ one.
+ * value-relation.cc (path_oracle::killing_def): New.
+ * value-relation.h (path_oracle::killing_def): New.
+
+2021-10-22 Richard Biener <rguenther@suse.de>
+
+ PR bootstrap/102681
+ * tree-ssa-sccvn.c (vn_phi_insert): For undefined SSA args
+ record VN_TOP.
+ (vn_phi_lookup): Likewise.
+
+2021-10-21 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/98667
+ * doc/invoke.texi: Document -fcf-protection requires i686 or
+ new.
+
+2021-10-21 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR middle-end/102764
+ * cfgexpand.c (expand_gimple_basic_block): Robustify latest change.
+
+2021-10-21 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/arm_neon.h (__STRUCTN): Delete function
+ macro and all invocations.
+
+2021-10-21 Andrew MacLeod <amacleod@redhat.com>
+
+ * doc/invoke.texi (ranger-debug): Document.
+ * flag-types.h (enum ranger_debug): New.
+ (enum evrp_mode): Remove debug values.
+ * gimple-range-cache.cc (DEBUG_RANGE_CACHE): Use new debug flag.
+ * gimple-range-gori.cc (gori_compute::gori_compute): Ditto.
+ * gimple-range.cc (gimple_ranger::gimple_ranger): Ditto.
+ * gimple-ssa-evrp.c (hybrid_folder::choose_value): Ditto.
+ (execute_early_vrp): Use evrp-mode directly.
+ * params.opt (enum evrp_mode): Remove debug values.
+ (ranger-debug): New.
+ (ranger-logical-depth): Relocate to be in alphabetical order.
+
+2021-10-21 Andrew MacLeod <amacleod@redhat.com>
+
+ * doc/invoke.texi: (vrp1-mode, vrp2-mode): Document.
+ * flag-types.h: (enum vrp_mode): New.
+ * params.opt: (vrp1-mode, vrp2-mode): New.
+ * tree-vrp.c (vrp_pass_num): New.
+ (pass_vrp::pass_vrp): Set pass number.
+ (pass_vrp::execute): Choose which VRP mode to execute.
+
+2021-10-21 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-ssa-evrp.c (class rvrp_folder): Move to tree-vrp.c.
+ (execute_early_vrp): For ranger only mode, invoke ranger_vrp.
+ * tree-vrp.c (class rvrp_folder): Relocate here.
+ (execute_ranger_vrp): New.
+ * tree-vrp.h (execute_ranger_vrp): Export.
+
+2021-10-21 Martin Liska <mliska@suse.cz>
+
+ PR debug/102585
+ PR bootstrap/102766
+ * opts.c (finish_options): Process flag_var_tracking* options
+ here as they can be adjusted by optimize attribute.
+ Process also flag_syntax_only and flag_gtoggle.
+ * toplev.c (process_options): Remove it here.
+ * common.opt: Make debug_nonbind_markers_p as PerFunction
+ attribute as it depends on optimization level.
+
+2021-10-21 Martin Jambor <mjambor@suse.cz>
+
+ PR tree-optimization/102505
+ * tree-sra.c (totally_scalarize_subtree): Check that the
+ encountered field fits within the acces we would like to put it
+ in.
+
+2021-10-21 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c
+ (back_threader::maybe_register_path): Remove circular paths check.
+
+2021-10-21 Richard Biener <rguenther@suse.de>
+
+ * toplev.c (process_options): Move the initial debug_hooks
+ setting ...
+ (toplev::main): ... before the call of the post_options
+ langhook.
+
+2021-10-21 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102847
+ * tree-vect-stmts.c (vect_model_load_cost): Add the scalar
+ load cost in the prologue for VMAT_INVARIANT.
+
+2021-10-21 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102847
+ * tree-vect-stmts.c (vect_model_load_cost): Explicitely
+ handle VMAT_INVARIANT as a splat in the prologue.
+
+2021-10-21 Hongyu Wang <hongyu.wang@intel.com>
+
+ PR target/102812
+ * config/i386/i386.c (ix86_get_ssemov): Adjust HFmode vector
+ move to use the same logic as HImode.
+
+2021-10-21 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-slp.c (vect_build_slp_tree_1): Remove
+ superfluous gimple_call_nothrow_p check.
+
+2021-10-21 Andrew Pinski <apinski@marvell.com>
+
+ * tree-cfg.c (maybe_remove_writeonly_store): Add dce_ssa_names argument.
+ Mark the ssa-name of the rhs as one to be removed.
+ (execute_fixup_cfg): Update call to maybe_remove_writeonly_store.
+ Call simple_dce_from_worklist at the end to a simple dce.
+
+2021-10-21 Andrew Pinski <apinski@marvell.com>
+
+ * tree-cfg.c (maybe_remove_writeonly_store): New function
+ factored out from ...
+ (execute_fixup_cfg): Here. Call maybe_remove_writeonly_store.
+
+2021-10-21 Andrew Pinski <apinski@marvell.com>
+
+ * tree-cfg.c (execute_fixup_cfg): Remove comment
+ about standalone pass.
+
+2021-10-21 Andrew Pinski <apinski@marvell.com>
+
+ * tree-cfg.c (execute_fixup_cfg): Output when the statement
+ is removed when it is a write only var.
+
+2021-10-21 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (back_threader::maybe_register_path):
+ Avoid threading circular paths.
+
+2021-10-20 Alex Coplan <alex.coplan@arm.com>
+
+ * calls.c (initialize_argument_information): Remove some dead
+ code, remove handling for function_arg returning const_int.
+ * doc/tm.texi: Delete documentation for unused target hooks.
+ * doc/tm.texi.in: Likewise.
+ * target.def (load_bounds_for_arg): Delete.
+ (store_bounds_for_arg): Delete.
+ (load_returned_bounds): Delete.
+ (store_returned_bounds): Delete.
+ * targhooks.c (default_load_bounds_for_arg): Delete.
+ (default_store_bounds_for_arg): Delete.
+ (default_load_returned_bounds): Delete.
+ (default_store_returned_bounds): Delete.
+ * targhooks.h (default_load_bounds_for_arg): Delete.
+ (default_store_bounds_for_arg): Delete.
+ (default_load_returned_bounds): Delete.
+ (default_store_returned_bounds): Delete.
+
+2021-10-20 Jonathan Wakely <jwakely@redhat.com>
+
+ * doc/extend.texi (Basic Asm): Clarify that asm is not an
+ extension in C++.
+ * doc/invoke.texi (-fno-asm): Fix description for C++.
+
+2021-10-20 Jonathan Wakely <jwakely@redhat.com>
+
+ * doc/install.texi: Remove link to old.html
+
+2021-10-20 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-simd.md (*aarch64_cmtst_same_<mode>): New.
+
+2021-10-20 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-simd.md (*aarch64_narrow_trunc<mode>): New.
+
+2021-10-20 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-simd.md (aarch64_simd_ashr<mode>): Add case cmp
+ case.
+ * config/aarch64/constraints.md (D1): New.
+
+2021-10-20 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-simd.md
+ (*aarch64_<srn_op>topbits_shuffle<mode>_le): New.
+ (*aarch64_topbits_shuffle<mode>_le): New.
+ (*aarch64_<srn_op>topbits_shuffle<mode>_be): New.
+ (*aarch64_topbits_shuffle<mode>_be): New.
+ * config/aarch64/predicates.md
+ (aarch64_simd_shift_imm_vec_exact_top): New.
+
+2021-10-20 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-simd.md (*aarch64_<srn_op>shrn<mode>_vect,
+ *aarch64_<srn_op>shrn<mode>2_vect_le,
+ *aarch64_<srn_op>shrn<mode>2_vect_be): New.
+ * config/aarch64/iterators.md (srn_op): New.
+
+2021-10-20 Chung-Lin Tang <cltang@codesourcery.com>
+
+ * omp-low.c (omp_copy_decl_2): For !ctx, use record_vars to add new copy
+ as local variable.
+ (scan_sharing_clauses): Place copy of OMP_CLAUSE_IN_REDUCTION decl in
+ ctx->outer instead of ctx.
+
+2021-10-20 Martin Liska <mliska@suse.cz>
+
+ Revert:
+ 2021-10-19 Martin Liska <mliska@suse.cz>
+
+ PR target/102374
+ * config/i386/i386-options.c (ix86_valid_target_attribute_inner_p): Strip whitespaces.
+ * system.h (strip_whilespaces): New function.
+
+2021-10-20 Martin Liska <mliska@suse.cz>
+
+ Revert:
+ 2021-10-19 Martin Liska <mliska@suse.cz>
+
+ PR target/102375
+ * config/aarch64/aarch64.c (aarch64_process_one_target_attr):
+ Strip whitespaces.
+
+2021-10-20 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_case_values_threshold):
+ Change to 8 with -Os, 11 otherwise.
+
+2021-10-20 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/aarch64/aarch64.c (neoversev1_tunings):
+ Enable AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND.
+ (neoversen2_tunings): Likewise.
+
+2021-10-20 Wilco Dijkstra <wdijkstr@arm.com>
+
+ PR target/100966
+ * config/aarch64/aarch64.md (frint_pattern): Update comment.
+ * config/aarch64/aarch64-simd-builtins.def: Change frintn to roundeven.
+ * config/aarch64/arm_fp16.h: Change frintn to roundeven.
+ * config/aarch64/arm_neon.h: Likewise.
+ * config/aarch64/iterators.md (frint_pattern): Use roundeven for FRINTN.
+
+2021-10-20 Martin Liska <mliska@suse.cz>
+
+ * config/arm/arm.c (arm_unwind_emit_sequence): Do not declare
+ already declared global variable.
+ (arm_unwind_emit_set): Use out_file as function argument.
+ (arm_unwind_emit): Likewise.
+ * config/darwin.c (machopic_output_data_section_indirection): Likewise.
+ (machopic_output_stub_indirection): Likewise.
+ (machopic_output_indirection): Likewise.
+ (machopic_finish): Likewise.
+ * config/i386/i386.c (ix86_asm_output_function_label): Likewise.
+ * config/i386/winnt.c (i386_pe_seh_unwind_emit): Likewise.
+ * config/ia64/ia64.c (process_epilogue): Likewise.
+ (process_cfa_adjust_cfa): Likewise.
+ (process_cfa_register): Likewise.
+ (process_cfa_offset): Likewise.
+ (ia64_asm_unwind_emit): Likewise.
+ * config/s390/s390.c (s390_asm_output_function_label): Likewise.
+
+2021-10-20 Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64-builtins.c
+ (aarch64_general_gimple_fold_builtin):
+ lower vld1 and vst1 variants of the neon builtins
+ * config/aarch64/aarch64-protos.h:
+ (aarch64_general_gimple_fold_builtin): Add gsi parameter.
+ * config/aarch64/aarch64.c (aarch64_general_gimple_fold_builtin):
+ Likwise.
+
+2021-10-20 Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com>
+
+ * match.pd: Generate IFN_TRUNC.
+
+2021-10-20 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102853
+ * tree-data-ref.c (split_constant_offset_1): Bail out
+ immediately if the expression traps on overflow.
+
+2021-10-20 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (back_threader::~back_threader): Remove.
+
+2021-10-20 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadupdate.c (back_jt_path_registry::adjust_paths_after_duplication):
+ Remove superflous debugging message.
+ (back_jt_path_registry::duplicate_thread_path): Same.
+
+2021-10-20 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (back_threader_registry::back_threader_registry):
+ Remove.
+ (back_threader_registry::register_path): Remove m_threaded_paths.
+
+2021-10-20 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/102814
+ * doc/invoke.texi: Document --param=max-fsm-thread-length.
+ * params.opt: Add --param=max-fsm-thread-length.
+ * tree-ssa-threadbackward.c
+ (back_threader_profitability::profitable_path_p): Fail on paths
+ longer than max-fsm-thread-length.
+
+2021-10-20 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR middle-end/102764
+ * cfgexpand.c (expand_gimple_basic_block): Disregard a final debug
+ statement to reset the current location for the outgoing edges.
+
+2021-10-20 Aldy Hernandez <aldyh@redhat.com>
+ Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-threadupdate.c (cancel_thread): Dump threading reason
+ on the same line as the threading cancellation.
+ (jt_path_registry::cancel_invalid_paths): Avoid rotating loops.
+ Avoid threading through loop headers where the path remains in the
+ loop.
+
+2021-10-20 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ * tree-object-size.c (unknown): Make into a function. Adjust
+ all uses.
+ (unknown_object_size): Simplify implementation.
+
+2021-10-20 Hongtao Liu <hongtao.liu@intel.com>
+ Kewen Lin <linkw@linux.ibm.com>
+
+ * doc/sourcebuild.texi (Effective-Target Keywords): Document
+ vect_slp_v2qi_store, vect_slp_v4qi_store, vect_slp_v8qi_store,
+ vect_slp_v16qi_store, vect_slp_v2hi_store,
+ vect_slp_v4hi_store, vect_slp_v2si_store, vect_slp_v4si_store.
+
+2021-10-19 Jonathan Wakely <jwakely@redhat.com>
+
+ * doc/extend.texi (Basic PowerPC Built-in Functions): Fix typo.
+
+2021-10-19 Paul A. Clarke <pc@us.ibm.com>
+
+ PR target/101893
+ PR target/102719
+ * config/rs6000/emmintrin.h: Guard POWER8 intrinsics.
+ * config/rs6000/pmmintrin.h: Same.
+ * config/rs6000/smmintrin.h: Same.
+ * config/rs6000/tmmintrin.h: Same.
+
+2021-10-19 Paul A. Clarke <pc@us.ibm.com>
+
+ * config.gcc (extra_headers): Add nmmintrin.h.
+
+2021-10-19 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (vect_supportable_dr_alignment): Add
+ misalignment parameter.
+ * tree-vect-data-refs.c (vect_get_peeling_costs_all_drs):
+ Do not change DR_MISALIGNMENT in place, instead pass the
+ adjusted misalignment to vect_supportable_dr_alignment.
+ (vect_peeling_supportable): Likewise.
+ (vect_peeling_hash_get_lowest_cost): Adjust.
+ (vect_enhance_data_refs_alignment): Likewise.
+ (vect_vfa_access_size): Likewise.
+ (vect_supportable_dr_alignment): Add misalignment
+ parameter and simplify.
+ * tree-vect-stmts.c (get_negative_load_store_type): Adjust.
+ (get_group_load_store_type): Likewise.
+ (get_load_store_type): Likewise.
+
+2021-10-19 Clément Chigot <clement.chigot@atos.net>
+
+ * config/rs6000/rs6000.c (rs6000_xcoff_file_end): Move
+ __tls_get_addr reference to .text csect.
+
+2021-10-19 Martin Liska <mliska@suse.cz>
+
+ PR target/102375
+ * config/aarch64/aarch64.c (aarch64_process_one_target_attr):
+ Strip whitespaces.
+
+2021-10-19 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (vect_get_store_cost): Adjust signature.
+ (vect_get_load_cost): Likewise.
+ * tree-vect-data-refs.c (vect_get_data_access_cost): Get
+ alignment support scheme and misalignment as arguments
+ and pass them down.
+ (vect_get_peeling_costs_all_drs): Compute that info here
+ and note that we shouldn't need to.
+ * tree-vect-stmts.c (vect_model_store_cost): Get
+ alignment support scheme and misalignment as arguments.
+ (vect_get_store_cost): Likewise.
+ (vect_model_load_cost): Likewise.
+ (vect_get_load_cost): Likewise.
+ (vectorizable_store): Pass down alignment support scheme
+ and misalignment to costing.
+ (vectorizable_load): Likewise.
+
+2021-10-19 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-stmts.c (get_negative_load_store_type): Add
+ offset output parameter and initialize it.
+ (get_group_load_store_type): Likewise.
+ (get_load_store_type): Likewise.
+ (vectorizable_store): Use offset as computed by
+ get_load_store_type.
+ (vectorizable_load): Likewise.
+
+2021-10-19 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102827
+ * tree-if-conv.c (predicate_statements): Add pe parameter
+ and use that edge to insert invariant stmts on.
+ (combine_blocks): Pass through pe.
+ (tree_if_conversion): Compute the edge to insert invariant
+ stmts on and pass it along.
+
+2021-10-19 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR target/102785
+ * config/bfin/bfin.md (addsubv2hi3, subaddv2hi3, ssaddsubv2hi3,
+ sssubaddv2hi3): Swap the order of operators in vec_concat.
+
+2021-10-19 Xionghu Luo <luoxhu@linux.ibm.com>
+
+ * config/rs6000/altivec.md (*altivec_vmrghb_internal): Delete.
+ (altivec_vmrghb_direct): New.
+ (*altivec_vmrghh_internal): Delete.
+ (altivec_vmrghh_direct): New.
+ (*altivec_vmrghw_internal): Delete.
+ (altivec_vmrghw_direct_<mode>): New.
+ (altivec_vmrghw_direct): Delete.
+ (*altivec_vmrglb_internal): Delete.
+ (altivec_vmrglb_direct): New.
+ (*altivec_vmrglh_internal): Delete.
+ (altivec_vmrglh_direct): New.
+ (*altivec_vmrglw_internal): Delete.
+ (altivec_vmrglw_direct_<mode>): New.
+ (altivec_vmrglw_direct): Delete.
+ * config/rs6000/rs6000-p8swap.c (rtx_is_swappable_p): Adjust.
+ * config/rs6000/rs6000.c (altivec_expand_vec_perm_const):
+ Adjust.
+ * config/rs6000/vsx.md (vsx_xxmrghw_<mode>): Adjust.
+ (vsx_xxmrglw_<mode>): Adjust.
+
+2021-10-19 Aldy Hernandez <aldyh@redhat.com>
+
+ * passes.def: Change threading comment before pass_ccp pass.
+
+2021-10-19 Haochen Gui <guihaoc@gcc.gnu.org>
+
+ * config/rs6000/rs6000-call.c (altivec_expand_lxvr_builtin):
+ Modify the expansion for sign extension. All extensions are done
+ within VSX registers.
+
+2021-10-19 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-stmts.c (get_group_load_store_type): Add
+ misalignment output parameter and initialize it.
+ (get_group_load_store_type): Likewise.
+ (vectorizable_store): Remove now redundant queries.
+ (vectorizable_load): Likewise.
+
+2021-10-19 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (vect_supportable_dr_alignment): Remove
+ check_aligned argument.
+ * tree-vect-data-refs.c (vect_supportable_dr_alignment):
+ Likewise.
+ (vect_peeling_hash_insert): Add supportable_if_not_aligned
+ argument and do not call vect_supportable_dr_alignment here.
+ (vect_peeling_supportable): Adjust.
+ (vect_enhance_data_refs_alignment): Compute whether the
+ access is supported with different alignment here and
+ pass that down to vect_peeling_hash_insert.
+ (vect_vfa_access_size): Adjust.
+ * tree-vect-stmts.c (vect_get_store_cost): Likewise.
+ (vect_get_load_cost): Likewise.
+ (get_negative_load_store_type): Likewise.
+ (get_group_load_store_type): Likewise.
+ (get_load_store_type): Likewise.
+
+2021-10-19 Martin Liska <mliska@suse.cz>
+
+ PR target/102374
+ * config/i386/i386-options.c (ix86_valid_target_attribute_inner_p): Strip whitespaces.
+ * system.h (strip_whilespaces): New function.
+
+2021-10-19 dianhong xu <dianhong.xu@intel.com>
+
+ * config/i386/avx512fp16intrin.h:
+ (_mm512_set1_pch): New intrinsic.
+ * config/i386/avx512fp16vlintrin.h:
+ (_mm256_set1_pch): New intrinsic.
+ (_mm_set1_pch): Ditto.
+
+2021-10-18 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/102796
+ * gimple-range.cc (gimple_ranger::range_on_edge): Process EH edges
+ normally. Return get_tree_range for non gimple_range_ssa_p names.
+ (gimple_ranger::range_of_stmt): Use get_tree_range for non
+ gimple_range_ssa_p names.
+
+2021-10-18 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/102761
+ * config/i386/i386.c (ix86_print_operand_address):
+ Error out for non-address_operand asm operands.
+
+2021-10-18 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-data-refs.c (vect_peeling_hash_insert): Do
+ not auto-convert dr_alignment_support to bool.
+ (vect_peeling_supportable): Likewise.
+ (vect_enhance_data_refs_alignment): Likewise.
+ (vect_supportable_dr_alignment): Commonize read/write case.
+ * tree-vect-stmts.c (vect_get_store_cost): Use
+ dr_alignment_support, not int, for the vect_supportable_dr_alignment
+ result.
+ (vect_get_load_cost): Likewise.
+
+2021-10-18 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ * tree-object-size.c (object_sizes_execute): Consolidate LHS
+ null check and do it early.
+
+2021-10-18 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-stmts.c (vectorizable_store): Use the
+ computed alignment scheme instead of querying
+ aligned_access_p.
+
+2021-10-18 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-stmts.c (vectorizable_store): Do not recompute
+ alignment scheme already determined by get_load_store_type.
+
+2021-10-18 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (class pass_thread_jumps_full):
+ Clone corresponding pass.
+
+2021-10-18 Roger Sayle <roger@nextmovesoftware.com>
+
+ * combine.c (recog_for_combine): For an unrecognized move/set of
+ a constant, try force_const_mem to place it in the constant pool.
+ * cse.c (constant_pool_entries_cost, constant_pool_entries_regcost):
+ Delete global variables (that are no longer assigned a cost value).
+ (cse_insn): Simplify logic for deciding whether to place a folded
+ constant in the constant pool using force_const_mem.
+ (cse_main): Remove zero initialization of constant_pool_entries_cost
+ and constant_pool_entries_regcost.
+ * config/i386/i386.c (ix86_rtx_costs): Make memory accesses
+ fractionally more expensive, when optimizing for speed.
+
+2021-10-18 Martin Liska <mliska@suse.cz>
+
+ PR gcov-profile/102746
+ PR gcov-profile/102747
+ * gcov.c (main): Return return_code.
+ (output_gcov_file): Mark return_code when error happens.
+ (generate_results): Likewise.
+ (read_graph_file): Likewise.
+ (read_count_file): Likewise.
+
+2021-10-18 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/bfin/bfin.md (define_constants): Remove UNSPEC_ONES.
+ (define_insn "ones"): Replace UNSPEC_ONES with a truncate of
+ a popcount, allowing compile-time evaluation/simplification.
+ (popcountsi2, popcounthi2): New expanders using a "ones" insn.
+
+2021-10-18 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102788
+ * tree-vect-patterns.c (vect_init_pattern_stmt): Allow
+ a NULL vectype.
+ (vect_pattern_recog_1): Likewise.
+ (vect_recog_bool_pattern): Continue matching the pattern
+ even if we do not have a vector type for a conversion
+ result.
+
+2021-10-18 Roger Sayle <roger@nextmovesoftware.com>
+
+ * simplify-rtx.c (simplify_const_unary_operation) [SS_NEG, SS_ABS]:
+ Evalute SS_NEG and SS_ABS of a constant argument.
+
+2021-10-18 prathamesh.kulkarni <prathamesh.kulkarni@linaro.org>
+
+ PR target/93183
+ * gimple-match-head.c (try_conditional_simplification): Add case for single operand.
+ * internal-fn.def: Add entry for COND_NEG internal function.
+ * internal-fn.c (FOR_EACH_CODE_MAPPING): Add entry for
+ NEGATE_EXPR, COND_NEG mapping.
+ * optabs.def: Add entry for cond_neg_optab.
+ * match.pd (UNCOND_UNARY, COND_UNARY): New operator lists.
+ (vec_cond COND (foo A) B) -> (IFN_COND_FOO COND A B): New pattern.
+ (vec_cond COND B (foo A)) -> (IFN_COND_FOO ~COND A B): Likewise.
+
+2021-10-18 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-strlen.c (class strlen_pass): Rename from
+ strlen_dom_walker.
+ (handle_builtin_stxncpy_strncat): Move to strlen_pass.
+ (handle_assign): Same.
+ (adjust_last_stmt): Same.
+ (maybe_warn_overflow): Same.
+ (handle_builtin_strlen): Same.
+ (handle_builtin_strchr): Same.
+ (handle_builtin_strcpy): Same.
+ (handle_builtin_strncat): Same.
+ (handle_builtin_stxncpy_strncat): Same.
+ (handle_builtin_memcpy): Same.
+ (handle_builtin_strcat): Same.
+ (handle_alloc_call): Same.
+ (handle_builtin_memset): Same.
+ (handle_builtin_memcmp): Same.
+ (get_len_or_size): Same.
+ (strxcmp_eqz_result): Same.
+ (handle_builtin_string_cmp): Same.
+ (handle_pointer_plus): Same.
+ (count_nonzero_bytes_addr): Same.
+ (count_nonzero_bytes): Same.
+ (handle_store): Same.
+ (strlen_check_and_optimize_call): Same.
+ (handle_integral_assign): Same.
+ (check_and_optimize_stmt): Same.
+ (printf_strlen_execute): Rename strlen_dom_walker to strlen_pass.
+
+2021-10-18 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102798
+ * tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref):
+ Only copy points-to info to newly generated SSA names.
+
+2021-10-18 Martin Liska <mliska@suse.cz>
+
+ * dbgcnt.c (dbg_cnt_process_opt): Remove unused but set variable.
+ * gcov.c (get_cycles_count): Likewise.
+ * lto-compress.c (lto_compression_zlib): Likewise.
+ (lto_uncompression_zlib): Likewise.
+ * targhooks.c (default_pch_valid_p): Likewise.
+
+2021-10-17 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-pass.h (make_pass_thread_jumps_full): New.
+ * tree-ssa-threadbackward.c (pass_thread_jumps::gate): Inline.
+ (try_thread_blocks): Add resolve and speed arguments.
+ (pass_thread_jumps::execute): Inline.
+ (do_early_thread_jumps): New.
+ (do_thread_jumps): New.
+ (make_pass_thread_jumps): Move.
+ (pass_early_thread_jumps::gate): Inline.
+ (pass_early_thread_jumps::execute): Inline.
+ (class pass_thread_jumps_full): New.
+
+2021-10-16 Piotr Kubaj <pkubaj@FreeBSD.org>
+
+ * configure.ac: Treat powerpc64*-*-freebsd* the same as
+ powerpc64-*-freebsd*.
+ * configure: Regenerate.
+
+2021-10-16 H.J. Lu <hjl.tools@gmail.com>
+
+ * value-query.cc (get_ssa_name_ptr_info_nonnull): Change
+ set_ptr_nonull to set_ptr_nonnull in comments.
+
+2021-10-16 Jan Hubicka <hubicka@ucw.cz>
+
+ PR tree-optimization/102720
+ * tree-ssa-structalias.c (compute_points_to_sets): Fix producing
+ of call used and clobbered sets.
+
+2021-10-15 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.h (LINK_COMMAND_SPEC_A): Update 'r' handling to
+ skip gomp and itm when r or nodefaultlibs is given.
+ (DSYMUTIL_SPEC): Do not call dsymutil for '-r' link lines.
+ Update ordering of exclusions, remove duplicate 'v' addition
+ (collect2 will add this from the main command line).
+
+2021-10-15 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin-driver.c (darwin_driver_init): Revise comments, handle
+ filelist and framework options in specs instead of code.
+ * config/darwin.h (SUBTARGET_DRIVER_SELF_SPECS): Update to handle link
+ specs that are really driver ones.
+ (DARWIN_CC1_SPEC): Likewise.
+ (CPP_SPEC): Likewise.
+ (SYSROOT_SPEC): Append space.
+ (LINK_SYSROOT_SPEC): Remove most driver link specs.
+ (STANDARD_STARTFILE_PREFIX_2): Update link-related specs.
+ (STARTFILE_SPEC): Likewise.
+ (ASM_MMACOSX_VERSION_MIN_SPEC): Fix line wrap.
+ (ASM_SPEC): Update driver-related specs.
+ (ASM_FINAL_SPEC): Likewise.
+ * config/darwin.opt: Remove now unused option aliases.
+ * config/i386/darwin.h (EXTRA_ASM_OPTS): Ensure space after opt.
+ (ASM_SPEC): Update driver-related specs.
+
+2021-10-15 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/i386/i386.c (ix86_hardreg_mov_ok): For vector modes,
+ allow standard_sse_constant_p immediate constants.
+
+2021-10-15 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config.gcc: Add tm-dwarf2.h to tm_d-file.
+
+2021-10-15 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-fold.h (gimple_range_ssa_p): Don't process names
+ that occur in abnormal phis.
+ * gimple-range.cc (gimple_ranger::range_on_edge): Return false for
+ abnormal and EH edges.
+ * gimple-ssa-evrp.c (rvrp_folder::value_of_expr): Ditto.
+ (rvrp_folder::value_on_edge): Ditto.
+ (rvrp_folder::value_of_stmt): Ditto.
+ (hybrid_folder::value_of_expr): Ditto for ranger queries.
+ (hybrid_folder::value_on_edge): Ditto.
+ (hybrid_folder::value_of_stmt): Ditto.
+ * value-query.cc (gimple_range_global): Always return a range if
+ the type is supported.
+
+2021-10-15 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.md: Consistently use "rG" constraint for copy
+ instruction in move patterns.
+
+2021-10-15 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/gcn-hsa.h (S_FIJI): Set unconditionally.
+ (S_900): Likewise.
+ (S_906): Likewise.
+ * config/gcn/gcn.c: Hard code SRAM ECC settings for old architectures.
+ * config/gcn/mkoffload.c (ELFABIVERSION_AMDGPU_HSA): Rename to ...
+ (ELFABIVERSION_AMDGPU_HSA_V3): ... this.
+ (ELFABIVERSION_AMDGPU_HSA_V4): New.
+ (SET_SRAM_ECC_UNSUPPORTED): New.
+ (copy_early_debug_info): Create elf flags to match the other objects.
+ (main): Just let the attribute flags pass through.
+
+2021-10-15 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * tree-loop-distribution.c (reduction_var_overflows_first):
+ Pass the type of reduction_var as first argument as it is also
+ done for the load type.
+ (loop_distribution::transform_reduction_loop): Add missing
+ TREE_TYPE while determining precission of reduction_var.
+
+2021-10-15 Richard Biener <rguenther@suse.de>
+
+ * defaults.h (PREFERRED_DEBUGGING_TYPE): Choose DWARF2_DEBUG
+ when not set.
+ * toplev.c (process_options): Warn when STABS debugging is
+ enabled but not the preferred format.
+ * config/pa/som.h (PREFERRED_DEBUGGING_TYPE): Define to
+ DBX_DEBUG.
+ * config/pdp11/pdp11.h (PREFERRED_DEBUGGING_TYPE): Likewise.
+
+2021-10-15 Richard Biener <rguenther@suse.de>
+
+ PR ipa/102762
+ * tree-inline.c (copy_bb): Avoid underflowing nargs.
+
+2021-10-15 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/i386-expand.c (ix86_expand_vec_perm): Convert
+ HFmode input operand to HImode.
+ (ix86_vectorize_vec_perm_const): Likewise.
+ * config/i386/sse.md (*avx512bw_permvar_truncv16siv16hi_1_hf):
+ New define_insn.
+ (*avx512f_permvar_truncv8siv8hi_1_hf):
+ Likewise.
+
+2021-10-15 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/102682
+ * expmed.c (store_bit_field_1): Ensure a LHS subreg would
+ not create a paradoxical subreg.
+
+2021-10-15 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/i386-expand.c (ix86_expand_vector_init):
+ For half_vector concat for HFmode, handle them like HImode.
+
+2021-10-14 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (class back_threader): Add m_resolve.
+ (back_threader::back_threader): Same.
+ (back_threader::resolve_phi): Try to solve without looking back if
+ possible.
+ (back_threader::find_paths_to_names): Same.
+ (try_thread_blocks): Pass resolve argument to back threader.
+ (pass_early_thread_jumps::execute): Same.
+
+2021-10-14 Aldy Hernandez <aldyh@redhat.com>
+
+ * doc/invoke.texi: Remove max-fsm-thread-length,
+ max-fsm-thread-paths, and fsm-maximum-phi-arguments.
+ * params.opt: Same.
+ * tree-ssa-threadbackward.c (back_threader::back_threader): Remove
+ argument.
+ (back_threader_registry::back_threader_registry): Same.
+ (back_threader_profitability::profitable_path_p): Remove
+ param_max_fsm_thread-length.
+ (back_threader_registry::register_path): Remove
+ m_max_allowable_paths.
+
+2021-10-14 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (class back_threader): Make m_imports
+ an auto_bitmap.
+ (back_threader::~back_threader): Do not release m_path.
+
+2021-10-14 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/102738
+ * vr-values.c (simplify_using_ranges::simplify): Handle RSHIFT_EXPR.
+
+2021-10-14 Kwok Cheung Yeung <kcy@codesourcery.com>
+
+ * omp-general.c (omp_check_context_selector): Move from c-omp.c.
+ (omp_mark_declare_variant): Move from c-omp.c.
+ (omp_context_name_list_prop): Update for Fortran strings.
+ * omp-general.h (omp_check_context_selector): New prototype.
+ (omp_mark_declare_variant): New prototype.
+
+2021-10-14 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/rs6000/rs6000.c (rs6000_density_test): Move early
+ exit test further up the function.
+
+2021-10-14 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/arm/arm.c (arm_add_stmt_cost): Delete.
+ (TARGET_VECTORIZE_ADD_STMT_COST): Delete.
+
+2021-10-14 Martin Jambor <mjambor@suse.cz>
+
+ * doc/invoke.texi (Optimize Options): Add entry for
+ ipa-cp-recursive-freq-factor.
+
+2021-10-14 Tamar Christina <tamar.christina@arm.com>
+
+ * match.pd: New rule.
+
+2021-10-14 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/102557
+ * ipa-modref-tree.h (modref_access_node::update2):
+ Also check that parm_offset is unchanged.
+ (modref_ref_node::insert_access): Fix updating of
+ parameter.
+
+2021-10-14 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (back_threader::resolve_phi): Add
+ FIXME note.
+
+2021-10-14 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102659
+ * tree-if-conv.c (if_convertible_gimple_assign_stmt_p): Also
+ rewrite pointer typed undefined overflow operations.
+ (predicate_statements): Likewise. Make sure to emit invariant
+ conversions in the preheader.
+ * tree-vectorizer.c (vect_loop_vectorized_call): Look through
+ non-empty preheaders.
+ * tree-data-ref.c (dr_analyze_indices): Strip useless
+ conversions to the MEM_REF base type.
+
+2021-10-14 Martin Liska <mliska@suse.cz>
+
+ * common.opt: Stop using AUTODETECT_VALUE
+ and use EnabledBy where possible.
+ * opts.c: Enable OPT_fvar_tracking with optimize >= 1.
+ * toplev.c (AUTODETECT_VALUE): Remove macro.
+ (process_options): Simplify by using EnabledBy and
+ OPT_fvar_tracking. Use OPTION_SET_P macro instead of
+ AUTODETECT_VALUE.
+
+2021-10-14 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/arm_neon.h (vld1_s8_x3): Use signed type for
+ pointer parameter.
+ (vld1_s32_x3): Likewise.
+
+2021-10-14 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/102736
+ PR tree-optimization/102736
+ * gimple-range-path.cc (path_range_query::range_on_path_entry):
+ Assert that the requested range is defined outside the path.
+ (path_range_query::ssa_range_in_phi): Do not call
+ range_on_path_entry for SSA names that are defined within the
+ path.
+
+2021-10-14 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin-driver.c (darwin_find_version_from_kernel):
+ Quote internal identifiers and avoid contractions in
+ warnings.
+ (darwin_default_min_version): Likewise.
+ (darwin_driver_init): Likewise.
+
+2021-10-14 Martin Jambor <mjambor@suse.cz>
+
+ * params.opt (ipa-cp-recursive-freq-factor): New.
+ * ipa-cp.c (ipcp_value): Switch to inline initialization. New members
+ scc_no, self_recursion_generated_level, same_scc and
+ self_recursion_generated_p.
+ (ipcp_lattice::add_value): Replaced parameter unlimited with
+ same_lat_gen_level, usit it determine limit of values and store it to
+ the value.
+ (ipcp_lattice<valtype>::print): Dump the new fileds.
+ (allocate_and_init_ipcp_value): Take same_lat_gen_level as a new
+ parameter and store it to the new value.
+ (self_recursively_generated_p): Removed.
+ (propagate_vals_across_arith_jfunc): Use self_recursion_generated_p
+ instead of self_recursively_generated_p, store self generation level
+ to such values.
+ (value_topo_info<valtype>::add_val): Set scc_no.
+ (value_topo_info<valtype>::propagate_effects): Multiply frequencies of
+ recursively feeding values and self generated values by appropriate
+ new factors.
+
+2021-10-14 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_add_stmt_cost): Remove
+ redundant test for flag_vect_cost_model.
+
+2021-10-14 Aldy Hernandez <aldyh@redhat.com>
+
+ * bitmap.c (debug): New overloaded function for auto_bitmaps.
+ * bitmap.h (debug): Same.
+
+2021-10-14 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm512_mask_fcmadd_pch):
+ Adjust builtin call.
+ (_mm512_mask3_fcmadd_pch): Likewise.
+ (_mm512_mask_fmadd_pch): Likewise
+ (_mm512_mask3_fmadd_pch): Likewise
+ (_mm512_mask_fcmadd_round_pch): Likewise
+ (_mm512_mask3_fcmadd_round_pch): Likewise
+ (_mm512_mask_fmadd_round_pch): Likewise
+ (_mm512_mask3_fmadd_round_pch): Likewise
+ (_mm_mask_fcmadd_sch): Likewise
+ (_mm_mask3_fcmadd_sch): Likewise
+ (_mm_mask_fmadd_sch): Likewise
+ (_mm_mask3_fmadd_sch): Likewise
+ (_mm_mask_fcmadd_round_sch): Likewise
+ (_mm_mask3_fcmadd_round_sch): Likewise
+ (_mm_mask_fmadd_round_sch): Likewise
+ (_mm_mask3_fmadd_round_sch): Likewise
+ (_mm_fcmadd_round_sch): Likewise
+ * config/i386/avx512fp16vlintrin.h (_mm_mask_fmadd_pch):
+ Adjust builtin call.
+ (_mm_mask3_fmadd_pch): Likewise
+ (_mm256_mask_fmadd_pch): Likewise
+ (_mm256_mask3_fmadd_pch): Likewise
+ (_mm_mask_fcmadd_pch): Likewise
+ (_mm_mask3_fcmadd_pch): Likewise
+ (_mm256_mask_fcmadd_pch): Likewise
+ (_mm256_mask3_fcmadd_pch): Likewise
+ * config/i386/i386-builtin.def: Add mask3 builtin for complex
+ fma, and adjust mask_builtin to corresponding expander.
+ * config/i386/i386-expand.c (ix86_expand_round_builtin):
+ Skip eraseing embedded rounding for expanders that emits
+ multiple insns.
+ * config/i386/sse.md (complexmove): New mode_attr.
+ (<avx512>_fmaddc_<mode>_mask1<round_expand_name>): New expander.
+ (<avx512>_fcmaddc_<mode>_mask1<round_expand_name>): Likewise.
+ (avx512fp16_fmaddcsh_v8hf_mask1<round_expand_name>): Likewise.
+ (avx512fp16_fcmaddcsh_v8hf_mask1<round_expand_name>): Likewise.
+ (avx512fp16_fcmaddcsh_v8hf_mask3<round_expand_name>): Likewise.
+ (avx512fp16_fmaddcsh_v8hf_mask3<round_expand_name>): Likewise.
+ * config/i386/subst.md (round_embedded_complex): New subst.
+
+2021-10-14 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.md (cbranchsf4): Disable if TARGET_SOFT_FLOAT.
+ (cbranchdf4): Likewise.
+ Add missing move patterns for TARGET_SOFT_FLOAT.
+
+2021-10-13 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/i386/i386-expand.c (ix86_expand_vector_move): Use a
+ pseudo intermediate when moving a SUBREG into a hard register,
+ by checking ix86_hardreg_mov_ok.
+ (ix86_expand_vector_extract): Store zero-extended SImode
+ intermediate in a pseudo, then set target using a SUBREG_PROMOTED
+ annotated subreg.
+ * config/i386/sse.md (mov<VMOVE>_internal): Prevent CSE creating
+ complex (SUBREG) sets of (vector) hard registers before reload, by
+ checking ix86_hardreg_mov_ok.
+
+2021-10-13 Indu Bhagat <indu.bhagat@oracle.com>
+
+ * ctfc.h (enum ctf_dtu_d_union_enum): Remove redundant comma.
+
+2021-10-13 Indu Bhagat <indu.bhagat@oracle.com>
+
+ * dwarf2ctf.c (gen_ctf_array_type): Fix typo in comment.
+
+2021-10-13 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/102630
+ * pointer-query.cc (compute_objsize_r): Handle named address spaces.
+
+2021-10-13 Iain Sandoe <iain@sandoe.co.uk>
+
+ * collect2.c (is_lto_object_file): Release simple-object
+ resources, close files.
+
+2021-10-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/arm/arm.c (thumb2_legitimate_address_p): Use VALID_MVE_MODE
+ when checking mve addressing modes.
+ (mve_vector_mem_operand): Fix the way we handle pre, post and offset
+ addressing modes.
+ (arm_print_operand): Fix printing of POST_ and PRE_MODIFY.
+ * config/arm/mve.md: Use mve_memory_operand predicate everywhere where
+ there is a single Ux constraint.
+
+2021-10-13 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.md (muldi3): Add support for inlining 64-bit
+ multiplication on 32-bit PA 1.1 and 2.0 targets.
+
+2021-10-13 Martin Liska <mliska@suse.cz>
+
+ PR gcov-profile/90364
+ * coverage.c (build_info): Emit checksum to the global variable.
+ (build_info_type): Add new field for checksum.
+ (coverage_obj_finish): Pass object_checksum.
+ (coverage_init): Use 0 as checksum for .gcno files.
+ * gcov-dump.c (dump_gcov_file): Dump also new checksum field.
+ * gcov.c (read_graph_file): Read also checksum.
+ * doc/invoke.texi: Document the behaviour change.
+
+2021-10-13 Richard Biener <rguenther@suse.de>
+
+ * gimple-iterator.h (gsi_iterator_update): Add GSI_LAST_NEW_STMT,
+ start at integer value 2.
+ * gimple-iterator.c (gsi_insert_seq_nodes_before): Update
+ the iterator for GSI_LAST_NEW_STMT.
+ (gsi_insert_seq_nodes_after): Likewise.
+ * tree-if-conv.c (predicate_statements): Use GSI_LAST_NEW_STMT.
+ * tree-ssa.c (execute_update_addresses_taken): Correct bogus
+ arguments to gsi_replace.
+
+2021-10-13 Martin Liska <mliska@suse.cz>
+
+ PR target/102688
+ * common.opt: Use EnabledBy instead of detection in
+ finish_options and process_options.
+ * opts.c (finish_options): Remove handling of
+ x_flag_unroll_all_loops.
+ * toplev.c (process_options): Likewise for flag_web and
+ flag_rename_registers.
+
+2021-10-13 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102659
+ * tree-if-conv.c (need_to_rewrite_undefined): New flag.
+ (if_convertible_gimple_assign_stmt_p): Mark the loop for
+ rewrite when stmts with undefined behavior on integer
+ overflow appear.
+ (combine_blocks): Predicate also when we need to rewrite stmts.
+ (predicate_statements): Rewrite affected stmts to something
+ with well-defined behavior on overflow.
+ (tree_if_conversion): Initialize need_to_rewrite_undefined.
+
+2021-10-13 Richard Biener <rguenther@suse.de>
+
+ PR ipa/102714
+ * ipa-sra.c (ptr_parm_has_nonarg_uses): Fix volatileness
+ check.
+
+2021-10-13 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * dwarf2ctf.c: Fix typo in comment.
+
+2021-10-12 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ PR target/101985
+ * config/rs6000/altivec.h (vec_cpsgn): Swap operand order.
+ * config/rs6000/rs6000-overload.def (VEC_COPYSIGN): Use SKIP to
+ avoid generating an automatic #define of vec_cpsgn. Use the
+ correct built-in for V4SFmode that doesn't depend on VSX.
+
+2021-10-12 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/85730
+ PR target/82524
+ * config/i386/i386.md (*add<mode>_1_slp): Rewrite as
+ define_insn_and_split pattern. Add alternative 1 and split it
+ post reload to insert operand 1 into the low part of operand 0.
+ (*sub<mode>_1_slp): Ditto.
+ (*and<mode>_1_slp): Ditto.
+ (*<any_or:code><mode>_1_slp): Ditto.
+ (*ashl<mode>3_1_slp): Ditto.
+ (*<any_shiftrt:insn><mode>3_1_slp): Ditto.
+ (*<any_rotate:insn><mode>3_1_slp): Ditto.
+ (*neg<mode>_1_slp): New insn_and_split pattern.
+ (*one_cmpl<mode>_1_slp): Ditto.
+
+2021-10-12 David Edelsohn <dje.gcc@gmail.com>
+
+ * doc/install.texi: Update MinGW and mingw-64 Binaries
+ download links.
+
+2021-10-12 Daniel Le Duc Khoi Nguyen <greenrecyclebin@gmail.com>
+
+ * doc/extend.texi (Common Variable Attributes): Fix typos in
+ alloc_size documentation.
+
+2021-10-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102696
+ * tree-vect-slp.c (vect_build_slp_tree_2): Properly mark
+ the tree fatally failed when we reject a BIT_FIELD_REF.
+
+2021-10-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102572
+ * tree-vect-stmts.c (vect_build_gather_load_calls): When
+ gathering the vectorized defs for the mask pass in the
+ desired mask vector type so invariants will be handled
+ correctly.
+
+2021-10-12 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-sve.md (*fcm<cmp_op><mode>_bic_combine,
+ *fcm<cmp_op><mode>_nor_combine, *fcmuo<mode>_bic_combine,
+ *fcmuo<mode>_nor_combine): New.
+
+2021-10-12 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR target/102588
+ * config/sparc/sparc-modes.def (OI): New integer mode.
+
+2021-10-12 Jakub Jelinek <jakub@redhat.com>
+
+ * gimple-fold.h (clear_padding_type_may_have_padding_p): Declare.
+ * gimple-fold.c (clear_padding_type_may_have_padding_p): No longer
+ static.
+
+2021-10-12 Jakub Jelinek <jakub@redhat.com>
+
+ * tree-vectorizer.h (loop_cost_model): New function.
+ (unlimited_cost_model): Use it.
+ * tree-vect-loop.c (vect_analyze_loop_costing): Use loop_cost_model
+ call instead of flag_vect_cost_model.
+ * tree-vect-data-refs.c (vect_enhance_data_refs_alignment): Likewise.
+ (vect_prune_runtime_alias_test_list): Likewise. Also use it instead
+ of flag_simd_cost_model.
+
+2021-10-12 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102483
+ * config/i386/i386-expand.c (emit_reduc_half): Handle
+ V4QImode.
+ * config/i386/mmx.md (reduc_<code>_scal_v4qi): New expander.
+ (reduc_plus_scal_v4qi): Ditto.
+
+2021-10-12 Paul A. Clarke <pc@us.ibm.com>
+
+ * config/rs6000/smmintrin.h (_mm_cmpeq_epi64, _mm_cmpgt_epi64,
+ _mm_mullo_epi32, _mm_mul_epi32, _mm_packus_epi32): New.
+ * config/rs6000/nmmintrin.h: Copy from i386, tweak to suit.
+
+2021-10-12 Paul A. Clarke <pc@us.ibm.com>
+
+ * config/rs6000/smmintrin.h (_mm_cvtepi8_epi16, _mm_cvtepi8_epi32,
+ _mm_cvtepi8_epi64, _mm_cvtepi16_epi32, _mm_cvtepi16_epi64,
+ _mm_cvtepi32_epi64, _mm_cvtepu8_epi16, _mm_cvtepu8_epi32,
+ _mm_cvtepu8_epi64, _mm_cvtepu16_epi32, _mm_cvtepu16_epi64,
+ _mm_cvtepu32_epi64): New.
+
+2021-10-12 Paul A. Clarke <pc@us.ibm.com>
+
+ * config/rs6000/smmintrin.h (_mm_test_all_zeros,
+ _mm_test_all_ones, _mm_test_mix_ones_zeros): Rewrite as macro.
+
+2021-10-12 Paul A. Clarke <pc@us.ibm.com>
+
+ * config/rs6000/smmintrin.h (_mm_min_epi8, _mm_min_epu16,
+ _mm_min_epi32, _mm_min_epu32, _mm_max_epi8, _mm_max_epu16,
+ _mm_max_epi32, _mm_max_epu32): New.
+
+2021-10-11 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref-tree.h (struct modref_access_node): Revert
+ accidental change.
+ (struct modref_ref_node): Likewise.
+
+2021-10-11 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref-tree.h (modref_tree::global_access_p): New member
+ function.
+ * ipa-modref.c:
+ (implicint_const_eaf_flags,implicit_pure_eaf_flags,
+ ignore_stores_eaf_flags): Move to ipa-modref.h
+ (remove_useless_eaf_flags): Remove early exit on NOCLOBBER.
+ (modref_summary::global_memory_read_p): New member function.
+ (modref_summary::global_memory_written_p): New member function.
+ * ipa-modref.h (modref_summary::global_memory_read_p,
+ modref_summary::global_memory_written_p): Declare.
+ (implicint_const_eaf_flags,implicit_pure_eaf_flags,
+ ignore_stores_eaf_flags): move here.
+ * tree-ssa-structalias.c: Include ipa-modref-tree.h, ipa-modref.h
+ and attr-fnspec.h.
+ (handle_rhs_call): Rewrite.
+ (handle_call_arg): New function.
+ (determine_global_memory_access): New function.
+ (handle_const_call): Remove
+ (handle_pure_call): Remove
+ (find_func_aliases_for_call): Update use of handle_rhs_call.
+ (compute_points_to_sets): Handle global memory acccesses
+ selectively
+
+2021-10-11 Diane Meirowitz <diane.meirowitz@oracle.com>
+
+ * doc/invoke.texi: Add link to UndefinedBehaviorSanitizer
+ documentation, mention UBSAN_OPTIONS, similar to what is done
+ for AddressSanitizer.
+
+2021-10-11 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/102683
+ * internal-fn.c (expand_DEFERRED_INIT): Check for mode
+ availability before building an integer type for storage
+ purposes.
+
+2021-10-11 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/101480
+ * gimple.c (gimple_call_fnspec): Do not mark operator new/delete
+ as const.
+
+2021-10-11 Martin Liska <mliska@suse.cz>
+
+ * common.opt: Remove Init(2) for some options.
+ * toplev.c (process_options): Do not use AUTODETECT_VALUE, but
+ use rather OPTION_SET_P.
+
+2021-10-11 Martin Liska <mliska@suse.cz>
+
+ * common.opt: Remove usage of IRA_REGION_AUTODETECT.
+ * flag-types.h (enum ira_region): Likewise.
+ * toplev.c (process_options): Use OPTION_SET_P instead of
+ IRA_REGION_AUTODETECT.
+
+2021-10-11 Jakub Jelinek <jakub@redhat.com>
+
+ * omp-low.c (omp_runtime_api_call): Handle omp_get_max_teams,
+ omp_[sg]et_teams_thread_limit and omp_set_num_teams.
+
+2021-10-11 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * config/s390/s390-protos.h (s390_rawmemchr): Add prototype.
+ * config/s390/s390.c (s390_rawmemchr): New function.
+ * config/s390/s390.md (rawmemchr<SINT:mode>): New expander.
+ * config/s390/vector.md (@vec_vfees<mode>): Basically a copy of
+ the pattern vfees<mode> from vx-builtins.md.
+ * config/s390/vx-builtins.md (*vfees<mode>): Remove.
+
+2021-10-11 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * builtins.c (get_memory_rtx): Change to external linkage.
+ * builtins.h (get_memory_rtx): Add function prototype.
+ * doc/md.texi (rawmemchr<mode>): Document.
+ * internal-fn.c (expand_RAWMEMCHR): Define.
+ * internal-fn.def (RAWMEMCHR): Add.
+ * optabs.def (rawmemchr_optab): Add.
+ * tree-loop-distribution.c (find_single_drs): Change return code
+ behaviour by also returning true if no single store was found
+ but a single load.
+ (loop_distribution::classify_partition): Respect the new return
+ code behaviour of function find_single_drs.
+ (loop_distribution::execute): Call new function
+ transform_reduction_loop in order to replace rawmemchr or strlen
+ like loops by calls into builtins.
+ (generate_reduction_builtin_1): New function.
+ (generate_rawmemchr_builtin): New function.
+ (generate_strlen_builtin_1): New function.
+ (generate_strlen_builtin): New function.
+ (generate_strlen_builtin_using_rawmemchr): New function.
+ (reduction_var_overflows_first): New function.
+ (determine_reduction_stmt_1): New function.
+ (determine_reduction_stmt): New function.
+ (loop_distribution::transform_reduction_loop): New function.
+
+2021-10-11 Martin Liska <mliska@suse.cz>
+
+ * tree.c (cl_option_hasher::hash): Use cl_optimization_hash
+ and remove legacy hashing code.
+
+2021-10-11 Kito Cheng <kito.cheng@sifive.com>
+
+ PR target/100316
+ * builtins.c (maybe_emit_call_builtin___clear_cache): Allow
+ CONST_INT for BEGIN and END, and use gcc_assert rather than
+ error.
+
+2021-10-10 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/102441
+ * var-tracking.c (add_stores): For cselib_sp_derived_value_p values
+ use MO_VAL_SET if loc is not sp.
+
+2021-10-10 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/102622
+ * match.pd: Swap the order of a?pow2cst:0 and a?-1:0 transformations.
+ Swap the order of a?0:pow2cst and a?0:-1 transformations.
+
+2021-10-09 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102639
+ * config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Handle
+ HFmode.
+ (ix86_use_mask_cmp_p): Ditto.
+ (ix86_expand_sse_movcc): Ditto.
+ * config/i386/i386.md (setcc_hf_mask): New define_insn.
+ (movhf_mask): Ditto.
+ (UNSPEC_MOVCC_MASK): New unspec.
+ * config/i386/sse.md (UNSPEC_PCMP): Move to i386.md.
+
+2021-10-08 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR rtl-optimization/102627
+ * lra-constraints.c (split_reg): Use at least natural mode of hard reg.
+
+2021-10-08 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-cache.cc (non_null_ref::non_null_deref_p): Grow
+ bitmap if needed.
+
+2021-10-08 Aldy Hernandez <aldyh@redhat.com>
+
+ * value-range.cc (irange::debug): New.
+ * value-range.h (irange::debug): New.
+
+2021-10-08 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/102385
+ * predict.h (change_edge_frequency): Declare.
+ * predict.c (change_edge_frequency): New function.
+ * tree-ssa-loop-manip.h (tree_transform_and_unroll_loop): Remove
+ edge argument.
+ (tree_unroll_loop): Likewise.
+ * gimple-loop-jam.c (tree_loop_unroll_and_jam): Update accordingly.
+ * tree-predcom.c (pcom_worker::tree_predictive_commoning_loop):
+ Likewise.
+ * tree-ssa-loop-prefetch.c (loop_prefetch_arrays): Likewise.
+ * tree-ssa-loop-manip.c (tree_unroll_loop): Likewise.
+ (tree_transform_and_unroll_loop): Likewise. Use single_dom_exit
+ to retrieve the exit edges. Make all the old profile update code
+ conditional on !single_loop_p -- the case it was written for --
+ and use a different approach for the single-loop case.
+
+2021-10-08 Martin Liska <mliska@suse.cz>
+
+ * config/alpha/alpha.c (alpha_option_override): Use new macro
+ OPTION_SET_P.
+ * config/arc/arc.c (arc_override_options): Likewise.
+ * config/arm/arm.c (arm_option_override): Likewise.
+ * config/bfin/bfin.c (bfin_load_pic_reg): Likewise.
+ * config/c6x/c6x.c (c6x_option_override): Likewise.
+ * config/csky/csky.c: Likewise.
+ * config/darwin.c (darwin_override_options): Likewise.
+ * config/frv/frv.c (frv_option_override): Likewise.
+ * config/i386/djgpp.h: Likewise.
+ * config/i386/i386.c (ix86_stack_protect_guard): Likewise.
+ (ix86_max_noce_ifcvt_seq_cost): Likewise.
+ * config/ia64/ia64.c (ia64_option_override): Likewise.
+ (ia64_override_options_after_change): Likewise.
+ * config/m32c/m32c.c (m32c_option_override): Likewise.
+ * config/m32r/m32r.c (m32r_init): Likewise.
+ * config/m68k/m68k.c (m68k_option_override): Likewise.
+ * config/microblaze/microblaze.c (microblaze_option_override): Likewise.
+ * config/mips/mips.c (mips_option_override): Likewise.
+ * config/nios2/nios2.c (nios2_option_override): Likewise.
+ * config/nvptx/nvptx.c (nvptx_option_override): Likewise.
+ * config/pa/pa.c (pa_option_override): Likewise.
+ * config/riscv/riscv.c (riscv_option_override): Likewise.
+ * config/rs6000/aix71.h: Likewise.
+ * config/rs6000/aix72.h: Likewise.
+ * config/rs6000/aix73.h: Likewise.
+ * config/rs6000/rs6000.c (darwin_rs6000_override_options): Likewise.
+ (rs6000_override_options_after_change): Likewise.
+ (rs6000_linux64_override_options): Likewise.
+ (glibc_supports_ieee_128bit): Likewise.
+ (rs6000_option_override_internal): Likewise.
+ (rs6000_file_start): Likewise.
+ (rs6000_darwin_file_start): Likewise.
+ * config/rs6000/rtems.h: Likewise.
+ * config/rs6000/sysv4.h: Likewise.
+ * config/rs6000/vxworks.h (SUB3TARGET_OVERRIDE_OPTIONS): Likewise.
+ * config/s390/s390.c (s390_option_override): Likewise.
+ * config/sh/linux.h: Likewise.
+ * config/sh/netbsd-elf.h (while): Likewise.
+ * config/sh/sh.c (sh_option_override): Likewise.
+ * config/sol2.c (solaris_override_options): Likewise.
+ * config/sparc/sparc.c (sparc_option_override): Likewise.
+ * config/tilegx/tilegx.c (tilegx_option_override): Likewise.
+ * config/visium/visium.c (visium_option_override): Likewise.
+ * config/vxworks.c (vxworks_override_options): Likewise.
+ * lto-opts.c (lto_write_options): Likewise.
+ * omp-expand.c (expand_omp_simd): Likewise.
+ * omp-general.c (omp_max_vf): Likewise.
+ * omp-offload.c (oacc_xform_loop): Likewise.
+ * opts.h (OPTION_SET_P): Likewise.
+ * targhooks.c (default_max_noce_ifcvt_seq_cost): Likewise.
+ * toplev.c (process_options): Likewise.
+ * tree-predcom.c: Likewise.
+ * tree-sra.c (analyze_all_variable_accesses): Likewise.
+
+2021-10-08 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102464
+ * config/i386/i386.c (ix86_optab_supported_p):
+ Return true for HFmode.
+ * match.pd: Simplify (_Float16) ceil ((double) x) to
+ __builtin_ceilf16 (a) when a is _Float16 type and
+ direct_internal_fn_supported_p.
+
+2021-10-08 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102494
+ * config/i386/i386-expand.c (emit_reduc_half): Hanlde V4HImode.
+ * config/i386/mmx.md (reduc_plus_scal_v4hi): New.
+ (reduc_<code>_scal_v4hi): New.
+
+2021-10-08 liuhongt <hongtao.liu@intel.com>
+
+ * common.opt (ftree-vectorize): Add Var(flag_tree_vectorize).
+ * doc/invoke.texi (Options That Control Optimization): Update
+ documents.
+ * opts.c (default_options_table): Enable auto-vectorization at
+ O2 with very-cheap cost model.
+ (finish_options): Use cheap cost model for
+ explicit -ftree{,-loop}-vectorize.
+
+2021-10-07 Indu Bhagat <indu.bhagat@oracle.com>
+
+ * ctfc.c (ctfc_delete_container): Free hash table contents.
+
+2021-10-07 Indu Bhagat <indu.bhagat@oracle.com>
+
+ * toplev.c (process_options): Do not warn for GNU GIMPLE.
+
+2021-10-07 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ * tree-object-size.c (addr_object_size,
+ compute_builtin_object_size): Drop PDECL and POFF arguments.
+ (addr_object_size): Adjust calls.
+ * tree-object-size.h (compute_builtin_object_size): Drop PDECL
+ and POFF arguments.
+
+2021-10-07 Roger Sayle <roger@nextmovesoftware.com>
+
+ * rtl.def (SMUL_HIGHPART, UMUL_HIGHPART): New RTX codes for
+ representing signed and unsigned high-part multiplication resp.
+ * simplify-rtx.c (simplify_binary_operation_1) [SMUL_HIGHPART,
+ UMUL_HIGHPART]: Simplify high-part multiplications by zero.
+ [SS_PLUS, US_PLUS, SS_MINUS, US_MINUS, SS_MULT, US_MULT,
+ SS_DIV, US_DIV]: Similar simplifications for saturating
+ arithmetic.
+ (simplify_const_binary_operation) [SS_PLUS, US_PLUS, SS_MINUS,
+ US_MINUS, SS_MULT, US_MULT, SMUL_HIGHPART, UMUL_HIGHPART]:
+ Implement compile-time evaluation for constant operands.
+ * dwarf2out.c (mem_loc_descriptor): Skip SMUL_HIGHPART and
+ UMUL_HIGHPART.
+ * doc/rtl.texi (smul_highpart, umul_highpart): Document RTX codes.
+ * doc/md.texi (smul@var{m}3_highpart, umul@var{m3}_highpart):
+ Mention the new smul_highpart and umul_highpart RTX codes.
+ * doc/invoke.texi: Silence @xref "compilation" warnings.
+
+2021-10-07 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/102388
+ * ipa-prop.c (ipa_edge_args_sum_t::duplicate): Also handle the
+ case when the source reference description corresponds to a
+ referance taken in a function src->caller is inlined to.
+
+2021-10-07 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/102581
+ * ipa-modref-tree.h (modref_access_node::contains_p): Handle offsets
+ better.
+ (modref_access_node::try_merge_with): Add sanity check that there
+ are no redundant entries in the list.
+
+2021-10-07 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102608
+ * tree-ssa-sccvn.c (visit_stmt): Drop .DEFERRED_INIT to
+ varying.
+
+2021-10-07 Martin Liska <mliska@suse.cz>
+
+ * toplev.c (toplev::main): Make
+ save_opt_decoded_options a pointer type
+ * toplev.h: Likewise.
+
+2021-10-07 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/gcn-valu.md (gather<mode>_insn_2offsets<exec>): Apply
+ HAVE_GCN_ASM_GLOBAL_LOAD_FIXED.
+ (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
+
+2021-10-07 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/gcn-hsa.h (SRAMOPT): Include the whole option string.
+ Adjust for new -msram-ecc=any behaviour.
+ (ASM_SPEC): Adjust -mxnack and -msram-ecc usage.
+ * config/gcn/gcn.c (output_file_start): Implement -msram-ecc=any.
+ * config/gcn/mkoffload.c (EF_AMDGPU_XNACK): Rename to ...
+ (EF_AMDGPU_XNACK_V3): ... this.
+ (EF_AMDGPU_SRAM_ECC): Rename to ...
+ (EF_AMDGPU_SRAM_ECC_V3): ... this.
+ (EF_AMDGPU_FEATURE_XNACK_V4): New.
+ (EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4): New.
+ (EF_AMDGPU_FEATURE_XNACK_ANY_V4): New.
+ (EF_AMDGPU_FEATURE_XNACK_OFF_V4): New.
+ (EF_AMDGPU_FEATURE_XNACK_ON_V4): New.
+ (EF_AMDGPU_FEATURE_SRAMECC_V4): New.
+ (EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4): New.
+ (EF_AMDGPU_FEATURE_SRAMECC_ANY_V4): New.
+ (EF_AMDGPU_FEATURE_SRAMECC_OFF_V4): New.
+ (EF_AMDGPU_FEATURE_SRAMECC_ON_V4): New.
+ (SET_XNACK_ON): New.
+ (SET_XNACK_OFF): New.
+ (TEST_XNACK): New.
+ (SET_SRAM_ECC_ON): New.
+ (SET_SRAM_ECC_ANY): New.
+ (SET_SRAM_ECC_OFF): New.
+ (TEST_SRAM_ECC_ANY): New.
+ (TEST_SRAM_ECC_ON): New.
+ (main): Implement HSACOv4 and -msram-ecc=any.
+
+2021-10-07 Andrew Stubbs <ams@codesourcery.com>
+
+ * config.in: Regenerate.
+ * config/gcn/gcn-hsa.h (X_FIJI): New macro.
+ (X_900): New macro.
+ (X_906): New macro.
+ (X_908): New macro.
+ (A_FIJI): Rename to ...
+ (S_FIJI): ... this.
+ (A_900): Rename to ...
+ (S_900): ... this.
+ (A_906): Rename to ...
+ (S_906): ... this.
+ (A_908): Rename to ...
+ (S_908): ... this.
+ (SRAMOPT): New macro.
+ (ASM_SPEC): Adjust xnack option usage.
+ * config/gcn/gcn.c (output_file_start): Adjust amdgcn_target usage.
+ * configure: Regenerate.
+ * configure.ac: Detect LLVM assembler dialect.
+
+2021-10-07 Richard Biener <rguenther@suse.de>
+
+ * tree-pretty-print.c (dump_generic_node): Do not elide
+ printing '&' when dumping with -gimple.
+
+2021-10-06 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-cache.cc (non_null_ref::adjust_range): Call new
+ intersect routine.
+ * gimple-range-fold.cc (adjust_pointer_diff_expr): Ditto.
+ (adjust_imagpart_expr): Ditto.
+ * value-range.cc (irange::irange_intersect): Call new routine if
+ RHS is a single pair.
+ (irange::intersect): New wide_int version.
+ * value-range.h (class irange): New prototype.
+
+2021-10-06 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-edge.cc (gimple_outgoing_range::gimple_outgoing_range):
+ Add parameter to limit size when recognizing switches.
+ (gimple_outgoing_range::edge_range_p): Check size limit.
+ * gimple-range-edge.h (gimple_outgoing_range): Add size field.
+ * gimple-range-gori.cc (gori_map::calculate_gori): Ignore switches
+ that exceed the size limit.
+ (gori_compute::gori_compute): Add initializer.
+ * params.opt (evrp-switch-limit): New.
+ * doc/invoke.texi: Update docs.
+
+2021-10-06 Andrew MacLeod <amacleod@redhat.com>
+
+ * value-range.h (irange::set_varying): Use TYPE_MIN_VALUE and
+ TYPE_MAX_VALUE instead of creating new trees when possible.
+
+2021-10-06 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-cache.cc (non_null_ref::adjust_range): Check for
+ zero and non-zero more efficently.
+
+2021-10-06 Richard Biener <rguenther@suse.de>
+
+ PR c/102605
+ * dumpfile.h (TDF_GIMPLE_VAL): New.
+ (dump_flag): Re-order and adjust TDF_* flags. Make
+ the enum uint32_t. Use std::underlying_type in the
+ operator overloads.
+ (optgroup_flag): Likewise for the operator overloads.
+ * tree-pretty-print.c (dump_generic_node): Wrap ADDR_EXPR
+ in _Literal if TDF_GIMPLE_VAL.
+ * gimple-pretty-print.c (dump_gimple_assign): Add
+ TDF_GIMPLE_VAL to flags when dumping operands where only
+ is_gimple_val are allowed.
+ (dump_gimple_cond): Likewise.
+
+2021-10-06 prathamesh.kulkarni <prathamesh.kulkarni@linaro.org>
+
+ * gimple-isel.cc (gimple_expand_vec_cond_expr): Remove redundant if
+ condition.
+
+2021-10-05 qing zhao <qing.zhao@oracle.com>
+
+ PR middle-end/102359
+ * gimplify.c (gimplify_decl_expr): Not add initialization for an
+ auto variable when it has been initialized by frontend.
+
+2021-10-05 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadupdate.c (jt_path_registry::cancel_invalid_paths):
+ Loosen restrictions
+
+2021-10-05 Jan-Benedict Glaw <jbglaw@lug-owl.de>
+
+ * common/config/avr/avr-common.c (avr_handle_option): Mark
+ argument as ATTRIBUTE_UNUSED.
+
+2021-10-05 Jan-Benedict Glaw <jbglaw@lug-owl.de>
+
+ * config/lm32/uclinux-elf.h (LINK_GCC_C_SEQUENCE_SPEC):
+ Undefine before redefinition.
+
+2021-10-05 Richard Biener <rguenther@suse.de>
+
+ * toplev.c (no_backend): Remove global var.
+ (process_options): Pass in no_backend, move post_options
+ langhook call to toplev::main.
+ (do_compile): Pass in no_backend, move process_options call
+ to toplev::main.
+ (toplev::run_self_tests): Check no_backend at the caller.
+ (toplev::main): Call post_options and process_options
+ split out from do_compile, do self-tests only if
+ no_backend is initialized.
+
+2021-10-05 Richard Biener <rguenther@suse.de>
+
+ * tree-cfg.c (dump_function_to_file): Dump the UID of the
+ function as part of the name when requested.
+ * tree-pretty-print.c (dump_function_name): Dump the UID when
+ requested and the langhook produced the actual name.
+
+2021-10-05 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/102587
+ PR middle-end/102285
+ * internal-fn.c (expand_DEFERRED_INIT): Fall back to
+ zero-initialization as last resort, use the constant
+ size as given by the DEFERRED_INIT argument to build
+ the initializer.
+
+2021-10-04 Marek Polacek <polacek@redhat.com>
+
+ PR c++/97573
+ * doc/invoke.texi: Document -Warray-compare.
+
+2021-10-04 Richard Biener <rguenther@suse.de>
+
+ * gimplify.c (is_var_need_auto_init): DECL_HARD_REGISTER
+ variables are not to be initialized.
+
+2021-10-04 Richard Biener <rguenther@suse.de>
+
+ * expr.h (non_mem_decl_p): Declare.
+ (mem_ref_refers_to_non_mem_p): Likewise.
+ * expr.c (non_mem_decl_p): Export.
+ (mem_ref_refers_to_non_mem_p): Likewise.
+ * internal-fn.c (expand_DEFERRED_INIT): Do not expand the LHS
+ but check the base with mem_ref_refers_to_non_mem_p
+ and non_mem_decl_p.
+
+2021-10-04 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102570
+ * tree-ssa-sccvn.h (vn_reference_op_struct): Document
+ we are using clique for the internal function code.
+ * tree-ssa-sccvn.c (vn_reference_op_eq): Compare the
+ internal function code.
+ (print_vn_reference_ops): Print the internal function code.
+ (vn_reference_op_compute_hash): Hash it.
+ (copy_reference_ops_from_call): Record it.
+ (visit_stmt): Remove the restriction around internal function
+ calls.
+ (fully_constant_vn_reference_p): Use fold_const_call and handle
+ internal functions.
+ (vn_reference_eq): Compare call return types.
+ * tree-ssa-pre.c (create_expression_by_pieces): Handle
+ generating calls to internal functions.
+ (compute_avail): Remove the restriction around internal function
+ calls.
+
+2021-10-04 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/102560
+ * gimple-ssa-warn-alloca.c (alloca_call_type): Remove static
+ marker for invalid_range.
+
+2021-10-04 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/102587
+ * internal-fn.c (expand_DEFERRED_INIT): Guard register
+ initialization path an avoid initializing VLA registers
+ with it.
+
+2021-10-04 Eric Botcazou <ebotcazou@adacore.com>
+
+ * config/rs6000/vxworks.h (TARGET_INIT_LIBFUNCS): Delete.
+
+2021-10-03 Martin Liska <mliska@suse.cz>
+
+ * toplev.c (toplev::main): Check opt_index if it is a part
+ of cl_options.
+
+2021-10-02 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/102563
+ * range-op.cc (operator_lshift::op1_range): Do not clobber
+ range.
+
+2021-10-02 Martin Liska <mliska@suse.cz>
+
+ * toplev.c (toplev::main): save_decoded_options[0] is program
+ name and so it should be skipped.
+
+2021-10-01 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/102546
+ * range-op.cc (operator_lshift::op1_range): Teach range-ops that
+ X << Y is non-zero implies X is also non-zero.
+
+2021-10-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/aarch64/aarch64-cores.def (AARCH64_CORE): New
+ Cortex-X2 core.
+ * config/aarch64/aarch64-tune.md: Regenerate.
+ * doc/invoke.texi: Update docs.
+
+2021-10-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/aarch64/aarch64-cores.def (AARCH64_CORE): New
+ Cortex-A710 core.
+ * config/aarch64/aarch64-tune.md: Regenerate.
+ * doc/invoke.texi: Update docs.
+
+2021-10-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/aarch64/aarch64-cores.def (AARCH64_CORE): New
+ Cortex-A510 core.
+ * config/aarch64/aarch64-tune.md: Regenerate.
+ * doc/invoke.texi: Update docs.
+
+2021-10-01 Martin Sebor <msebor@redhat.com>
+
+ PR c/102103
+ * doc/invoke.texi (-Waddress): Update.
+ * gengtype.c (write_types): Avoid -Waddress.
+ * poly-int.h (POLY_SET_COEFF): Avoid using null.
+
+2021-10-01 John David Anglin <danglin@gcc.gnu.org>
+
+ PR debug/102373
+ * config/pa/pa.c (pa_option_override): Default to dwarf version 4
+ on hppa64-hpux.
+
+2021-10-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/aarch64/aarch64.h (AARCH64_FL_V9): Update value.
+
+2021-10-01 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::compute_ranges): Use
+ get_path_oracle.
+ * gimple-range-path.h (class path_range_query): Remove shadowed
+ m_oracle field.
+ (path_range_query::get_path_oracle): New.
+
+2021-10-01 Jakub Jelinek <jakub@redhat.com>
+ Richard Biener <rguenther@suse.de>
+
+ PR sanitizer/102515
+ * doc/invoke.texi (-fsanitize=integer-divide-by-zero): Remove
+ INT_MIN / -1 division detection from here ...
+ (-fsanitize=signed-integer-overflow): ... and add it here.
+
+2021-10-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Added
+ armv9-a.
+ * config/aarch64/aarch64.h (AARCH64_FL_V9): New.
+ (AARCH64_FL_FOR_ARCH9): New flags for Armv9-A.
+ (AARCH64_ISA_V9): New ISA flag.
+ * doc/invoke.texi: Update docs.
+
+2021-10-01 Martin Liska <mliska@suse.cz>
+
+ * toplev.c (toplev::main): Save decoded optimization options.
+ * toplev.h (save_opt_decoded_options): New.
+ * doc/extend.texi: Be more clear about optimize and target
+ attributes.
+
+2021-10-01 Eric Botcazou <ebotcazou@adacore.com>
+
+ * explow.c: Include langhooks.h.
+ (set_stack_check_libfunc): Build a proper function type.
+
+2021-10-01 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR c++/64697
+ * config/i386/i386.c (legitimate_pic_address_disp_p): For PE-COFF do
+ not return true for external weak function symbols in medium model.
+
+2021-10-01 Jakub Jelinek <jakub@redhat.com>
+
+ * tree.h (OMP_CLAUSE_ORDER_REPRODUCIBLE): Define.
+ * tree-pretty-print.c (dump_omp_clause) <case OMP_CLAUSE_ORDER>: Print
+ reproducible: for OMP_CLAUSE_ORDER_REPRODUCIBLE.
+ * omp-general.c (omp_extract_for_data): If OMP_CLAUSE_ORDER is seen
+ without OMP_CLAUSE_ORDER_UNCONSTRAINED, overwrite sched_kind to
+ OMP_CLAUSE_SCHEDULE_STATIC.
+
+2021-10-01 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/102518
+ * tree-inline.c (setup_one_parameter): Avoid substituting
+ an invariant into contexts where a GIMPLE register is not valid.
+
+2021-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/arm/arm-cpus.in: Add Cortex-R52+ CPU.
+ * config/arm/arm-tables.opt: Regenerate.
+ * config/arm/arm-tune.md: Regenerate.
+ * doc/invoke.texi: Update docs.
+
+2021-09-30 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/89954
+ * config/i386/i386.md
+ (sign_extend:WIDE (any_logic:NARROW (memory, immediate)) splitters):
+ New splitters.
+
+2021-09-30 Tobias Burnus <tobias@codesourcery.com>
+
+ * omp-low.c (omp_runtime_api_call): Add omp_aligned_{,c}alloc and
+ omp_{c,re}alloc, fix omp_alloc/omp_free.
+
+2021-09-30 Martin Liska <mliska@suse.cz>
+
+ * defaults.h (ASM_OUTPUT_ASCII): Do not hide global variable
+ asm_out_file and stream directly to MYFILE.
+
+2021-09-30 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-data-refs.c (vect_update_misalignment_for_peel):
+ Restore and fix condition under which we apply npeel to
+ the DRs misalignment value.
+
+2021-09-30 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-data-refs.c (vect_update_misalignment_for_peel):
+ Fix npeel check for variable amount of peeling.
+
+2021-09-30 Aldy Hernandez <aldyh@redhat.com>
+
+ * lto-wrapper.c (run_gcc): Plug snprintf overflow.
+
+2021-09-30 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range.cc (gimple_ranger::debug): New.
+ * gimple-range.h (class gimple_ranger): Add debug.
+
+2021-09-30 Aldy Hernandez <aldyh@redhat.com>
+
+ PR middle-end/102519
+ * tree-vrp.c (hybrid_threader::~hybrid_threader): Free m_query.
+
+2021-09-29 Indu Bhagat <indu.bhagat@oracle.com>
+
+ PR debug/102507
+ * btfout.c (GTY): Add GTY (()) albeit for cosmetic only purpose.
+ (btf_finalize): Empty the hash_map btf_var_ids.
+
+2021-09-29 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-vrp.c (thread_through_all_blocks): Return bool.
+ (execute_vrp_threader): Return TODO_* flags.
+ (pass_data_vrp_threader): Set todo_flags_finish to 0.
+
+2021-09-29 Aldy Hernandez <aldyh@redhat.com>
+
+ * timevar.def (TV_TREE_VRP_THREADER): New.
+ * tree-vrp.c: Use TV_TREE_VRP_THREADER for VRP threader pass.
+
+2021-09-29 David Faust <david.faust@oracle.com>
+
+ * config.gcc (bpf-*-*): Do not overwrite extra_headers.
+
+2021-09-29 Jonathan Wright <jonathan.wright@arm.com>
+
+ * config/aarch64/aarch64-builtins.c (TYPES_BINOP_PPU): Define
+ new type qualifier enum.
+ (TYPES_TERNOP_SSSU): Likewise.
+ (TYPES_TERNOP_PPPU): Likewise.
+ * config/aarch64/aarch64-simd-builtins.def: Define PPU, SSU,
+ PPPU and SSSU builtin generator macros for qtbl1 and qtbx1
+ Neon builtins.
+ * config/aarch64/arm_neon.h (vqtbl1_p8): Use type-qualified
+ builtin and remove casts.
+ (vqtbl1_s8): Likewise.
+ (vqtbl1q_p8): Likewise.
+ (vqtbl1q_s8): Likewise.
+ (vqtbx1_s8): Likewise.
+ (vqtbx1_p8): Likewise.
+ (vqtbx1q_s8): Likewise.
+ (vqtbx1q_p8): Likewise.
+ (vtbl1_p8): Likewise.
+ (vtbl2_p8): Likewise.
+ (vtbx2_p8): Likewise.
+
+2021-09-29 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-data-refs.c (vect_dr_misalign_for_aligned_access):
+ New helper.
+ (vect_update_misalignment_for_peel): Use it to update
+ misaligned to the value necessary for an aligned access.
+ (vect_get_peeling_costs_all_drs): Likewise.
+ (vect_enhance_data_refs_alignment): Likewise.
+
+2021-09-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_expand_cpymem): Count number of
+ emitted operations and adjust heuristic for code size.
+
+2021-09-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_expand_setmem): Count number of
+ emitted operations and adjust heuristic for code size.
+
+2021-09-29 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/102504
+ * gimplify.c (gimplify_scan_omp_clauses): Use omp_check_private even
+ in OMP_SCOPE clauses, not just on worksharing construct clauses.
+
+2021-09-28 Geng Qi <gengqi@linux.alibaba.com>
+
+ * config/riscv/riscv.md (mulv<mode>4): Call gen_smul<mode>3_highpart.
+ (<u>mulditi3): Call <su>muldi3_highpart.
+ (<u>muldi3_highpart): Rename to <su>muldi3_highpart.
+ (<u>mulsidi3): Call <su>mulsi3_highpart.
+ (<u>mulsi3_highpart): Rename to <su>mulsi3_highpart.
+
+2021-09-28 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.h (DSYMUTIL_SPEC): Recognize D sources.
+
+2021-09-28 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/rs6000/darwin.h (FIXED_R13): Add for PPC64.
+ (FIRST_SAVED_GP_REGNO): Save from R13 even when it is one
+ of the fixed regs.
+
+2021-09-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64.h (AARCH64_FL_LS64): Define
+ (AARCH64_FL_V8_7): Likewise.
+ (AARCH64_FL_FOR_ARCH8_7): Likewise.
+ * config/aarch64/aarch64-arches.def (armv8.7-a): Define.
+ * config/aarch64/aarch64-option-extensions.def (ls64): Define.
+ * doc/invoke.texi: Document the above.
+
+2021-09-28 Aldy Hernandez <aldyh@redhat.com>
+
+ * dbgcnt.c (dbg_cnt_counter): New.
+ * dbgcnt.h (dbg_cnt_counter): New.
+ * dumpfile.c (dump_options): Add entry for TDF_THREADING.
+ * dumpfile.h (enum dump_flag): Add TDF_THREADING.
+ * gimple-range-path.cc (DEBUG_SOLVER): Use TDF_THREADING.
+ * tree-ssa-threadupdate.c (dump_jump_thread_path): Dump out
+ debug counter.
+
+2021-09-28 Aldy Hernandez <aldyh@redhat.com>
+
+ * cfgcleanup.c (pass_jump::execute): Check
+ flag_expensive_optimizations.
+ (pass_jump_after_combine::gate): Same.
+ * doc/invoke.texi (-fthread-jumps): Enable for -O1.
+ * opts.c (default_options_table): Enable -fthread-jumps at -O1.
+ * tree-ssa-threadupdate.c
+ (fwd_jt_path_registry::remove_jump_threads_including): Bail unless
+ flag_thread_jumps.
+
+2021-09-28 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * tree-ssa-reassoc.c (biased_names): New global.
+ (propagate_bias_p): New function.
+ (loop_carried_phi): Remove.
+ (propagate_rank): Propagate bias along single uses.
+ (get_rank): Update biased_names when needed.
+
+2021-09-28 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * passes.def (pass_reassoc): Rename parameter to early_p.
+ * tree-ssa-reassoc.c (reassoc_bias_loop_carried_phi_ranks_p):
+ New variable.
+ (phi_rank): Don't bias loop-carried phi ranks
+ before vectorization pass.
+ (execute_reassoc): Add bias_loop_carried_phi_ranks_p parameter.
+ (pass_reassoc::pass_reassoc): Add bias_loop_carried_phi_ranks_p
+ initializer.
+ (pass_reassoc::set_param): Set bias_loop_carried_phi_ranks_p
+ value.
+ (pass_reassoc::execute): Pass bias_loop_carried_phi_ranks_p to
+ execute_reassoc.
+ (pass_reassoc::bias_loop_carried_phi_ranks_p): New member.
+
+2021-09-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/102498
+ * config/i386/i386.c (standard_80387_constant_p): Don't recognize
+ special 80387 instruction XFmode constants if flag_rounding_math.
+
+2021-09-28 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/100112
+ * tree-ssa-sccvn.c (visit_reference_op_load): Record the
+ referece into the hashtable twice in case last_vuse is
+ different from the original vuse on the stmt.
+
+2021-09-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/102492
+ * gimplify.c (gimplify_adjust_omp_clauses_1): Don't call the
+ omp_finish_clause langhook on implicitly added OMP_CLAUSE_PRIVATE
+ clauses on SIMD constructs.
+
+2021-09-28 Aldy Hernandez <aldyh@redhat.com>
+
+ PR tree-optimization/102511
+ * gimple-range-path.cc (path_range_query::range_on_path_entry):
+ Return VARYING when nothing found.
+
+2021-09-28 Hongyu Wang <hongyu.wang@intel.com>
+
+ PR target/102230
+ * config/i386/i386.h (VALID_AVX512FP16_REG_MODE): Add
+ V2HF mode check.
+ (VALID_SSE2_REG_VHF_MODE): Add V4HFmode and V2HFmode.
+ (VALID_MMX_REG_MODE): Add V4HFmode.
+ (SSE_REG_MODE_P): Replace VALID_AVX512FP16_REG_MODE with
+ vector mode condition.
+ * config/i386/i386.c (classify_argument): Parse V4HF/V2HF
+ via sse regs.
+ (function_arg_32): Add V4HFmode.
+ (function_arg_advance_32): Likewise.
+ * config/i386/i386.md (mode): Add V4HF/V2HF.
+ (MODE_SIZE): Likewise.
+ * config/i386/mmx.md (MMXMODE): Add V4HF mode.
+ (V_32): Add V2HF mode.
+ (VHF_32_64): New mode iterator.
+ (*mov<mode>_internal): Adjust sse alternatives to support
+ V4HF mode move.
+ (*mov<mode>_internal): Adjust sse alternatives to support
+ V2HF mode move.
+ (<insn><mode>3): New define_insn for add/sub/mul/div.
+
+2021-09-28 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (pass_thread_jumps::gate): Check
+ flag_thread_jumps.
+ (pass_early_thread_jumps::gate): Same.
+ * tree-ssa-threadedge.c (jump_threader::thread_outgoing_edges):
+ Return if !flag_thread_jumps.
+ * tree-ssa-threadupdate.c
+ (jt_path_registry::register_jump_thread): Assert that
+ flag_thread_jumps is true.
+
+2021-09-28 liuhongt <hongtao.liu@intel.com>
+
+ * simplify-rtx.c
+ (simplify_context::simplify_binary_operation_1): Relax
+ condition of simplifying (vec_concat:M (vec_select op0
+ index0)(vec_select op1 index1)) to allow different modes
+ between op0 and M, but have same inner mode.
+
+2021-09-28 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/i386-expand.c (emit_reduc_half): Handle
+ V8HF/V16HF/V32HFmode.
+ * config/i386/sse.md (REDUC_SSE_PLUS_MODE): Add V8HF.
+ (REDUC_SSE_SMINMAX_MODE): Ditto.
+ (REDUC_PLUS_MODE): Add V16HF and V32HF.
+ (REDUC_SMINMAX_MODE): Ditto.
+
+2021-09-27 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc
+ (path_range_query::precompute_ranges_in_block): Rename to...
+ (path_range_query::compute_ranges_in_block): ...this.
+ (path_range_query::precompute_ranges): Rename to...
+ (path_range_query::compute_ranges): ...this.
+ (path_range_query::precompute_relations): Rename to...
+ (path_range_query::compute_relations): ...this.
+ (path_range_query::precompute_phi_relations): Rename to...
+ (path_range_query::compute_phi_relations): ...this.
+ * gimple-range-path.h: Rename precompute* to compute*.
+ * tree-ssa-threadbackward.c
+ (back_threader::find_taken_edge_switch): Same.
+ (back_threader::find_taken_edge_cond): Same.
+ * tree-ssa-threadedge.c
+ (hybrid_jt_simplifier::compute_ranges_from_state): Same.
+ (hybrid_jt_state::register_equivs_stmt): Inline...
+ * tree-ssa-threadedge.h: ...here.
+
+2021-09-27 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-vrp.c (lhs_of_dominating_assert): Remove.
+ (class vrp_jt_state): Remove.
+ (class vrp_jt_simplifier): Remove.
+ (vrp_jt_simplifier::simplify): Remove.
+ (class vrp_jump_threader): Remove.
+ (vrp_jump_threader::vrp_jump_threader): Remove.
+ (vrp_jump_threader::~vrp_jump_threader): Remove.
+ (vrp_jump_threader::before_dom_children): Remove.
+ (vrp_jump_threader::after_dom_children): Remove.
+
+2021-09-27 Aldy Hernandez <aldyh@redhat.com>
+
+ * passes.def (pass_vrp_threader): New.
+ * tree-pass.h (make_pass_vrp_threader): Add make_pass_vrp_threader.
+ * tree-ssa-threadedge.c (hybrid_jt_state::register_equivs_stmt): New.
+ (hybrid_jt_simplifier::hybrid_jt_simplifier): New.
+ (hybrid_jt_simplifier::simplify): New.
+ (hybrid_jt_simplifier::compute_ranges_from_state): New.
+ * tree-ssa-threadedge.h (class hybrid_jt_state): New.
+ (class hybrid_jt_simplifier): New.
+ * tree-vrp.c (execute_vrp): Remove ASSERT_EXPR based jump
+ threader.
+ (class hybrid_threader): New.
+ (hybrid_threader::hybrid_threader): New.
+ (hybrid_threader::~hybrid_threader): New.
+ (hybrid_threader::before_dom_children): New.
+ (hybrid_threader::after_dom_children): New.
+ (execute_vrp_threader): New.
+ (class pass_vrp_threader): New.
+ (make_pass_vrp_threader): New.
+
+2021-09-27 Martin Liska <mliska@suse.cz>
+
+ * output.h (enum section_flag): New.
+ (SECTION_FORGET): Remove.
+ (SECTION_ENTSIZE): Make it (1UL << 8) - 1.
+ (SECTION_STYLE_MASK): Define it based on other enum
+ values.
+ * varasm.c (switch_to_section): Remove unused handling of
+ SECTION_FORGET.
+
+2021-09-27 Martin Liska <mliska@suse.cz>
+
+ * common.opt: Add new variable flag_default_complex_method.
+ * opts.c (finish_options): Handle flags related to
+ x_flag_complex_method.
+ * toplev.c (process_options): Remove option handling related
+ to flag_complex_method.
+
+2021-09-27 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/102450
+ * gimple-fold.c (gimple_fold_builtin_memory_op): Avoid using
+ type_for_size, instead use int_mode_for_size.
+
+2021-09-27 Andrew Pinski <apinski@marvell.com>
+
+ PR c/94726
+ * gimplify.c (gimplify_save_expr): Return early
+ if the type of val is error_mark_node.
+
+2021-09-27 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssanames.c (ssa_name_has_boolean_range): Use
+ get_range_query.
+
+2021-09-27 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-ssa-evrp-analyze.h (class evrp_range_analyzer): Remove
+ vrp_visit_cond_stmt.
+ * tree-ssa-dom.c (cprop_operand): Convert to range_query API.
+ (cprop_into_stmt): Same.
+ (dom_opt_dom_walker::optimize_stmt): Same.
+
+2021-09-27 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/97351
+ PR tree-optimization/97352
+ PR tree-optimization/82426
+ * tree-vectorizer.h (dr_misalignment): Add vector type
+ argument.
+ (aligned_access_p): Likewise.
+ (known_alignment_for_access_p): Likewise.
+ (vect_supportable_dr_alignment): Likewise.
+ (vect_known_alignment_in_bytes): Likewise. Refactor.
+ (DR_MISALIGNMENT): Remove.
+ (vect_update_shared_vectype): Likewise.
+ * tree-vect-data-refs.c (dr_misalignment): Refactor, handle
+ a vector type with larger alignment requirement and apply
+ the negative step adjustment here.
+ (vect_calculate_target_alignment): Remove.
+ (vect_compute_data_ref_alignment): Get explicit vector type
+ argument, do not apply a negative step alignment adjustment
+ here.
+ (vect_slp_analyze_node_alignment): Re-analyze alignment
+ when we re-visit the DR with a bigger desired alignment but
+ keep more precise results from smaller alignments.
+ * tree-vect-slp.c (vect_update_shared_vectype): Remove.
+ (vect_slp_analyze_node_operations_1): Do not update the
+ shared vector type on stmts.
+ * tree-vect-stmts.c (vect_analyze_stmt): Push/pop the
+ vector type of an SLP node to the representative stmt-info.
+ (vect_transform_stmt): Likewise.
+
+2021-09-27 liuhongt <hongtao.liu@intel.com>
+
+ Revert:
+ 2021-09-09 liuhongt <hongtao.liu@intel.com>
+
+ PR target/101059
+ * config/i386/sse.md (reduc_plus_scal_<mode>): Split to ..
+ (reduc_plus_scal_v4sf): .. this, New define_expand.
+ (reduc_plus_scal_v2df): .. and this, New define_expand.
+
+2021-09-26 liuhongt <hongtao.liu@intel.com>
+
+ * doc/extend.texi (Half-Precision): Remove storage only
+ description for _Float16 w/o avx512fp16.
+
+2021-09-25 Dimitar Dimitrov <dimitar@dinux.eu>
+
+ * config/pru/constraints.md (Rrio): New constraint.
+ * config/pru/predicates.md (regio_operand): New predicate.
+ * config/pru/pru-pragma.c (pru_register_pragmas): Register
+ the __regio_symbol address space.
+ * config/pru/pru-protos.h (pru_symref2ioregno): Declaration.
+ * config/pru/pru.c (pru_symref2ioregno): New helper function.
+ (pru_legitimate_address_p): Remove.
+ (pru_addr_space_legitimate_address_p): Use the address space
+ aware hook variant.
+ (pru_nongeneric_pointer_addrspace): New helper function.
+ (pru_insert_attributes): New function to validate __regio_symbol
+ usage.
+ (TARGET_INSERT_ATTRIBUTES): New macro.
+ (TARGET_LEGITIMATE_ADDRESS_P): Remove.
+ (TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P): New macro.
+ * config/pru/pru.h (enum reg_class): Add REGIO_REGS class.
+ * config/pru/pru.md (*regio_readsi): New pattern to read I/O
+ registers.
+ (*regio_nozext_writesi): New pattern to write to I/O registers.
+ (*regio_zext_write_r30<EQS0:mode>): Ditto.
+ * doc/extend.texi: Document the new PRU Named Address Space.
+
+2021-09-24 Patrick Palka <ppalka@redhat.com>
+
+ PR c++/98216
+ PR c++/91292
+ * real.c (encode_ieee_double): Avoid unwanted sign extension.
+ (encode_ieee_quad): Likewise.
+
+2021-09-24 Vladimir Makarov <vmakarov@redhat.com>
+
+ PR rtl-optimization/102147
+ * ira-build.c (ira_conflict_vector_profitable_p): Make
+ profitability calculation independent of host compiler pointer and
+ IRA_INT_BITS sizes.
+
+2021-09-24 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::path_range_query):
+ Move debugging header...
+ (path_range_query::precompute_ranges): ...here.
+ (path_range_query::internal_range_of_expr): Do not call
+ range_on_path_entry if NAME is defined in the current block.
+
+2021-09-24 Richard Biener <rguenther@suse.de>
+
+ * cfghooks.c (verify_flow_info): Verify unallocated BB and
+ edge flags are not set.
+
+2021-09-24 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadupdate.c (jt_path_registry::cancel_invalid_paths):
+ New.
+ (jt_path_registry::register_jump_thread): Call
+ cancel_invalid_paths.
+ * tree-ssa-threadupdate.h (class jt_path_registry): Add
+ cancel_invalid_paths.
+
+2021-09-24 Feng Xue <fxue@os.amperecomputing.com>
+
+ PR tree-optimization/102400
+ * tree-ssa-sccvn.c (vn_reference_insert_pieces): Initialize
+ result_vdef to zero value.
+
+2021-09-24 Feng Xue <fxue@os.amperecomputing.com>
+
+ PR tree-optimization/102451
+ * tree-ssa-dse.c (delete_dead_or_redundant_call): Record bb of stmt
+ before removal.
+
+2021-09-24 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/sse.md (cond_<insn><mode>): Extend to support
+ vector HFmodes.
+ (cond_mul<mode>): Likewise.
+ (cond_div<mode>): Likewise.
+ (cond_<code><mode>): Likewise.
+ (cond_fma<mode>): Likewise.
+ (cond_fms<mode>): Likewise.
+ (cond_fnma<mode>): Likewise.
+ (cond_fnms<mode>): Likewise.
+
+2021-09-23 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/102463
+ * gimple-range-fold.cc (fold_using_range::relation_fold_and_or): If
+ there is no range-ops handler, don't look for a relation.
+
+2021-09-23 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-cache.cc (ranger_cache::ranger_cache): Take
+ non-executable_edge flag as parameter.
+ * gimple-range-cache.h (ranger_cache): Adjust prototype.
+ * gimple-range-gori.cc (gori_compute::gori_compute): Take
+ non-executable_edge flag as parameter.
+ (gori_compute::outgoing_edge_range_p): Check new flag.
+ * gimple-range-gori.h (gori_compute): Adjust prototype.
+ * gimple-range.cc (gimple_ranger::gimple_ranger): Create new flag.
+ (gimple_ranger::range_on_edge): Check new flag.
+ * gimple-range.h (gimple_ranger::non_executable_edge_flag): New.
+ * gimple-ssa-evrp.c (rvrp_folder): Pass ranger flag to simplifer.
+ (hybrid_folder::hybrid_folder): Set ranger non-executable flag value.
+ (hybrid_folder::fold_stmt): Set flag value in the simplifer.
+ * vr-values.c (simplify_using_ranges::set_and_propagate_unexecutable):
+ Use not_executable flag if provided inmstead of EDGE_EXECUTABLE.
+ (simplify_using_ranges::simplify_switch_using_ranges): Clear
+ EDGE_EXECUTABLE like it originally did.
+ (simplify_using_ranges::cleanup_edges_and_switches): Clear any
+ NON_EXECUTABLE flags.
+ (simplify_using_ranges::simplify_using_ranges): Adjust.
+ * vr-values.h (class simplify_using_ranges): Adjust.
+ (simplify_using_ranges::set_range_query): Add non-executable flag param.
+
+2021-09-23 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ PR target/102024
+ * config/rs6000/rs6000-call.c (rs6000_aggregate_candidate): Detect
+ zero-width bit fields and return indicator.
+ (rs6000_discover_homogeneous_aggregate): Diagnose when the
+ presence of a zero-width bit field changes parameter passing in
+ GCC 12.
+
+2021-09-23 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-fold.cc (fold_using_range::range_of_phi):
+ Remove dominator check.
+
+2021-09-23 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::precompute_relations):
+ Hoist edge calculations before using EDGE_SUCC.
+
+2021-09-23 Jonathan Wakely <jwakely@redhat.com>
+
+ * configure.ac: Fix --with-multilib-list description.
+ * configure: Regenerate.
+
+2021-09-23 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102448
+ * tree-vect-data-refs.c (vect_duplicate_ssa_name_ptr_info):
+ Clear alignment info copied from DR_PTR_INFO.
+
+2021-09-23 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/i386-expand.c (ix86_use_mask_cmp_p): Enable
+ HFmode mask_cmp.
+ * config/i386/sse.md (sseintvecmodelower): Add HF vector modes.
+ (<avx512>_store<mode>_mask): Extend to support HF vector modes.
+ (vec_cmp<mode><avx512fmaskmodelower>): Likewise.
+ (vcond_mask_<mode><avx512fmaskmodelower>): Likewise.
+ (vcond<mode><mode>): New expander.
+ (vcond<mode><sseintvecmodelower>): Likewise.
+ (vcond<sseintvecmodelower><mode>): Likewise.
+ (vcondu<mode><sseintvecmodelower>): Likewise.
+
+2021-09-23 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/sse.md (extend<ssePHmodelower><mode>2):
+ New expander.
+ (extendv4hf<mode>2): Likewise.
+ (extendv2hfv2df2): Likewise.
+ (trunc<mode><ssePHmodelower>2): Likewise.
+ (avx512fp16_vcvt<castmode>2ph_<mode>): Rename to ...
+ (trunc<mode>v4hf2): ... this, and drop constraints.
+ (avx512fp16_vcvtpd2ph_v2df): Rename to ...
+ (truncv2dfv2hf2): ... this, and likewise.
+
+2021-09-23 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/sse.md (float<floatunssuffix><mode><ssePHmodelower>2):
+ New expander.
+ (avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>):
+ Rename to ...
+ (float<floatunssuffix><mode>v4hf2): ... this, and drop constraints.
+ (avx512fp16_vcvt<floatsuffix>qq2ph_v2di): Rename to ...
+ (float<floatunssuffix>v2div2hf2): ... this, and likewise.
+
+2021-09-23 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/i386.md (fix<fixunssuffix>_trunchf<mode>2): New expander.
+ (fixuns_trunchfhi2): Likewise.
+ (*fixuns_trunchfsi2zext): New define_insn.
+ * config/i386/sse.md (ssePHmodelower): New mode_attr.
+ (fix<fixunssuffix>_trunc<ssePHmodelower><mode>2):
+ New expander for same element vector fix_truncate.
+ (fix<fixunssuffix>_trunc<ssePHmodelower><mode>2):
+ Likewise for V4HF to V4SI/V4DI fix_truncate.
+ (fix<fixunssuffix>_truncv2hfv2di2):
+ Likeise for V2HF to V2DI fix_truncate.
+
+2021-09-23 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/i386.md (<code>hf3): New expander.
+
+2021-09-23 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/sse.md (FMAMODEM): extend to handle FP16.
+ (VFH_SF_AVX512VL): Extend to handle HFmode.
+ (VF_SF_AVX512VL): Deleted.
+
+2021-09-23 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/i386.md (rinthf2): New expander.
+ (nearbyinthf2): New expander.
+
+2021-09-23 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-dom.c (class dom_jump_threader_simplifier): Rename...
+ (class dom_jt_state): ...this and provide virtual overrides.
+ (dom_jt_state::register_equiv): New.
+ (class dom_jt_simplifier): Rename from
+ dom_jump_threader_simplifier.
+ (dom_jump_threader_simplifier::simplify): Rename...
+ (dom_jt_simplifier::simplify): ...to this.
+ (pass_dominator::execute): Use dom_jt_simplifier and
+ dom_jt_state.
+ * tree-ssa-threadedge.c (jump_threader::jump_threader):
+ Clean-up.
+ (jt_state::register_equivs_stmt): Abstract out...
+ (jump_threader::record_temporary_equivalences_from_stmts_at_dest):
+ ...from here.
+ (jump_threader::thread_around_empty_blocks): Update state.
+ (jump_threader::thread_through_normal_block): Same.
+ (jt_state::jt_state): Remove.
+ (jt_state::push): Remove pass specific bits. Keep block vector
+ updated.
+ (jt_state::append_path): New.
+ (jt_state::pop): Remove pass specific bits.
+ (jt_state::register_equiv): Same.
+ (jt_state::record_ranges_from_stmt): Same.
+ (jt_state::register_equivs_on_edge): Same. Rename...
+ (jt_state::register_equivs_edge): ...to this.
+ (jt_state::dump): New.
+ (jt_state::debug): New.
+ (jump_threader_simplifier::simplify): Remove.
+ (jt_state::get_path): New.
+ * tree-ssa-threadedge.h (class jt_simplifier): Make into a base
+ class. Expose common functionality as virtual methods.
+ (class jump_threader_simplifier): Same. Rename...
+ (class jt_simplifier): ...to this.
+ * tree-vrp.c (class vrp_jump_threader_simplifier): Rename...
+ (class vrp_jt_simplifier): ...to this. Provide pass specific
+ overrides.
+ (class vrp_jt_state): New.
+ (vrp_jump_threader_simplifier::simplify): Rename...
+ (vrp_jt_simplifier::simplify): ...to this. Inline code from
+ what used to be the base class.
+ (vrp_jump_threader::vrp_jump_threader): Use vrp_jt_state and
+ vrp_jt_simplifier.
+
+2021-09-22 Tobias Burnus <tobias@codesourcery.com>
+
+ PR fortran/55534
+ * doc/invoke.texi (-Wno-missing-include-dirs.): Document Fortran
+ behavior.
+
+2021-09-22 Roger Sayle <roger@nextmovesoftware.com>
+ Richard Biener <rguenther@suse.de>
+
+ * match.pd (negation simplifications): Implement some negation
+ folding transformations from fold-const.c's fold_negate_expr.
+ * tree-ssa-sccvn.c (vn_nary_build_or_lookup_1): Add a SIMPLIFY
+ argument, to control whether the op should be simplified prior
+ to looking up/assigning a value number.
+ (vn_nary_build_or_lookup): Update call to vn_nary_build_or_lookup_1.
+ (vn_nary_simplify): Likewise.
+ (visit_nary_op): Likewise, but when constructing a NEGATE_EXPR
+ now call vn_nary_build_or_lookup_1 disabling simplification.
+
+2021-09-22 Jiufu Guo <guojiufu@linux.ibm.com>
+
+ PR tree-optimization/102087
+ * tree-ssa-loop-niter.c (number_of_iterations_until_wrap):
+ Update bound/cmp/control for niter.
+
+2021-09-22 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-fold.cc (fold_using_range::range_of_range_op):
+ Move check for non-empty BB here.
+ (fur_source::register_outgoing_edges): ...from here.
+
+2021-09-22 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::internal_range_of_expr):
+ Remove call to improve_range_with_equivs.
+ (path_range_query::improve_range_with_equivs): Remove
+ * gimple-range-path.h: Remove improve_range_with_equivs.
+
+2021-09-22 dianhong xu <dianhong.xu@intel.com>
+
+ * config/i386/avx512fp16intrin.h:
+ (_mm512_mask_blend_ph): New intrinsic.
+ (_mm512_permutex2var_ph): Ditto.
+ (_mm512_permutexvar_ph): Ditto.
+ * config/i386/avx512fp16vlintrin.h:
+ (_mm256_mask_blend_ph): New intrinsic.
+ (_mm256_permutex2var_ph): Ditto.
+ (_mm256_permutexvar_ph): Ditto.
+ (_mm_mask_blend_ph): Ditto.
+ (_mm_permutex2var_ph): Ditto.
+ (_mm_permutexvar_ph): Ditto.
+
+2021-09-22 dianhong xu <dianhong.xu@intel.com>
+
+ * config/i386/avx512fp16intrin.h: Add new intrinsics.
+ (_mm512_conj_pch): New intrinsic.
+ (_mm512_mask_conj_pch): Ditto.
+ (_mm512_maskz_conj_pch): Ditto.
+ * config/i386/avx512fp16vlintrin.h: Add new intrinsics.
+ (_mm256_conj_pch): New intrinsic.
+ (_mm256_mask_conj_pch): Ditto.
+ (_mm256_maskz_conj_pch): Ditto.
+ (_mm_conj_pch): Ditto.
+ (_mm_mask_conj_pch): Ditto.
+ (_mm_maskz_conj_pch): Ditto.
+
+2021-09-22 dianhong xu <dianhong.xu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_MM512_REDUCE_OP): New macro
+ (_mm512_reduce_add_ph): New intrinsic.
+ (_mm512_reduce_mul_ph): Ditto.
+ (_mm512_reduce_min_ph): Ditto.
+ (_mm512_reduce_max_ph): Ditto.
+ * config/i386/avx512fp16vlintrin.h
+ (_MM256_REDUCE_OP/_MM_REDUCE_OP): New macro.
+ (_mm256_reduce_add_ph): New intrinsic.
+ (_mm256_reduce_mul_ph): Ditto.
+ (_mm256_reduce_min_ph): Ditto.
+ (_mm256_reduce_max_ph): Ditto.
+ (_mm_reduce_add_ph): Ditto.
+ (_mm_reduce_mul_ph): Ditto.
+ (_mm_reduce_min_ph): Ditto.
+ (_mm_reduce_max_ph): Ditto.
+
+2021-09-22 dianhong xu <dianhong.xu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (__m512h_u, __m256h_u,
+ __m128h_u): New typedef.
+ (_mm512_load_ph): New intrinsic.
+ (_mm256_load_ph): Ditto.
+ (_mm_load_ph): Ditto.
+ (_mm512_loadu_ph): Ditto.
+ (_mm256_loadu_ph): Ditto.
+ (_mm_loadu_ph): Ditto.
+ (_mm512_store_ph): Ditto.
+ (_mm256_store_ph): Ditto.
+ (_mm_store_ph): Ditto.
+ (_mm512_storeu_ph): Ditto.
+ (_mm256_storeu_ph): Ditto.
+ (_mm_storeu_ph): Ditto.
+ (_mm512_abs_ph): Ditto.
+ * config/i386/avx512fp16vlintrin.h
+ (_mm_abs_ph): Ditto.
+ (_mm256_abs_ph): Ditto.
+
+2021-09-22 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * config/s390/tpf.md (prologue_tpf, epilogue_tpf): Add cc clobber.
+
+2021-09-22 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ PR target/102222
+ * config/s390/s390.c (s390_expand_insv): Emit a normal move if it
+ is actually a full copy of the source operand into the target.
+ Don't emit a strict low part move if source and target mode match.
+
+2021-09-22 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/102415
+ * omp-expand.c (expand_omp_single): If region->exit is NULL,
+ assert region->entry is GIMPLE_OMP_SCOPE region and return.
+
+2021-09-22 Jakub Jelinek <jakub@redhat.com>
+
+ * tree.h (OMP_CLAUSE_ALLOCATE_ALIGN): Define.
+ * tree.c (omp_clause_num_ops): Change number of OMP_CLAUSE_ALLOCATE
+ arguments from 2 to 3.
+ * tree-pretty-print.c (dump_omp_clause): Print allocator() around
+ allocate clause allocator and print align if present.
+ * omp-low.c (scan_sharing_clauses): Force allocate_map entry even
+ for omp_default_mem_alloc if align modifier is present. If align
+ modifier is present, use TREE_LIST to encode both allocator and
+ align.
+ (lower_private_allocate, lower_rec_input_clauses, create_task_copyfn):
+ Handle align modifier on allocator clause if present.
+
+2021-09-22 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/i386.md (define_attr "isa"): Add
+ fma_or_avx512vl.
+ (define_attr "enabled"): Correspond fma_or_avx512vl to
+ TARGET_FMA || TARGET_AVX512VL.
+ * config/i386/mmx.md (fmav2sf4): Extend to AVX512 fma.
+ (fmsv2sf4): Ditto.
+ (fnmav2sf4): Ditto.
+ (fnmsv2sf4): Ditto.
+
+2021-09-22 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/i386.md (cstorehf3): New define_expand.
+
+2021-09-22 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/i386.md (<rounding_insn>hf2): New expander.
+ (sse4_1_round<mode>2): Extend from MODEF to MODEFH.
+ * config/i386/sse.md (*sse4_1_round<ssescalarmodesuffix>):
+ Extend from VF_128 to VFH_128.
+
+2021-09-22 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/i386-features.c (i386-features.c): Handle
+ E_HFmode.
+ * config/i386/i386.md (sqrthf2): New expander.
+ (*sqrthf2): New define_insn.
+ * config/i386/sse.md
+ (*<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>):
+ Extend to VFH_128.
+
+2021-09-22 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm_mask_fcmadd_sch):
+ New intrinsic.
+ (_mm_mask3_fcmadd_sch): Likewise.
+ (_mm_maskz_fcmadd_sch): Likewise.
+ (_mm_fcmadd_sch): Likewise.
+ (_mm_mask_fmadd_sch): Likewise.
+ (_mm_mask3_fmadd_sch): Likewise.
+ (_mm_maskz_fmadd_sch): Likewise.
+ (_mm_fmadd_sch): Likewise.
+ (_mm_mask_fcmadd_round_sch): Likewise.
+ (_mm_mask3_fcmadd_round_sch): Likewise.
+ (_mm_maskz_fcmadd_round_sch): Likewise.
+ (_mm_fcmadd_round_sch): Likewise.
+ (_mm_mask_fmadd_round_sch): Likewise.
+ (_mm_mask3_fmadd_round_sch): Likewise.
+ (_mm_maskz_fmadd_round_sch): Likewise.
+ (_mm_fmadd_round_sch): Likewise.
+ (_mm_fcmul_sch): Likewise.
+ (_mm_mask_fcmul_sch): Likewise.
+ (_mm_maskz_fcmul_sch): Likewise.
+ (_mm_fmul_sch): Likewise.
+ (_mm_mask_fmul_sch): Likewise.
+ (_mm_maskz_fmul_sch): Likewise.
+ (_mm_fcmul_round_sch): Likewise.
+ (_mm_mask_fcmul_round_sch): Likewise.
+ (_mm_maskz_fcmul_round_sch): Likewise.
+ (_mm_fmul_round_sch): Likewise.
+ (_mm_mask_fmul_round_sch): Likewise.
+ (_mm_maskz_fmul_round_sch): Likewise.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/sse.md
+ (avx512fp16_fmaddcsh_v8hf_maskz<round_expand_name>): New expander.
+ (avx512fp16_fcmaddcsh_v8hf_maskz<round_expand_name>): Ditto.
+ (avx512fp16_fma_<complexopname>sh_v8hf<mask_scalarcz_name><round_scalarcz_name>):
+ New define insn.
+ (avx512fp16_<complexopname>sh_v8hf_mask<round_name>): Ditto.
+ (avx512fp16_<complexopname>sh_v8hf<mask_scalarc_name><round_scalarcz_name>):
+ Ditto.
+ * config/i386/subst.md (mask_scalarcz_name): New.
+ (mask_scalarc_name): Ditto.
+ (mask_scalarc_operand3): Ditto.
+ (mask_scalarcz_operand4): Ditto.
+ (round_scalarcz_name): Ditto.
+ (round_scalarc_mask_operand3): Ditto.
+ (round_scalarcz_mask_operand4): Ditto.
+ (round_scalarc_mask_op3): Ditto.
+ (round_scalarcz_mask_op4): Ditto.
+ (round_scalarcz_constraint): Ditto.
+ (round_scalarcz_nimm_predicate): Ditto.
+ (mask_scalarcz): Ditto.
+ (mask_scalarc): Ditto.
+ (round_scalarcz): Ditto.
+
+2021-09-22 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm512_fcmadd_pch):
+ New intrinsic.
+ (_mm512_mask_fcmadd_pch): Likewise.
+ (_mm512_mask3_fcmadd_pch): Likewise.
+ (_mm512_maskz_fcmadd_pch): Likewise.
+ (_mm512_fmadd_pch): Likewise.
+ (_mm512_mask_fmadd_pch): Likewise.
+ (_mm512_mask3_fmadd_pch): Likewise.
+ (_mm512_maskz_fmadd_pch): Likewise.
+ (_mm512_fcmadd_round_pch): Likewise.
+ (_mm512_mask_fcmadd_round_pch): Likewise.
+ (_mm512_mask3_fcmadd_round_pch): Likewise.
+ (_mm512_maskz_fcmadd_round_pch): Likewise.
+ (_mm512_fmadd_round_pch): Likewise.
+ (_mm512_mask_fmadd_round_pch): Likewise.
+ (_mm512_mask3_fmadd_round_pch): Likewise.
+ (_mm512_maskz_fmadd_round_pch): Likewise.
+ (_mm512_fcmul_pch): Likewise.
+ (_mm512_mask_fcmul_pch): Likewise.
+ (_mm512_maskz_fcmul_pch): Likewise.
+ (_mm512_fmul_pch): Likewise.
+ (_mm512_mask_fmul_pch): Likewise.
+ (_mm512_maskz_fmul_pch): Likewise.
+ (_mm512_fcmul_round_pch): Likewise.
+ (_mm512_mask_fcmul_round_pch): Likewise.
+ (_mm512_maskz_fcmul_round_pch): Likewise.
+ (_mm512_fmul_round_pch): Likewise.
+ (_mm512_mask_fmul_round_pch): Likewise.
+ (_mm512_maskz_fmul_round_pch): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_fmadd_pch):
+ New intrinsic.
+ (_mm_mask_fmadd_pch): Likewise.
+ (_mm_mask3_fmadd_pch): Likewise.
+ (_mm_maskz_fmadd_pch): Likewise.
+ (_mm256_fmadd_pch): Likewise.
+ (_mm256_mask_fmadd_pch): Likewise.
+ (_mm256_mask3_fmadd_pch): Likewise.
+ (_mm256_maskz_fmadd_pch): Likewise.
+ (_mm_fcmadd_pch): Likewise.
+ (_mm_mask_fcmadd_pch): Likewise.
+ (_mm_mask3_fcmadd_pch): Likewise.
+ (_mm_maskz_fcmadd_pch): Likewise.
+ (_mm256_fcmadd_pch): Likewise.
+ (_mm256_mask_fcmadd_pch): Likewise.
+ (_mm256_mask3_fcmadd_pch): Likewise.
+ (_mm256_maskz_fcmadd_pch): Likewise.
+ (_mm_fmul_pch): Likewise.
+ (_mm_mask_fmul_pch): Likewise.
+ (_mm_maskz_fmul_pch): Likewise.
+ (_mm256_fmul_pch): Likewise.
+ (_mm256_mask_fmul_pch): Likewise.
+ (_mm256_maskz_fmul_pch): Likewise.
+ (_mm_fcmul_pch): Likewise.
+ (_mm_mask_fcmul_pch): Likewise.
+ (_mm_maskz_fcmul_pch): Likewise.
+ (_mm256_fcmul_pch): Likewise.
+ (_mm256_mask_fcmul_pch): Likewise.
+ (_mm256_maskz_fcmul_pch): Likewise.
+ * config/i386/i386-builtin-types.def (V8HF_FTYPE_V8HF_V8HF_V8HF,
+ V8HF_FTYPE_V16HF_V16HF_V16HF, V16HF_FTYPE_V16HF_V16HF_V16HF_UQI,
+ V32HF_FTYPE_V32HF_V32HF_V32HF_INT,
+ V32HF_FTYPE_V32HF_V32HF_V32HF_UHI_INT): Add new builtin types.
+ * config/i386/i386-builtin.def: Add new builtins.
+ * config/i386/i386-expand.c: Handle new builtin types.
+ * config/i386/subst.md (SUBST_CV): New.
+ (maskc_name): Ditto.
+ (maskc_operand3): Ditto.
+ (maskc): Ditto.
+ (sdc_maskz_name): Ditto.
+ (sdc_mask_op4): Ditto.
+ (sdc_mask_op5): Ditto.
+ (sdc_mask_mode512bit_condition): Ditto.
+ (sdc): Ditto.
+ (round_maskc_operand3): Ditto.
+ (round_sdc_mask_operand4): Ditto.
+ (round_maskc_op3): Ditto.
+ (round_sdc_mask_op4): Ditto.
+ (round_saeonly_sdc_mask_operand5): Ditto.
+ * config/i386/sse.md (unspec): Add complex fma unspecs.
+ (avx512fmaskcmode): New.
+ (UNSPEC_COMPLEX_F_C_MA): Ditto.
+ (UNSPEC_COMPLEX_F_C_MUL): Ditto.
+ (complexopname): Ditto.
+ (<avx512>_fmaddc_<mode>_maskz<round_expand_name>): New expander.
+ (<avx512>_fcmaddc_<mode>_maskz<round_expand_name>): Ditto.
+ (fma_<complexopname>_<mode><sdc_maskz_name><round_name>): New
+ define insn.
+ (<avx512>_<complexopname>_<mode>_mask<round_name>): Ditto.
+ (<avx512>_<complexopname>_<mode><maskc_name><round_name>): Ditto.
+
+2021-09-22 Kewen Lin <linkw@linux.ibm.com>
+
+ * config/rs6000/rs6000.opt (rs6000-density-pct-threshold,
+ rs6000-density-size-threshold, rs6000-density-penalty,
+ rs6000-density-load-pct-threshold,
+ rs6000-density-load-num-threshold): New parameter.
+ * config/rs6000/rs6000.c (rs6000_density_test): Adjust with
+ corresponding parameters.
+
+2021-09-21 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::defined_outside_path):
+ New.
+ (path_range_query::range_on_path_entry): New.
+ (path_range_query::internal_range_of_expr): Resolve unknowns
+ with ranger.
+ (path_range_query::improve_range_with_equivs): New.
+ (path_range_query::ssa_range_in_phi): Resolve unknowns with
+ ranger.
+ * gimple-range-path.h (class path_range_query): Add
+ defined_outside_path, range_on_path_entry, and
+ improve_range_with_equivs.
+
+2021-09-21 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::add_to_imports): New.
+ (path_range_query::add_copies_to_imports): New.
+ (path_range_query::precompute_ranges): Call
+ add_copies_to_imports.
+ * gimple-range-path.h (class path_range_query): Add prototypes
+ for add_copies_to_imports and add_to_imports.
+
+2021-09-21 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::range_defined_in_block):
+ Remove useless code.
+
+2021-09-21 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-fold.h (class fur_source): Make oracle protected.
+ * gimple-range-path.cc (path_range_query::path_range_query): Add
+ resolve argument. Initialize oracle.
+ (path_range_query::~path_range_query): Delete oracle.
+ (path_range_query::range_of_stmt): Adapt to use relations.
+ (path_range_query::precompute_ranges): Pre-compute relations.
+ (class jt_fur_source): New
+ (jt_fur_source::jt_fur_source): New.
+ (jt_fur_source::register_relation): New.
+ (jt_fur_source::query_relation): New.
+ (path_range_query::precompute_relations): New.
+ (path_range_query::precompute_phi_relations): New.
+ * gimple-range-path.h (path_range_query): Add resolve argument.
+ Add oracle, precompute_relations, precompute_phi_relations.
+ * tree-ssa-threadbackward.c (back_threader::back_threader): Pass
+ resolve argument to solver.
+
+2021-09-21 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-fold.cc (fold_using_range::range_of_range_op):
+ Rename postfold_gcond_edges to register_outgoing_edges and
+ adapt.
+ (fold_using_range::postfold_gcond_edges): Rename...
+ (fur_source::register_outgoing_edges): ...to this.
+ * gimple-range-fold.h (postfold_gcond_edges): Rename to
+ register_outgoing_edges and move to fur_source.
+
+2021-09-21 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-fold.cc (fold_using_range::range_of_phi): Check
+ dom_info_available_p.
+
+2021-09-21 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-cache.cc (non_null_ref::non_null_ref): Use create
+ and quick_grow_cleared instead of safe_grow_cleared.
+
+2021-09-21 Thomas Schwinge <thomas@codesourcery.com>
+
+ PR other/102408
+ * omp-oacc-neuter-broadcast.cc (oacc_do_neutering): Evaluate
+ 'random ()' to '0'.
+
+2021-09-21 Richard Earnshaw <rearnsha@arm.com>
+
+ * configure.ac: Detect when the assembler supports new-style
+ architecture extensions.
+ * common/config/arm/arm-common.c (arm_rewrite_mcpu): Return
+ the full CPU string if the assembler can grok it.
+ (arm_rewrite_march): Likewise but for the architecture.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+
+2021-09-21 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102421
+ * tree-vect-loop.c (vect_dissolve_slp_only_groups): Copy and
+ adjust alignment info.
+
+2021-09-21 Kewen Lin <linkw@linux.ibm.com>
+
+ * ipa-fnsummary.c (ipa_fn_summary_write): Remove inconsistent
+ bitfield stream out.
+
+2021-09-20 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-fold.cc (fold_using_range::range_of_phi): Ignore
+ undefined edges, apply an equivalence if appropriate.
+ * gimple-range-gori.cc (gori_compute::outgoing_edge_range_p): Return
+ UNDEFINED if EDGE_EXECUTABLE is not set.
+ * gimple-range.cc (gimple_ranger::gimple_ranger): Set all edges
+ as EXECUTABLE upon startup.
+ (gimple_ranger::range_on_edge): Return UNDEFINED for edges without
+ EDGE_EXECUTABLE set.
+ * vr-values.c (set_and_propagate_unexecutable): New.
+ (simplify_using_ranges::fold_cond): Call set_and_propagate.
+ (simplify_using_ranges::simplify_switch_using_ranges): Ditto.
+ * vr-values.h: Add prototype.
+
+2021-09-20 Andrew MacLeod <amacleod@redhat.com>
+
+ * value-relation.cc (equiv_oracle::register_initial_def): New.
+ (equiv_oracle::register_relation): Call register_initial_def.
+ (equiv_oracle::add_equiv_to_block): New. Split register_relation.
+ (relation_oracle::register_stmt): Check def block of PHI arguments.
+ * value-relation.h (equiv_oracle): Add new prototypes.
+
+2021-09-20 Matthias Kretz <m.kretz@gsi.de>
+
+ * cppbuiltin.c (define_builtin_macros_for_compilation_flags):
+ Define __RECIPROCAL_MATH__, __NO_SIGNED_ZEROS__,
+ __NO_TRAPPING_MATH__, __ASSOCIATIVE_MATH__, and
+ __ROUNDING_MATH__ according to their corresponding flags.
+ * doc/cpp.texi: Document __RECIPROCAL_MATH__,
+ __NO_SIGNED_ZEROS__, __NO_TRAPPING_MATH__, __ASSOCIATIVE_MATH__,
+ and __ROUNDING_MATH__.
+
+2021-09-20 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-stmts.c (vectorizable_load): Use the vectype
+ from the SLP node.
+
+2021-09-20 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-data-refs.c (vect_duplicate_ssa_name_ptr_info):
+ Do not compute alignment of the vectorized access here.
+
+2021-09-20 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-data-refs.c (vect_enhance_data_refs_alignment):
+ Store -1 for runtime alias peeling iterations.
+
+2021-09-20 Richard Biener <rguenther@suse.de>
+
+ * config.gcc: Obsolete hppa[12]*-*-hpux10* and hppa[12]*-*-hpux11*.
+
+2021-09-20 Thomas Schwinge <thomas@codesourcery.com>
+
+ * input.c (string_concat_db::record_string_concatenation)
+ (string_concat_db::get_string_concatenation): Skip for
+ 'RESERVED_LOCATION_P'.
+
+2021-09-20 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/65206
+ * tree-data-ref.h (struct data_reference): Add alt_indices,
+ order it last.
+ * tree-data-ref.c (free_data_ref): Release alt_indices.
+ (dr_analyze_indices): Work on struct indices and get DR_REF as tree.
+ (create_data_ref): Adjust.
+ (initialize_data_dependence_relation): Split into head
+ and tail. When the base objects fail to match up try
+ again with pointer-based analysis of indices.
+ * tree-vectorizer.c (vec_info_shared::check_datarefs): Do
+ not compare the lazily computed alternate set of indices.
+
+2021-09-20 Iain Sandoe <iain@sandoe.co.uk>
+
+ * gcc.c: Test for execute OK when we find the
+ programs for assembler linker and dsymutil and those
+ were specified at configure-time.
+
+2021-09-19 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/102403
+ * gimple-predicate-analysis.cc (predicate::init_from_control_deps):
+ Correct a function pre/postcondition.
+
+2021-09-19 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/102243
+ * tree-ssa-strlen.c (get_range): Handle null cfun.
+
+2021-09-19 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.h (LINK_COMMAND_SPEC_A): Use Darwin10
+ unwinder shim as a convenience library.
+
+2021-09-19 Andrew Pinski <apinski@marvell.com>
+
+ * doc/install.texi: Add note about
+ binutils 2.35 is required for LTO usage.
+
+2021-09-19 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c
+ (back_threader_registry::register_path): Use push_edge.
+ * tree-ssa-threadedge.c
+ (jump_threader::thread_around_empty_blocks): Same.
+ (jump_threader::thread_through_normal_block): Same.
+ (jump_threader::thread_across_edge): Same. Also, use auto_bitmap.
+ Tidy up code.
+ * tree-ssa-threadupdate.c
+ (jt_path_registry::allocate_thread_edge): Remove.
+ (jt_path_registry::push_edge): New.
+ (dump_jump_thread_path): Make static.
+ * tree-ssa-threadupdate.h (allocate_thread_edge): Remove.
+ (push_edge): New.
+
+2021-09-19 Aldy Hernandez <aldyh@redhat.com>
+
+ * gimple-range-path.cc (path_range_query::path_range_query): Add
+ header.
+ (path_range_query::dump): Remove extern declaration of dump_ranger.
+ * gimple-range-trace.cc (dump_ranger): Add DEBUG_FUNCTION marker.
+ * gimple-range-trace.h (dump_ranger): Add prototype.
+
+2021-09-19 John Ericson <git@JohnEricson.me>
+
+ * gcc.c (find_a_program): New function, factored out of...
+ (find_a_file): Here.
+ (execute): Use find_a_program when looking for programs rather
+ than find_a_file.
+
+2021-09-19 Matwey V. Kornilov <matwey.kornilov@gmail.com>
+
+ * config/avr/avr-mcus.def: Add atmega324pb.
+ * doc/avr-mmcu.texi: Corresponding changes.
+
+2021-09-19 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR middle-end/88173
+ * match.pd (cmp @0 REAL_CST@1): When @0 is also REAL_CST, apply
+ the same transformations as to @1. For comparisons against NaN,
+ don't check HONOR_SNANS but confirm that neither operand is a
+ signaling NaN.
+
+2021-09-19 Benjamin Peterson <benjamin@locrian.net>
+
+ * attribs.c (make_unique_name): Delete.
+ * attribs.h (make_unique_name): Delete.
+
+2021-09-19 Andrew Pinski <apinski@marvell.com>
+
+ * lra-constraints.c (check_and_process_move): Assert
+ that dclass and sclass are greater than or equal to NO_REGS.
+
+2021-09-18 Jakub Jelinek <jakub@redhat.com>
+
+ * tree.h (OMP_CLAUSE_ORDER_UNCONSTRAINED): Define.
+ * tree-pretty-print.c (dump_omp_clause): Print unconstrained:
+ for OMP_CLAUSE_ORDER_UNCONSTRAINED.
+
+2021-09-18 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/i386-features.c (remove_partial_avx_dependency):
+ Restrict TARGET_USE_VECTOR_FP_CONVERTS and
+ TARGET_USE_VECTOR_CONVERTS to conversion instructions only.
+
+2021-09-18 Jakub Jelinek <jakub@redhat.com>
+
+ * gimplify.c (omp_default_clause): For C/C++ default({,first}private),
+ if file/namespace scope variable doesn't have predetermined sharing,
+ treat it as if there was default(none).
+
+2021-09-18 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm_fmadd_sh):
+ New intrinsic.
+ (_mm_mask_fmadd_sh): Likewise.
+ (_mm_mask3_fmadd_sh): Likewise.
+ (_mm_maskz_fmadd_sh): Likewise.
+ (_mm_fmadd_round_sh): Likewise.
+ (_mm_mask_fmadd_round_sh): Likewise.
+ (_mm_mask3_fmadd_round_sh): Likewise.
+ (_mm_maskz_fmadd_round_sh): Likewise.
+ (_mm_fnmadd_sh): Likewise.
+ (_mm_mask_fnmadd_sh): Likewise.
+ (_mm_mask3_fnmadd_sh): Likewise.
+ (_mm_maskz_fnmadd_sh): Likewise.
+ (_mm_fnmadd_round_sh): Likewise.
+ (_mm_mask_fnmadd_round_sh): Likewise.
+ (_mm_mask3_fnmadd_round_sh): Likewise.
+ (_mm_maskz_fnmadd_round_sh): Likewise.
+ (_mm_fmsub_sh): Likewise.
+ (_mm_mask_fmsub_sh): Likewise.
+ (_mm_mask3_fmsub_sh): Likewise.
+ (_mm_maskz_fmsub_sh): Likewise.
+ (_mm_fmsub_round_sh): Likewise.
+ (_mm_mask_fmsub_round_sh): Likewise.
+ (_mm_mask3_fmsub_round_sh): Likewise.
+ (_mm_maskz_fmsub_round_sh): Likewise.
+ (_mm_fnmsub_sh): Likewise.
+ (_mm_mask_fnmsub_sh): Likewise.
+ (_mm_mask3_fnmsub_sh): Likewise.
+ (_mm_maskz_fnmsub_sh): Likewise.
+ (_mm_fnmsub_round_sh): Likewise.
+ (_mm_mask_fnmsub_round_sh): Likewise.
+ (_mm_mask3_fnmsub_round_sh): Likewise.
+ (_mm_maskz_fnmsub_round_sh): Likewise.
+ * config/i386/i386-builtin-types.def
+ (V8HF_FTYPE_V8HF_V8HF_V8HF_UQI_INT): New builtin type.
+ * config/i386/i386-builtin.def: Add new builtins.
+ * config/i386/i386-expand.c: Handle new builtin type.
+ * config/i386/sse.md (fmai_vmfmadd_<mode><round_name>):
+ Ajdust to support FP16.
+ (fmai_vmfmsub_<mode><round_name>): Ditto.
+ (fmai_vmfnmadd_<mode><round_name>): Ditto.
+ (fmai_vmfnmsub_<mode><round_name>): Ditto.
+ (*fmai_fmadd_<mode>): Ditto.
+ (*fmai_fmsub_<mode>): Ditto.
+ (*fmai_fnmadd_<mode><round_name>): Ditto.
+ (*fmai_fnmsub_<mode><round_name>): Ditto.
+ (avx512f_vmfmadd_<mode>_mask<round_name>): Ditto.
+ (avx512f_vmfmadd_<mode>_mask3<round_name>): Ditto.
+ (avx512f_vmfmadd_<mode>_maskz<round_expand_name>): Ditto.
+ (avx512f_vmfmadd_<mode>_maskz_1<round_name>): Ditto.
+ (*avx512f_vmfmsub_<mode>_mask<round_name>): Ditto.
+ (avx512f_vmfmsub_<mode>_mask3<round_name>): Ditto.
+ (*avx512f_vmfmsub_<mode>_maskz_1<round_name>): Ditto.
+ (*avx512f_vmfnmsub_<mode>_mask<round_name>): Ditto.
+ (*avx512f_vmfnmsub_<mode>_mask3<round_name>): Ditto.
+ (*avx512f_vmfnmsub_<mode>_mask<round_name>): Ditto.
+ (*avx512f_vmfnmadd_<mode>_mask<round_name>): Renamed to ...
+ (avx512f_vmfnmadd_<mode>_mask<round_name>) ... this, and
+ adjust to support FP16.
+ (avx512f_vmfnmadd_<mode>_mask3<round_name>): Ditto.
+ (avx512f_vmfnmadd_<mode>_maskz_1<round_name>): Ditto.
+ (avx512f_vmfnmadd_<mode>_maskz<round_expand_name>): New
+ expander.
+
+2021-09-18 H.J. Lu <hjl.tools@gmail.com>
+
+ * config/i386/sse.md (avx512fmaskmodelower): Extend to support
+ HF modes.
+ (maskload<mode><avx512fmaskmodelower>): Ditto.
+ (maskstore<mode><avx512fmaskmodelower>): Ditto.
+
+2021-09-18 H.J. Lu <hjl.tools@gmail.com>
+
+ * config/i386/i386-expand.c (ix86_expand_fp_absneg_operator):
+ Handle HFmode.
+ (ix86_expand_copysign): Ditto.
+ (ix86_expand_xorsign): Ditto.
+ * config/i386/i386.c (ix86_build_const_vector): Handle HF vector
+ modes.
+ (ix86_build_signbit_mask): Ditto.
+ (ix86_can_change_mode_class): Ditto.
+ * config/i386/i386.md
+ (SSEMODEF): Add HFmode.
+ (ssevecmodef): Ditto.
+ (<code>hf2): New define_expand.
+ (*<code>hf2_1): New define_insn_and_split.
+ (copysign<mode>): Extend to support HFmode under AVX512FP16.
+ (xorsign<mode>): Ditto.
+ * config/i386/sse.md (VFB): New mode iterator.
+ (VFB_128_256): Ditto.
+ (VFB_512): Ditto.
+ (sseintvecmode2): Support HF vector mode.
+ (<code><mode>2): Use new mode iterator.
+ (*<code><mode>2): Ditto.
+ (copysign<mode>3): Ditto.
+ (xorsign<mode>3): Ditto.
+ (<code><mode>3<mask_name>): Ditto.
+ (<code><mode>3<mask_name>): Ditto.
+ (<sse>_andnot<mode>3<mask_name>): Adjust for HF vector mode.
+ (<sse>_andnot<mode>3<mask_name>): Ditto.
+ (*<code><mode>3<mask_name>): Ditto.
+ (*<code><mode>3<mask_name>): Ditto.
+
+2021-09-18 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm512_mask_fmadd_ph):
+ New intrinsic.
+ (_mm512_mask3_fmadd_ph): Likewise.
+ (_mm512_maskz_fmadd_ph): Likewise.
+ (_mm512_fmadd_round_ph): Likewise.
+ (_mm512_mask_fmadd_round_ph): Likewise.
+ (_mm512_mask3_fmadd_round_ph): Likewise.
+ (_mm512_maskz_fmadd_round_ph): Likewise.
+ (_mm512_fnmadd_ph): Likewise.
+ (_mm512_mask_fnmadd_ph): Likewise.
+ (_mm512_mask3_fnmadd_ph): Likewise.
+ (_mm512_maskz_fnmadd_ph): Likewise.
+ (_mm512_fnmadd_round_ph): Likewise.
+ (_mm512_mask_fnmadd_round_ph): Likewise.
+ (_mm512_mask3_fnmadd_round_ph): Likewise.
+ (_mm512_maskz_fnmadd_round_ph): Likewise.
+ (_mm512_fmsub_ph): Likewise.
+ (_mm512_mask_fmsub_ph): Likewise.
+ (_mm512_mask3_fmsub_ph): Likewise.
+ (_mm512_maskz_fmsub_ph): Likewise.
+ (_mm512_fmsub_round_ph): Likewise.
+ (_mm512_mask_fmsub_round_ph): Likewise.
+ (_mm512_mask3_fmsub_round_ph): Likewise.
+ (_mm512_maskz_fmsub_round_ph): Likewise.
+ (_mm512_fnmsub_ph): Likewise.
+ (_mm512_mask_fnmsub_ph): Likewise.
+ (_mm512_mask3_fnmsub_ph): Likewise.
+ (_mm512_maskz_fnmsub_ph): Likewise.
+ (_mm512_fnmsub_round_ph): Likewise.
+ (_mm512_mask_fnmsub_round_ph): Likewise.
+ (_mm512_mask3_fnmsub_round_ph): Likewise.
+ (_mm512_maskz_fnmsub_round_ph): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm256_fmadd_ph):
+ New intrinsic.
+ (_mm256_mask_fmadd_ph): Likewise.
+ (_mm256_mask3_fmadd_ph): Likewise.
+ (_mm256_maskz_fmadd_ph): Likewise.
+ (_mm_fmadd_ph): Likewise.
+ (_mm_mask_fmadd_ph): Likewise.
+ (_mm_mask3_fmadd_ph): Likewise.
+ (_mm_maskz_fmadd_ph): Likewise.
+ (_mm256_fnmadd_ph): Likewise.
+ (_mm256_mask_fnmadd_ph): Likewise.
+ (_mm256_mask3_fnmadd_ph): Likewise.
+ (_mm256_maskz_fnmadd_ph): Likewise.
+ (_mm_fnmadd_ph): Likewise.
+ (_mm_mask_fnmadd_ph): Likewise.
+ (_mm_mask3_fnmadd_ph): Likewise.
+ (_mm_maskz_fnmadd_ph): Likewise.
+ (_mm256_fmsub_ph): Likewise.
+ (_mm256_mask_fmsub_ph): Likewise.
+ (_mm256_mask3_fmsub_ph): Likewise.
+ (_mm256_maskz_fmsub_ph): Likewise.
+ (_mm_fmsub_ph): Likewise.
+ (_mm_mask_fmsub_ph): Likewise.
+ (_mm_mask3_fmsub_ph): Likewise.
+ (_mm_maskz_fmsub_ph): Likewise.
+ (_mm256_fnmsub_ph): Likewise.
+ (_mm256_mask_fnmsub_ph): Likewise.
+ (_mm256_mask3_fnmsub_ph): Likewise.
+ (_mm256_maskz_fnmsub_ph): Likewise.
+ (_mm_fnmsub_ph): Likewise.
+ (_mm_mask_fnmsub_ph): Likewise.
+ (_mm_mask3_fnmsub_ph): Likewise.
+ (_mm_maskz_fnmsub_ph): Likewise.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/sse.md
+ (<avx512>_fmadd_<mode>_maskz<round_expand_name>): Adjust to
+ support HF vector modes.
+ (<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>):
+ Ditto.
+ (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_1): Ditto.
+ (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_2): Ditto.
+ (*<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name>_bcst_3): Ditto.
+ (<avx512>_fmadd_<mode>_mask<round_name>): Ditto.
+ (<avx512>_fmadd_<mode>_mask3<round_name>): Ditto.
+ (<avx512>_fmsub_<mode>_maskz<round_expand_name>): Ditto.
+ (<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>):
+ Ditto.
+ (*<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_1): Ditto.
+ (*<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_2): Ditto.
+ (*<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name>_bcst_3): Ditto.
+ (<avx512>_fmsub_<mode>_mask<round_name>): Ditto.
+ (<avx512>_fmsub_<mode>_mask3<round_name>): Ditto.
+ (<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>):
+ Ditto.
+ (*<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_1): Ditto.
+ (*<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_2): Ditto.
+ (*<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name>_bcst_3): Ditto.
+ (<avx512>_fnmadd_<mode>_mask<round_name>): Ditto.
+ (<avx512>_fnmadd_<mode>_mask3<round_name>): Ditto.
+ (<avx512>_fnmsub_<mode>_maskz<round_expand_name>): Ditto.
+ (<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>):
+ Ditto.
+ (*<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_1): Ditto.
+ (*<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_2): Ditto.
+ (*<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name>_bcst_3): Ditto.
+ (<avx512>_fnmsub_<mode>_mask<round_name>): Ditto.
+ (<avx512>_fnmsub_<mode>_mask3<round_name>): Ditto.
+
+2021-09-18 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm512_fmaddsub_ph):
+ New intrinsic.
+ (_mm512_mask_fmaddsub_ph): Likewise.
+ (_mm512_mask3_fmaddsub_ph): Likewise.
+ (_mm512_maskz_fmaddsub_ph): Likewise.
+ (_mm512_fmaddsub_round_ph): Likewise.
+ (_mm512_mask_fmaddsub_round_ph): Likewise.
+ (_mm512_mask3_fmaddsub_round_ph): Likewise.
+ (_mm512_maskz_fmaddsub_round_ph): Likewise.
+ (_mm512_mask_fmsubadd_ph): Likewise.
+ (_mm512_mask3_fmsubadd_ph): Likewise.
+ (_mm512_maskz_fmsubadd_ph): Likewise.
+ (_mm512_fmsubadd_round_ph): Likewise.
+ (_mm512_mask_fmsubadd_round_ph): Likewise.
+ (_mm512_mask3_fmsubadd_round_ph): Likewise.
+ (_mm512_maskz_fmsubadd_round_ph): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm256_fmaddsub_ph):
+ New intrinsic.
+ (_mm256_mask_fmaddsub_ph): Likewise.
+ (_mm256_mask3_fmaddsub_ph): Likewise.
+ (_mm256_maskz_fmaddsub_ph): Likewise.
+ (_mm_fmaddsub_ph): Likewise.
+ (_mm_mask_fmaddsub_ph): Likewise.
+ (_mm_mask3_fmaddsub_ph): Likewise.
+ (_mm_maskz_fmaddsub_ph): Likewise.
+ (_mm256_fmsubadd_ph): Likewise.
+ (_mm256_mask_fmsubadd_ph): Likewise.
+ (_mm256_mask3_fmsubadd_ph): Likewise.
+ (_mm256_maskz_fmsubadd_ph): Likewise.
+ (_mm_fmsubadd_ph): Likewise.
+ (_mm_mask_fmsubadd_ph): Likewise.
+ (_mm_mask3_fmsubadd_ph): Likewise.
+ (_mm_maskz_fmsubadd_ph): Likewise.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/sse.md (VFH_SF_AVX512VL): New mode iterator.
+ * (<avx512>_fmsubadd_<mode>_maskz<round_expand_name>): New expander.
+ * (<avx512>_fmaddsub_<mode>_maskz<round_expand_name>): Use
+ VFH_SF_AVX512VL.
+ * (<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>):
+ Ditto.
+ * (<avx512>_fmaddsub_<mode>_mask<round_name>): Ditto.
+ * (<avx512>_fmaddsub_<mode>_mask3<round_name>): Ditto.
+ * (<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>):
+ Ditto.
+ * (<avx512>_fmsubadd_<mode>_mask<round_name>): Ditto.
+ * (<avx512>_fmsubadd_<mode>_mask3<round_name>): Ditto.
+
+2021-09-18 liuhongt <hongtao.liu@intel.com>
+
+ PR target/87767
+ * config/i386/i386.c (ix86_print_operand): Handle
+ V8HF/V16HF/V32HFmode.
+ * config/i386/i386.h (VALID_BCST_MODE_P): Add HFmode.
+ * config/i386/sse.md (avx512bcst): Remove.
+
+2021-09-17 Martin Sebor <msebor@redhat.com>
+
+ * Makefile.in (OBJS): Add gimple-predicate-analysis.o.
+ * tree-ssa-uninit.c (max_phi_args): Move to gimple-predicate-analysis.
+ (MASK_SET_BIT, MASK_TEST_BIT, MASK_EMPTY): Same.
+ (check_defs): Add comment.
+ (can_skip_redundant_opnd): Update comment.
+ (compute_uninit_opnds_pos): Adjust to namespace change.
+ (find_pdom): Move to gimple-predicate-analysis.cc.
+ (find_dom): Same.
+ (struct uninit_undef_val_t): New.
+ (is_non_loop_exit_postdominating): Move to gimple-predicate-analysis.cc.
+ (find_control_equiv_block): Same.
+ (MAX_NUM_CHAINS, MAX_CHAIN_LEN, MAX_POSTDOM_CHECK): Same.
+ (MAX_SWITCH_CASES): Same.
+ (compute_control_dep_chain): Same.
+ (find_uninit_use): Use predicate analyzer.
+ (struct pred_info): Move to gimple-predicate-analysis.
+ (convert_control_dep_chain_into_preds): Same.
+ (find_predicates): Same.
+ (collect_phi_def_edges): Same.
+ (warn_uninitialized_phi): Use predicate analyzer.
+ (find_def_preds): Move to gimple-predicate-analysis.
+ (dump_pred_info): Same.
+ (dump_pred_chain): Same.
+ (dump_predicates): Same.
+ (destroy_predicate_vecs): Remove.
+ (execute_late_warn_uninitialized): New.
+ (get_cmp_code): Move to gimple-predicate-analysis.
+ (is_value_included_in): Same.
+ (value_sat_pred_p): Same.
+ (find_matching_predicate_in_rest_chains): Same.
+ (is_use_properly_guarded): Same.
+ (prune_uninit_phi_opnds): Same.
+ (find_var_cmp_const): Same.
+ (use_pred_not_overlap_with_undef_path_pred): Same.
+ (pred_equal_p): Same.
+ (is_neq_relop_p): Same.
+ (is_neq_zero_form_p): Same.
+ (pred_expr_equal_p): Same.
+ (is_pred_expr_subset_of): Same.
+ (is_pred_chain_subset_of): Same.
+ (is_included_in): Same.
+ (is_superset_of): Same.
+ (pred_neg_p): Same.
+ (simplify_pred): Same.
+ (simplify_preds_2): Same.
+ (simplify_preds_3): Same.
+ (simplify_preds_4): Same.
+ (simplify_preds): Same.
+ (push_pred): Same.
+ (push_to_worklist): Same.
+ (get_pred_info_from_cmp): Same.
+ (is_degenerated_phi): Same.
+ (normalize_one_pred_1): Same.
+ (normalize_one_pred): Same.
+ (normalize_one_pred_chain): Same.
+ (normalize_preds): Same.
+ (can_one_predicate_be_invalidated_p): Same.
+ (can_chain_union_be_invalidated_p): Same.
+ (uninit_uses_cannot_happen): Same.
+ (pass_late_warn_uninitialized::execute): Define.
+ * gimple-predicate-analysis.cc: New file.
+ * gimple-predicate-analysis.h: New file.
+
+2021-09-17 Julian Brown <julian@codesourcery.com>
+
+ * config/gcn/gcn.c (gimple.h): Include.
+ (gcn_fork_join): Emit barrier for worker-level joins.
+ * omp-oacc-neuter-broadcast.cc (find_local_vars_to_propagate): Add
+ writes_gang_private bitmap parameter. Set bit for blocks
+ containing gang-private variable writes.
+ (worker_single_simple): Don't emit barrier after predicated block.
+ (worker_single_copy): Don't emit barrier if we're not broadcasting
+ anything and the block contains no gang-private writes.
+ (neuter_worker_single): Don't predicate blocks that only contain
+ NOPs or internal marker functions. Pass has_gang_private_write
+ argument to worker_single_copy.
+ (oacc_do_neutering): Add writes_gang_private bitmap handling.
+
+2021-09-17 Julian Brown <julian@codesourcery.com>
+
+ * config/gcn/gcn-protos.h
+ (gcn_goacc_create_worker_broadcast_record): Update prototype.
+ * config/gcn/gcn-tree.c (gcn_goacc_get_worker_red_decl): Use
+ preallocated block of LDS memory. Do not cache/share decls for
+ reduction temporaries between invocations.
+ (gcn_goacc_reduction_teardown): Unshare VAR on second use.
+ (gcn_goacc_create_worker_broadcast_record): Add OFFSET parameter
+ and return temporary LDS space at that offset. Return pointer in
+ "sender" case.
+ * config/gcn/gcn.c (acc_lds_size, gang_private_hwm, lds_allocs):
+ New global vars.
+ (ACC_LDS_SIZE): Define as acc_lds_size.
+ (gcn_init_machine_status): Don't initialise lds_allocated,
+ lds_allocs, reduc_decls fields of machine function struct.
+ (gcn_option_override): Handle default size for gang-private
+ variables and -mgang-private-size option.
+ (gcn_expand_prologue): Use LDS_SIZE instead of LDS_SIZE-1 when
+ initialising M0_REG.
+ (gcn_shared_mem_layout): New function.
+ (gcn_print_lds_decl): Update comment. Use global lds_allocs map and
+ gang_private_hwm variable.
+ (TARGET_GOACC_SHARED_MEM_LAYOUT): Define target hook.
+ * config/gcn/gcn.h (machine_function): Remove lds_allocated,
+ lds_allocs, reduc_decls. Add reduction_base, reduction_limit.
+ * config/gcn/gcn.opt (gang_private_size_opt): New global.
+ (mgang-private-size=): New option.
+ * doc/tm.texi.in (TARGET_GOACC_SHARED_MEM_LAYOUT): Place
+ documentation hook.
+ * doc/tm.texi: Regenerate.
+ * omp-oacc-neuter-broadcast.cc (targhooks.h, diagnostic-core.h):
+ Add includes.
+ (build_sender_ref): Handle sender_decl being pointer.
+ (worker_single_copy): Add PLACEMENT and ISOLATE_BROADCASTS
+ parameters. Pass placement argument to
+ create_worker_broadcast_record hook invocations. Handle
+ sender_decl being pointer and isolate_broadcasts inserting extra
+ barriers.
+ (blk_offset_map_t): Add typedef.
+ (neuter_worker_single): Add BLK_OFFSET_MAP parameter. Pass
+ preallocated range to worker_single_copy call.
+ (dfs_broadcast_reachable_1): New function.
+ (idx_decl_pair_t, used_range_vec_t): New typedefs.
+ (sort_size_descending): New function.
+ (addr_range): New class.
+ (splay_tree_compare_addr_range, splay_tree_free_key)
+ (first_fit_range, merge_ranges_1, merge_ranges): New functions.
+ (execute_omp_oacc_neuter_broadcast): Rename to...
+ (oacc_do_neutering): ... this. Add BOUNDS_LO, BOUNDS_HI
+ parameters. Arrange layout of shared memory for broadcast
+ operations.
+ (execute_omp_oacc_neuter_broadcast): New function.
+ (pass_omp_oacc_neuter_broadcast::gate): Remove num_workers==1
+ handling from here. Enable pass for all OpenACC routines in order
+ to call shared memory-layout hook.
+ * target.def (create_worker_broadcast_record): Add OFFSET
+ parameter.
+ (shared_mem_layout): New hook.
+
+2021-09-17 Julian Brown <julian@codesourcery.com>
+ Thomas Schwinge <thomas@codesourcery.com>
+
+ * omp-oacc-neuter-broadcast.cc
+ (pass_omp_oacc_neuter_broadcast::gate): Disable if num_workers is
+ 1.
+ (execute_omp_oacc_neuter_broadcast): Adjust.
+
+2021-09-17 Andrew MacLeod <amacleod@redhat.com>
+
+ * value-relation.cc (class equiv_chain): Move to header file.
+ (path_oracle::path_oracle): New.
+ (path_oracle::~path_oracle): New.
+ (path_oracle::register_relation): New.
+ (path_oracle::query_relation): New.
+ (path_oracle::reset_path): New.
+ (path_oracle::dump): New.
+ * value-relation.h (class equiv_chain): Move to here.
+ (class path_oracle): New.
+
+2021-09-17 Andrew MacLeod <amacleod@redhat.com>
+
+ * gimple-range-cache.cc (ranger_cache::ranger_cache): Create a DOM
+ based oracle.
+ * gimple-range-fold.cc (fur_depend::register_relation): Use
+ register_stmt/edge routines.
+ * value-relation.cc (equiv_chain::find): Relocate from equiv_oracle.
+ (equiv_oracle::equiv_oracle): Create self equivalence cache.
+ (equiv_oracle::~equiv_oracle): Release same.
+ (equiv_oracle::equiv_set): Return entry from self equiv cache if there
+ are no equivalences.
+ (equiv_oracle::find_equiv_block): Move list find to equiv_chain.
+ (equiv_oracle::register_relation): Rename from register_equiv.
+ (relation_chain_head::find_relation): Relocate from dom_oracle.
+ (relation_oracle::register_stmt): New.
+ (relation_oracle::register_edge): New.
+ (dom_oracle::*): Rename from relation_oracle.
+ (dom_oracle::register_relation): Adjust to call equiv_oracle.
+ (dom_oracle::set_one_relation): Split from register_relation.
+ (dom_oracle::register_transitives): Consolidate 2 methods.
+ (dom_oracle::find_relation_block): Move core to relation_chain.
+ (dom_oracle::query_relation): Rename from find_relation_dom and adjust.
+ * value-relation.h (class relation_oracle): New pure virtual base.
+ (class equiv_oracle): Inherit from relation_oracle and adjust.
+ (class dom_oracle): Rename from old relation_oracle and adjust.
+
+2021-09-17 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/102200
+ * pointer-query.cc (access_ref::inform_access): Handle MIN/MAX_EXPR.
+ (handle_min_max_size): Change argument. Store original SSA_NAME for
+ operands to potentially distinct (sub)objects.
+ (compute_objsize_r): Adjust call to the above.
+
+2021-09-17 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000.c (rs6000-builtins.h): New include.
+ (rs6000_new_builtin_vectorized_function): New function.
+ (rs6000_new_builtin_md_vectorized_function): Likewise.
+ (rs6000_builtin_vectorized_function): Call
+ rs6000_new_builtin_vectorized_function.
+ (rs6000_builtin_md_vectorized_function): Call
+ rs6000_new_builtin_md_vectorized_function.
+
+2021-09-17 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-builtin-new.def (ASSEMBLE_ACC): Add mmaint flag.
+ (ASSEMBLE_PAIR): Likewise.
+ (BUILD_ACC): Likewise.
+ (DISASSEMBLE_ACC): Likewise.
+ (DISASSEMBLE_PAIR): Likewise.
+ (PMXVBF16GER2): Likewise.
+ (PMXVBF16GER2NN): Likewise.
+ (PMXVBF16GER2NP): Likewise.
+ (PMXVBF16GER2PN): Likewise.
+ (PMXVBF16GER2PP): Likewise.
+ (PMXVF16GER2): Likewise.
+ (PMXVF16GER2NN): Likewise.
+ (PMXVF16GER2NP): Likewise.
+ (PMXVF16GER2PN): Likewise.
+ (PMXVF16GER2PP): Likewise.
+ (PMXVF32GER): Likewise.
+ (PMXVF32GERNN): Likewise.
+ (PMXVF32GERNP): Likewise.
+ (PMXVF32GERPN): Likewise.
+ (PMXVF32GERPP): Likewise.
+ (PMXVF64GER): Likewise.
+ (PMXVF64GERNN): Likewise.
+ (PMXVF64GERNP): Likewise.
+ (PMXVF64GERPN): Likewise.
+ (PMXVF64GERPP): Likewise.
+ (PMXVI16GER2): Likewise.
+ (PMXVI16GER2PP): Likewise.
+ (PMXVI16GER2S): Likewise.
+ (PMXVI16GER2SPP): Likewise.
+ (PMXVI4GER8): Likewise.
+ (PMXVI4GER8PP): Likewise.
+ (PMXVI8GER4): Likewise.
+ (PMXVI8GER4PP): Likewise.
+ (PMXVI8GER4SPP): Likewise.
+ (XVBF16GER2): Likewise.
+ (XVBF16GER2NN): Likewise.
+ (XVBF16GER2NP): Likewise.
+ (XVBF16GER2PN): Likewise.
+ (XVBF16GER2PP): Likewise.
+ (XVF16GER2): Likewise.
+ (XVF16GER2NN): Likewise.
+ (XVF16GER2NP): Likewise.
+ (XVF16GER2PN): Likewise.
+ (XVF16GER2PP): Likewise.
+ (XVF32GER): Likewise.
+ (XVF32GERNN): Likewise.
+ (XVF32GERNP): Likewise.
+ (XVF32GERPN): Likewise.
+ (XVF32GERPP): Likewise.
+ (XVF64GER): Likewise.
+ (XVF64GERNN): Likewise.
+ (XVF64GERNP): Likewise.
+ (XVF64GERPN): Likewise.
+ (XVF64GERPP): Likewise.
+ (XVI16GER2): Likewise.
+ (XVI16GER2PP): Likewise.
+ (XVI16GER2S): Likewise.
+ (XVI16GER2SPP): Likewise.
+ (XVI4GER8): Likewise.
+ (XVI4GER8PP): Likewise.
+ (XVI8GER4): Likewise.
+ (XVI8GER4PP): Likewise.
+ (XVI8GER4SPP): Likewise.
+ (XXMFACC): Likewise.
+ (XXMTACC): Likewise.
+ (XXSETACCZ): Likewise.
+ (ASSEMBLE_PAIR_V): Likewise.
+ (BUILD_PAIR): Likewise.
+ (DISASSEMBLE_PAIR_V): Likewise.
+ (LXVP): New.
+ (STXVP): New.
+ * config/rs6000/rs6000-call.c (rs6000_gimple_fold_new_mma_builtin):
+ Handle RS6000_BIF_LXVP and RS6000_BIF_STXVP.
+ * config/rs6000/rs6000-gen-builtins.c (attrinfo): Add ismmaint.
+ (parse_bif_attrs): Handle ismmaint.
+ (write_decls): Add bif_mmaint_bit and bif_is_mmaint.
+ (write_bif_static_init): Handle ismmaint.
+
+2021-09-17 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-call.c (rs6000_gimple_fold_new_builtin): New
+ forward decl.
+ (rs6000_gimple_fold_builtin): Call rs6000_gimple_fold_new_builtin.
+ (rs6000_new_builtin_valid_without_lhs): New function.
+ (rs6000_gimple_fold_new_mma_builtin): Likewise.
+ (rs6000_gimple_fold_new_builtin): Likewise.
+
+2021-09-17 Thomas Schwinge <thomas@codesourcery.com>
+
+ * hash-table.h (hash_table<Descriptor, Lazy, Allocator>::expand):
+ Destruct stale Value objects.
+ * hash-map-tests.c (test_map_of_type_with_ctor_and_dtor_expand):
+ Update.
+
+2021-09-17 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR c/102245
+ * match.pd (shift optimizations): Disable recent sign-changing
+ optimization for shifts by zero, these will be folded later.
+
+2021-09-17 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-builtin-new.def (__builtin_mffsl): Move from
+ [power9] to [always].
+
+2021-09-17 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-stmts.c (vectorizable_load): Do not frob
+ stmt_info for SLP.
+
+2021-09-17 H.J. Lu <hjl.tools@gmail.com>
+
+ * config/i386/i386-features.c (remove_partial_avx_dependency):
+ Also check TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY and
+ and TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY before generating
+ vxorps.
+ * config/i386/i386.h (TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY):
+ New.
+ (TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Likewise.
+ * config/i386/i386.md (SSE FP to FP splitters): Replace
+ TARGET_SSE_PARTIAL_REG_DEPENDENCY with
+ TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY.
+ (SSE INT to FP splitter): Replace TARGET_SSE_PARTIAL_REG_DEPENDENCY
+ with TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY.
+ * config/i386/x86-tune.def
+ (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): New.
+ (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Likewise.
+
+2021-09-17 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/101900
+ * config/i386/i386-features.c (remove_partial_avx_dependency):
+ Check TARGET_USE_VECTOR_FP_CONVERTS and TARGET_USE_VECTOR_CONVERTS
+ before generating vxorps.
+
+2021-09-17 H.J. Lu <hjl.tools@gmail.com>
+
+ * config/i386/i386-options.c (processor_cost_table): Use
+ tremont_cost for Tremont.
+ * config/i386/x86-tune-costs.h (tremont_memcpy): New.
+ (tremont_memset): Likewise.
+ (tremont_cost): Likewise.
+ * config/i386/x86-tune.def (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB):
+ Enable for Tremont.
+
+2021-09-17 H.J. Lu <hjl.tools@gmail.com>
+
+ * common/config/i386/i386-common.c: Use Haswell scheduling model
+ for Tremont.
+ * config/i386/i386.c (ix86_sched_init_global): Prepare for Tremont
+ scheduling pass.
+ * config/i386/x86-tune-sched.c (ix86_issue_rate): Change Tremont
+ issue rate to 4.
+ (ix86_adjust_cost): Handle Tremont.
+ * config/i386/x86-tune.def (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY):
+ Enable for Tremont.
+ (X86_TUNE_USE_LEAVE): Likewise.
+ (X86_TUNE_PUSH_MEMORY): Likewise.
+ (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Likewise.
+ (X86_TUNE_USE_CLTD): Likewise.
+ (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Likewise.
+ (X86_TUNE_AVOID_MFENCE): Likewise.
+ (X86_TUNE_SSE_TYPELESS_STORES): Likewise.
+ (X86_TUNE_SSE_LOAD0_BY_PXOR): Likewise.
+ (X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Disable for Tremont.
+ (X86_TUNE_FOUR_JUMP_LIMIT): Likewise.
+ (X86_TUNE_OPT_AGU): Likewise.
+ (X86_TUNE_AVOID_LEA_FOR_ADDR): Likewise.
+ (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE): Likewise.
+ (X86_TUNE_EXPAND_ABS): Likewise.
+ (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS): Likewise.
+ (X86_TUNE_SLOW_PSHUFB): Likewise.
+
+2021-09-17 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR rtl-optimization/102306
+ * combine.c (try_combine): Abort the combination if we are about to
+ duplicate volatile references.
+
+2021-09-17 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm_undefined_ph):
+ New intrinsic.
+ (_mm256_undefined_ph): Likewise.
+ (_mm512_undefined_ph): Likewise.
+ (_mm_cvtsh_h): Likewise.
+ (_mm256_cvtsh_h): Likewise.
+ (_mm512_cvtsh_h): Likewise.
+ (_mm512_castph_ps): Likewise.
+ (_mm512_castph_pd): Likewise.
+ (_mm512_castph_si512): Likewise.
+ (_mm512_castph512_ph128): Likewise.
+ (_mm512_castph512_ph256): Likewise.
+ (_mm512_castph128_ph512): Likewise.
+ (_mm512_castph256_ph512): Likewise.
+ (_mm512_zextph128_ph512): Likewise.
+ (_mm512_zextph256_ph512): Likewise.
+ (_mm512_castps_ph): Likewise.
+ (_mm512_castpd_ph): Likewise.
+ (_mm512_castsi512_ph): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_castph_ps):
+ New intrinsic.
+ (_mm256_castph_ps): Likewise.
+ (_mm_castph_pd): Likewise.
+ (_mm256_castph_pd): Likewise.
+ (_mm_castph_si128): Likewise.
+ (_mm256_castph_si256): Likewise.
+ (_mm_castps_ph): Likewise.
+ (_mm256_castps_ph): Likewise.
+ (_mm_castpd_ph): Likewise.
+ (_mm256_castpd_ph): Likewise.
+ (_mm_castsi128_ph): Likewise.
+ (_mm256_castsi256_ph): Likewise.
+ (_mm256_castph256_ph128): Likewise.
+ (_mm256_castph128_ph256): Likewise.
+ (_mm256_zextph128_ph256): Likewise.
+
+2021-09-17 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm_cvtsh_ss):
+ New intrinsic.
+ (_mm_mask_cvtsh_ss): Likewise.
+ (_mm_maskz_cvtsh_ss): Likewise.
+ (_mm_cvtsh_sd): Likewise.
+ (_mm_mask_cvtsh_sd): Likewise.
+ (_mm_maskz_cvtsh_sd): Likewise.
+ (_mm_cvt_roundsh_ss): Likewise.
+ (_mm_mask_cvt_roundsh_ss): Likewise.
+ (_mm_maskz_cvt_roundsh_ss): Likewise.
+ (_mm_cvt_roundsh_sd): Likewise.
+ (_mm_mask_cvt_roundsh_sd): Likewise.
+ (_mm_maskz_cvt_roundsh_sd): Likewise.
+ (_mm_cvtss_sh): Likewise.
+ (_mm_mask_cvtss_sh): Likewise.
+ (_mm_maskz_cvtss_sh): Likewise.
+ (_mm_cvtsd_sh): Likewise.
+ (_mm_mask_cvtsd_sh): Likewise.
+ (_mm_maskz_cvtsd_sh): Likewise.
+ (_mm_cvt_roundss_sh): Likewise.
+ (_mm_mask_cvt_roundss_sh): Likewise.
+ (_mm_maskz_cvt_roundss_sh): Likewise.
+ (_mm_cvt_roundsd_sh): Likewise.
+ (_mm_mask_cvt_roundsd_sh): Likewise.
+ (_mm_maskz_cvt_roundsd_sh): Likewise.
+ * config/i386/i386-builtin-types.def
+ (V8HF_FTYPE_V2DF_V8HF_V8HF_UQI_INT,
+ V8HF_FTYPE_V4SF_V8HF_V8HF_UQI_INT,
+ V2DF_FTYPE_V8HF_V2DF_V2DF_UQI_INT,
+ V4SF_FTYPE_V8HF_V4SF_V4SF_UQI_INT): Add new builtin types.
+ * config/i386/i386-builtin.def: Add corrresponding new builtins.
+ * config/i386/i386-expand.c: Handle new builtin types.
+ * config/i386/sse.md (VF48_128): New mode iterator.
+ (avx512fp16_vcvtsh2<ssescalarmodesuffix><mask_scalar_name><round_saeonly_scalar_name>):
+ New.
+ (avx512fp16_vcvt<ssescalarmodesuffix>2sh<mask_scalar_name><round_scalar_name>):
+ Ditto.
+
+2021-09-17 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm512_cvtph_pd):
+ New intrinsic.
+ (_mm512_mask_cvtph_pd): Likewise.
+ (_mm512_maskz_cvtph_pd): Likewise.
+ (_mm512_cvt_roundph_pd): Likewise.
+ (_mm512_mask_cvt_roundph_pd): Likewise.
+ (_mm512_maskz_cvt_roundph_pd): Likewise.
+ (_mm512_cvtxph_ps): Likewise.
+ (_mm512_mask_cvtxph_ps): Likewise.
+ (_mm512_maskz_cvtxph_ps): Likewise.
+ (_mm512_cvtx_roundph_ps): Likewise.
+ (_mm512_mask_cvtx_roundph_ps): Likewise.
+ (_mm512_maskz_cvtx_roundph_ps): Likewise.
+ (_mm512_cvtxps_ph): Likewise.
+ (_mm512_mask_cvtxps_ph): Likewise.
+ (_mm512_maskz_cvtxps_ph): Likewise.
+ (_mm512_cvtx_roundps_ph): Likewise.
+ (_mm512_mask_cvtx_roundps_ph): Likewise.
+ (_mm512_maskz_cvtx_roundps_ph): Likewise.
+ (_mm512_cvtpd_ph): Likewise.
+ (_mm512_mask_cvtpd_ph): Likewise.
+ (_mm512_maskz_cvtpd_ph): Likewise.
+ (_mm512_cvt_roundpd_ph): Likewise.
+ (_mm512_mask_cvt_roundpd_ph): Likewise.
+ (_mm512_maskz_cvt_roundpd_ph): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_cvtph_pd):
+ New intrinsic.
+ (_mm_mask_cvtph_pd): Likewise.
+ (_mm_maskz_cvtph_pd): Likewise.
+ (_mm256_cvtph_pd): Likewise.
+ (_mm256_mask_cvtph_pd): Likewise.
+ (_mm256_maskz_cvtph_pd): Likewise.
+ (_mm_cvtxph_ps): Likewise.
+ (_mm_mask_cvtxph_ps): Likewise.
+ (_mm_maskz_cvtxph_ps): Likewise.
+ (_mm256_cvtxph_ps): Likewise.
+ (_mm256_mask_cvtxph_ps): Likewise.
+ (_mm256_maskz_cvtxph_ps): Likewise.
+ (_mm_cvtxps_ph): Likewise.
+ (_mm_mask_cvtxps_ph): Likewise.
+ (_mm_maskz_cvtxps_ph): Likewise.
+ (_mm256_cvtxps_ph): Likewise.
+ (_mm256_mask_cvtxps_ph): Likewise.
+ (_mm256_maskz_cvtxps_ph): Likewise.
+ (_mm_cvtpd_ph): Likewise.
+ (_mm_mask_cvtpd_ph): Likewise.
+ (_mm_maskz_cvtpd_ph): Likewise.
+ (_mm256_cvtpd_ph): Likewise.
+ (_mm256_mask_cvtpd_ph): Likewise.
+ (_mm256_maskz_cvtpd_ph): Likewise.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/i386-builtin-types.def: Add corresponding builtin types.
+ * config/i386/i386-expand.c: Handle new builtin types.
+ * config/i386/sse.md
+ (VF4_128_8_256): New.
+ (VF48H_AVX512VL): Ditto.
+ (ssePHmode): Add HF vector modes.
+ (castmode): Add new convertable modes.
+ (qq2phsuff): Ditto.
+ (ph2pssuffix): New.
+ (avx512fp16_vcvt<castmode>2ph_<mode><mask_name><round_name>): Ditto.
+ (avx512fp16_vcvt<castmode>2ph_<mode>): Ditto.
+ (*avx512fp16_vcvt<castmode>2ph_<mode>): Ditto.
+ (avx512fp16_vcvt<castmode>2ph_<mode>_mask): Ditto.
+ (*avx512fp16_vcvt<castmode>2ph_<mode>_mask): Ditto.
+ (*avx512fp16_vcvt<castmode>2ph_<mode>_mask_1): Ditto.
+ (avx512fp16_float_extend_ph<mode>2<mask_name><round_saeonly_name>):
+ Ditto.
+ (avx512fp16_float_extend_ph<mode>2<mask_name>): Ditto.
+ (*avx512fp16_float_extend_ph<mode>2_load<mask_name>): Ditto.
+ (avx512fp16_float_extend_phv2df2<mask_name>): Ditto.
+ (*avx512fp16_float_extend_phv2df2_load<mask_name>): Ditto.
+
+2021-09-17 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm_cvttsh_i32):
+ New intrinsic.
+ (_mm_cvttsh_u32): Likewise.
+ (_mm_cvtt_roundsh_i32): Likewise.
+ (_mm_cvtt_roundsh_u32): Likewise.
+ (_mm_cvttsh_i64): Likewise.
+ (_mm_cvttsh_u64): Likewise.
+ (_mm_cvtt_roundsh_i64): Likewise.
+ (_mm_cvtt_roundsh_u64): Likewise.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/sse.md
+ (avx512fp16_fix<fixunssuffix>_trunc<mode>2<round_saeonly_name>):
+ New.
+
+2021-09-17 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm512_cvttph_epi32):
+ New intrinsic.
+ (_mm512_mask_cvttph_epi32): Likewise.
+ (_mm512_maskz_cvttph_epi32): Likewise.
+ (_mm512_cvtt_roundph_epi32): Likewise.
+ (_mm512_mask_cvtt_roundph_epi32): Likewise.
+ (_mm512_maskz_cvtt_roundph_epi32): Likewise.
+ (_mm512_cvttph_epu32): Likewise.
+ (_mm512_mask_cvttph_epu32): Likewise.
+ (_mm512_maskz_cvttph_epu32): Likewise.
+ (_mm512_cvtt_roundph_epu32): Likewise.
+ (_mm512_mask_cvtt_roundph_epu32): Likewise.
+ (_mm512_maskz_cvtt_roundph_epu32): Likewise.
+ (_mm512_cvttph_epi64): Likewise.
+ (_mm512_mask_cvttph_epi64): Likewise.
+ (_mm512_maskz_cvttph_epi64): Likewise.
+ (_mm512_cvtt_roundph_epi64): Likewise.
+ (_mm512_mask_cvtt_roundph_epi64): Likewise.
+ (_mm512_maskz_cvtt_roundph_epi64): Likewise.
+ (_mm512_cvttph_epu64): Likewise.
+ (_mm512_mask_cvttph_epu64): Likewise.
+ (_mm512_maskz_cvttph_epu64): Likewise.
+ (_mm512_cvtt_roundph_epu64): Likewise.
+ (_mm512_mask_cvtt_roundph_epu64): Likewise.
+ (_mm512_maskz_cvtt_roundph_epu64): Likewise.
+ (_mm512_cvttph_epi16): Likewise.
+ (_mm512_mask_cvttph_epi16): Likewise.
+ (_mm512_maskz_cvttph_epi16): Likewise.
+ (_mm512_cvtt_roundph_epi16): Likewise.
+ (_mm512_mask_cvtt_roundph_epi16): Likewise.
+ (_mm512_maskz_cvtt_roundph_epi16): Likewise.
+ (_mm512_cvttph_epu16): Likewise.
+ (_mm512_mask_cvttph_epu16): Likewise.
+ (_mm512_maskz_cvttph_epu16): Likewise.
+ (_mm512_cvtt_roundph_epu16): Likewise.
+ (_mm512_mask_cvtt_roundph_epu16): Likewise.
+ (_mm512_maskz_cvtt_roundph_epu16): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_cvttph_epi32):
+ New intirnsic.
+ (_mm_mask_cvttph_epi32): Likewise.
+ (_mm_maskz_cvttph_epi32): Likewise.
+ (_mm256_cvttph_epi32): Likewise.
+ (_mm256_mask_cvttph_epi32): Likewise.
+ (_mm256_maskz_cvttph_epi32): Likewise.
+ (_mm_cvttph_epu32): Likewise.
+ (_mm_mask_cvttph_epu32): Likewise.
+ (_mm_maskz_cvttph_epu32): Likewise.
+ (_mm256_cvttph_epu32): Likewise.
+ (_mm256_mask_cvttph_epu32): Likewise.
+ (_mm256_maskz_cvttph_epu32): Likewise.
+ (_mm_cvttph_epi64): Likewise.
+ (_mm_mask_cvttph_epi64): Likewise.
+ (_mm_maskz_cvttph_epi64): Likewise.
+ (_mm256_cvttph_epi64): Likewise.
+ (_mm256_mask_cvttph_epi64): Likewise.
+ (_mm256_maskz_cvttph_epi64): Likewise.
+ (_mm_cvttph_epu64): Likewise.
+ (_mm_mask_cvttph_epu64): Likewise.
+ (_mm_maskz_cvttph_epu64): Likewise.
+ (_mm256_cvttph_epu64): Likewise.
+ (_mm256_mask_cvttph_epu64): Likewise.
+ (_mm256_maskz_cvttph_epu64): Likewise.
+ (_mm_cvttph_epi16): Likewise.
+ (_mm_mask_cvttph_epi16): Likewise.
+ (_mm_maskz_cvttph_epi16): Likewise.
+ (_mm256_cvttph_epi16): Likewise.
+ (_mm256_mask_cvttph_epi16): Likewise.
+ (_mm256_maskz_cvttph_epi16): Likewise.
+ (_mm_cvttph_epu16): Likewise.
+ (_mm_mask_cvttph_epu16): Likewise.
+ (_mm_maskz_cvttph_epu16): Likewise.
+ (_mm256_cvttph_epu16): Likewise.
+ (_mm256_mask_cvttph_epu16): Likewise.
+ (_mm256_maskz_cvttph_epu16): Likewise.
+ * config/i386/i386-builtin.def: Add new builtins.
+ * config/i386/sse.md
+ (avx512fp16_fix<fixunssuffix>_trunc<mode>2<mask_name><round_saeonly_name>):
+ New.
+ (avx512fp16_fix<fixunssuffix>_trunc<mode>2<mask_name>): Ditto.
+ (*avx512fp16_fix<fixunssuffix>_trunc<mode>2_load<mask_name>): Ditto.
+ (avx512fp16_fix<fixunssuffix>_truncv2di2<mask_name>): Ditto.
+ (avx512fp16_fix<fixunssuffix>_truncv2di2_load<mask_name>): Ditto.
+
+2021-09-17 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm_cvtsh_i32): New intrinsic.
+ (_mm_cvtsh_u32): Likewise.
+ (_mm_cvt_roundsh_i32): Likewise.
+ (_mm_cvt_roundsh_u32): Likewise.
+ (_mm_cvtsh_i64): Likewise.
+ (_mm_cvtsh_u64): Likewise.
+ (_mm_cvt_roundsh_i64): Likewise.
+ (_mm_cvt_roundsh_u64): Likewise.
+ (_mm_cvti32_sh): Likewise.
+ (_mm_cvtu32_sh): Likewise.
+ (_mm_cvt_roundi32_sh): Likewise.
+ (_mm_cvt_roundu32_sh): Likewise.
+ (_mm_cvti64_sh): Likewise.
+ (_mm_cvtu64_sh): Likewise.
+ (_mm_cvt_roundi64_sh): Likewise.
+ (_mm_cvt_roundu64_sh): Likewise.
+ * config/i386/i386-builtin-types.def: Add corresponding builtin types.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/i386-expand.c (ix86_expand_round_builtin):
+ Handle new builtin types.
+ * config/i386/sse.md
+ (avx512fp16_vcvtsh2<sseintconvertsignprefix>si<rex64namesuffix><round_name>):
+ New define_insn.
+ (avx512fp16_vcvtsh2<sseintconvertsignprefix>si<rex64namesuffix>_2): Likewise.
+ (avx512fp16_vcvt<floatsuffix>si2sh<rex64namesuffix><round_name>): Likewise.
+
+2021-09-16 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-c.c (rs6000-builtins.h): New include.
+ (altivec_resolve_new_overloaded_builtin): New forward decl.
+ (rs6000_new_builtin_type_compatible): New function.
+ (altivec_resolve_overloaded_builtin): Call
+ altivec_resolve_new_overloaded_builtin.
+ (altivec_build_new_resolved_builtin): New function.
+ (altivec_resolve_new_overloaded_builtin): Likewise.
+ * config/rs6000/rs6000-call.c (rs6000_new_builtin_is_supported):
+ Likewise.
+ * config/rs6000/rs6000-gen-builtins.c (write_decls): Remove _p from
+ name of rs6000_new_builtin_is_supported.
+
+2021-09-16 Uroš Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386-protos.h (ix86_decompose_address):
+ Change return type to bool.
+ * config/i386/i386.c (ix86_decompose_address): Ditto.
+
+2021-09-16 Tobias Burnus <tobias@codesourcery.com>
+
+ PR target/102353
+ * config/rs6000/t-rs6000 (build/rs6000-gen-builtins.o, build/rbtree.o):
+ Added 'build/' to target, use build/%.o rule.
+ (build/rs6000-gen-builtins$(build_exeext)): Add 'build/' and
+ '$(build_exeext)' to target and 'build/' for the *.o files.
+ (rs6000-builtins.c): Update for those changes; run rs6000-gen-builtins
+ with $(RUN_GEN).
+
+2021-09-16 Martin Jambor <mjambor@suse.cz>
+
+ * cgraph.c (cgraph_node::dump): Do not check caller count sums if
+ the body has been removed. Remove trailing whitespace.
+
+2021-09-16 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/102360
+ * internal-fn.c (expand_DEFERRED_INIT): Make pattern-init
+ of non-memory more robust.
+
+2021-09-16 Daniel Cederman <cederman@gaisler.com>
+
+ * config/sparc/sparc-opts.h (enum sparc_processor_type): Add LEON5
+ * config/sparc/sparc.c (struct processor_costs): Add LEON5 costs
+ (leon5_adjust_cost): Increase cost of store with data dependency
+ on ALU instruction and FPU anti-dependencies.
+ (sparc_option_override): Add LEON5 costs
+ (sparc_adjust_cost): Add LEON5 cost adjustments
+ * config/sparc/sparc.h: Add LEON5
+ * config/sparc/sparc.md: Include LEON5 scheduling information
+ * config/sparc/sparc.opt: Add LEON5
+ * doc/invoke.texi: Add LEON5
+ * config/sparc/leon5.md: New file.
+
+2021-09-16 Daniel Cederman <cederman@gaisler.com>
+
+ * config/sparc/sparc.md (stack_protect_set32): Add NOP to prevent
+ sensitive sequence for B2BST errata workaround.
+
+2021-09-16 Daniel Cederman <cederman@gaisler.com>
+
+ * config/sparc/sparc.c (sparc_do_work_around_errata): Do not begin
+ functions with atomic instruction in the UT700 errata workaround.
+
+2021-09-16 Daniel Cederman <cederman@gaisler.com>
+
+ * config/sparc/sparc.c (next_active_non_empty_insn): New function
+ that returns next active non empty assembly instruction.
+ (sparc_do_work_around_errata): Use new function.
+
+2021-09-16 Daniel Cederman <cederman@gaisler.com>
+
+ * config/sparc/sparc.c (store_insn_p): Add predicate for store
+ attributes.
+ (load_insn_p): Add predicate for load attributes.
+ (sparc_do_work_around_errata): Use new predicates.
+
+2021-09-16 Andreas Larsson <andreas@gaisler.com>
+
+ * config/sparc/sparc.c (dump_target_flag_bits): Print bit names for
+ LEON and LEON3.
+
+2021-09-16 Martin Liska <mliska@suse.cz>
+
+ * config/mips/netbsd.h: Fix typo in name of a macro.
+
+2021-09-16 liuhongt <hongtao.liu@intel.com>
+
+ PR middle-end/102080
+ * match.pd: Check mask type when doing cond_op related gimple
+ simplification.
+ * tree.c (is_truth_type_for): New function.
+ * tree.h (is_truth_type_for): New declaration.
+
+2021-09-16 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm512_cvtepi32_ph): New
+ intrinsic.
+ (_mm512_mask_cvtepi32_ph): Likewise.
+ (_mm512_maskz_cvtepi32_ph): Likewise.
+ (_mm512_cvt_roundepi32_ph): Likewise.
+ (_mm512_mask_cvt_roundepi32_ph): Likewise.
+ (_mm512_maskz_cvt_roundepi32_ph): Likewise.
+ (_mm512_cvtepu32_ph): Likewise.
+ (_mm512_mask_cvtepu32_ph): Likewise.
+ (_mm512_maskz_cvtepu32_ph): Likewise.
+ (_mm512_cvt_roundepu32_ph): Likewise.
+ (_mm512_mask_cvt_roundepu32_ph): Likewise.
+ (_mm512_maskz_cvt_roundepu32_ph): Likewise.
+ (_mm512_cvtepi64_ph): Likewise.
+ (_mm512_mask_cvtepi64_ph): Likewise.
+ (_mm512_maskz_cvtepi64_ph): Likewise.
+ (_mm512_cvt_roundepi64_ph): Likewise.
+ (_mm512_mask_cvt_roundepi64_ph): Likewise.
+ (_mm512_maskz_cvt_roundepi64_ph): Likewise.
+ (_mm512_cvtepu64_ph): Likewise.
+ (_mm512_mask_cvtepu64_ph): Likewise.
+ (_mm512_maskz_cvtepu64_ph): Likewise.
+ (_mm512_cvt_roundepu64_ph): Likewise.
+ (_mm512_mask_cvt_roundepu64_ph): Likewise.
+ (_mm512_maskz_cvt_roundepu64_ph): Likewise.
+ (_mm512_cvtepi16_ph): Likewise.
+ (_mm512_mask_cvtepi16_ph): Likewise.
+ (_mm512_maskz_cvtepi16_ph): Likewise.
+ (_mm512_cvt_roundepi16_ph): Likewise.
+ (_mm512_mask_cvt_roundepi16_ph): Likewise.
+ (_mm512_maskz_cvt_roundepi16_ph): Likewise.
+ (_mm512_cvtepu16_ph): Likewise.
+ (_mm512_mask_cvtepu16_ph): Likewise.
+ (_mm512_maskz_cvtepu16_ph): Likewise.
+ (_mm512_cvt_roundepu16_ph): Likewise.
+ (_mm512_mask_cvt_roundepu16_ph): Likewise.
+ (_mm512_maskz_cvt_roundepu16_ph): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_cvtepi32_ph): New
+ intrinsic.
+ (_mm_mask_cvtepi32_ph): Likewise.
+ (_mm_maskz_cvtepi32_ph): Likewise.
+ (_mm256_cvtepi32_ph): Likewise.
+ (_mm256_mask_cvtepi32_ph): Likewise.
+ (_mm256_maskz_cvtepi32_ph): Likewise.
+ (_mm_cvtepu32_ph): Likewise.
+ (_mm_mask_cvtepu32_ph): Likewise.
+ (_mm_maskz_cvtepu32_ph): Likewise.
+ (_mm256_cvtepu32_ph): Likewise.
+ (_mm256_mask_cvtepu32_ph): Likewise.
+ (_mm256_maskz_cvtepu32_ph): Likewise.
+ (_mm_cvtepi64_ph): Likewise.
+ (_mm_mask_cvtepi64_ph): Likewise.
+ (_mm_maskz_cvtepi64_ph): Likewise.
+ (_mm256_cvtepi64_ph): Likewise.
+ (_mm256_mask_cvtepi64_ph): Likewise.
+ (_mm256_maskz_cvtepi64_ph): Likewise.
+ (_mm_cvtepu64_ph): Likewise.
+ (_mm_mask_cvtepu64_ph): Likewise.
+ (_mm_maskz_cvtepu64_ph): Likewise.
+ (_mm256_cvtepu64_ph): Likewise.
+ (_mm256_mask_cvtepu64_ph): Likewise.
+ (_mm256_maskz_cvtepu64_ph): Likewise.
+ (_mm_cvtepi16_ph): Likewise.
+ (_mm_mask_cvtepi16_ph): Likewise.
+ (_mm_maskz_cvtepi16_ph): Likewise.
+ (_mm256_cvtepi16_ph): Likewise.
+ (_mm256_mask_cvtepi16_ph): Likewise.
+ (_mm256_maskz_cvtepi16_ph): Likewise.
+ (_mm_cvtepu16_ph): Likewise.
+ (_mm_mask_cvtepu16_ph): Likewise.
+ (_mm_maskz_cvtepu16_ph): Likewise.
+ (_mm256_cvtepu16_ph): Likewise.
+ (_mm256_mask_cvtepu16_ph): Likewise.
+ (_mm256_maskz_cvtepu16_ph): Likewise.
+ * config/i386/i386-builtin-types.def: Add corresponding builtin types.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/i386-expand.c
+ (ix86_expand_args_builtin): Handle new builtin types.
+ (ix86_expand_round_builtin): Ditto.
+ * config/i386/i386-modes.def: Declare V2HF and V6HF.
+ * config/i386/sse.md (VI2H_AVX512VL): New.
+ (qq2phsuff): Ditto.
+ (sseintvecmode): Add HF vector modes.
+ (avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode><mask_name><round_name>):
+ New.
+ (avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>): Ditto.
+ (*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>): Ditto.
+ (avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask): Ditto.
+ (*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask): Ditto.
+ (*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask_1): Ditto.
+ (avx512fp16_vcvt<floatsuffix>qq2ph_v2di): Ditto.
+ (*avx512fp16_vcvt<floatsuffix>qq2ph_v2di): Ditto.
+ (avx512fp16_vcvt<floatsuffix>qq2ph_v2di_mask): Ditto.
+ (*avx512fp16_vcvt<floatsuffix>qq2ph_v2di_mask): Ditto.
+ (*avx512fp16_vcvt<floatsuffix>qq2ph_v2di_mask_1): Ditto.
+ * config/i386/subst.md (round_qq2phsuff): New subst_attr.
+
+2021-09-16 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm512_cvtph_epi32):
+ New intrinsic/
+ (_mm512_mask_cvtph_epi32): Likewise.
+ (_mm512_maskz_cvtph_epi32): Likewise.
+ (_mm512_cvt_roundph_epi32): Likewise.
+ (_mm512_mask_cvt_roundph_epi32): Likewise.
+ (_mm512_maskz_cvt_roundph_epi32): Likewise.
+ (_mm512_cvtph_epu32): Likewise.
+ (_mm512_mask_cvtph_epu32): Likewise.
+ (_mm512_maskz_cvtph_epu32): Likewise.
+ (_mm512_cvt_roundph_epu32): Likewise.
+ (_mm512_mask_cvt_roundph_epu32): Likewise.
+ (_mm512_maskz_cvt_roundph_epu32): Likewise.
+ (_mm512_cvtph_epi64): Likewise.
+ (_mm512_mask_cvtph_epi64): Likewise.
+ (_mm512_maskz_cvtph_epi64): Likewise.
+ (_mm512_cvt_roundph_epi64): Likewise.
+ (_mm512_mask_cvt_roundph_epi64): Likewise.
+ (_mm512_maskz_cvt_roundph_epi64): Likewise.
+ (_mm512_cvtph_epu64): Likewise.
+ (_mm512_mask_cvtph_epu64): Likewise.
+ (_mm512_maskz_cvtph_epu64): Likewise.
+ (_mm512_cvt_roundph_epu64): Likewise.
+ (_mm512_mask_cvt_roundph_epu64): Likewise.
+ (_mm512_maskz_cvt_roundph_epu64): Likewise.
+ (_mm512_cvtph_epi16): Likewise.
+ (_mm512_mask_cvtph_epi16): Likewise.
+ (_mm512_maskz_cvtph_epi16): Likewise.
+ (_mm512_cvt_roundph_epi16): Likewise.
+ (_mm512_mask_cvt_roundph_epi16): Likewise.
+ (_mm512_maskz_cvt_roundph_epi16): Likewise.
+ (_mm512_cvtph_epu16): Likewise.
+ (_mm512_mask_cvtph_epu16): Likewise.
+ (_mm512_maskz_cvtph_epu16): Likewise.
+ (_mm512_cvt_roundph_epu16): Likewise.
+ (_mm512_mask_cvt_roundph_epu16): Likewise.
+ (_mm512_maskz_cvt_roundph_epu16): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_cvtph_epi32):
+ New intrinsic.
+ (_mm_mask_cvtph_epi32): Likewise.
+ (_mm_maskz_cvtph_epi32): Likewise.
+ (_mm256_cvtph_epi32): Likewise.
+ (_mm256_mask_cvtph_epi32): Likewise.
+ (_mm256_maskz_cvtph_epi32): Likewise.
+ (_mm_cvtph_epu32): Likewise.
+ (_mm_mask_cvtph_epu32): Likewise.
+ (_mm_maskz_cvtph_epu32): Likewise.
+ (_mm256_cvtph_epu32): Likewise.
+ (_mm256_mask_cvtph_epu32): Likewise.
+ (_mm256_maskz_cvtph_epu32): Likewise.
+ (_mm_cvtph_epi64): Likewise.
+ (_mm_mask_cvtph_epi64): Likewise.
+ (_mm_maskz_cvtph_epi64): Likewise.
+ (_mm256_cvtph_epi64): Likewise.
+ (_mm256_mask_cvtph_epi64): Likewise.
+ (_mm256_maskz_cvtph_epi64): Likewise.
+ (_mm_cvtph_epu64): Likewise.
+ (_mm_mask_cvtph_epu64): Likewise.
+ (_mm_maskz_cvtph_epu64): Likewise.
+ (_mm256_cvtph_epu64): Likewise.
+ (_mm256_mask_cvtph_epu64): Likewise.
+ (_mm256_maskz_cvtph_epu64): Likewise.
+ (_mm_cvtph_epi16): Likewise.
+ (_mm_mask_cvtph_epi16): Likewise.
+ (_mm_maskz_cvtph_epi16): Likewise.
+ (_mm256_cvtph_epi16): Likewise.
+ (_mm256_mask_cvtph_epi16): Likewise.
+ (_mm256_maskz_cvtph_epi16): Likewise.
+ (_mm_cvtph_epu16): Likewise.
+ (_mm_mask_cvtph_epu16): Likewise.
+ (_mm_maskz_cvtph_epu16): Likewise.
+ (_mm256_cvtph_epu16): Likewise.
+ (_mm256_mask_cvtph_epu16): Likewise.
+ (_mm256_maskz_cvtph_epu16): Likewise.
+ * config/i386/i386-builtin-types.def: Add new builtin types.
+ * config/i386/i386-builtin.def: Add new builtins.
+ * config/i386/i386-expand.c
+ (ix86_expand_args_builtin): Handle new builtin types.
+ (ix86_expand_round_builtin): Ditto.
+ * config/i386/sse.md (sseintconvert): New.
+ (ssePHmode): Ditto.
+ (UNSPEC_US_FIX_NOTRUNC): Ditto.
+ (sseintconvertsignprefix): Ditto.
+ (avx512fp16_vcvtph2<sseintconvertsignprefix><sseintconvert>_<mode><mask_name><round_name>):
+ Ditto.
+
+2021-09-16 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h: (_mm_cvtsi16_si128):
+ New intrinsic.
+ (_mm_cvtsi128_si16): Likewise.
+ (_mm_mask_load_sh): Likewise.
+ (_mm_maskz_load_sh): Likewise.
+ (_mm_mask_store_sh): Likewise.
+ (_mm_move_sh): Likewise.
+ (_mm_mask_move_sh): Likewise.
+ (_mm_maskz_move_sh): Likewise.
+ * config/i386/i386-builtin-types.def: Add corresponding builtin types.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/i386-expand.c
+ (ix86_expand_special_args_builtin): Handle new builtin types.
+ (ix86_expand_vector_init_one_nonzero): Adjust for FP16 target.
+ * config/i386/sse.md (VI2F): New mode iterator.
+ (vec_set<mode>_0): Use new mode iterator.
+ (avx512f_mov<ssescalarmodelower>_mask): Adjust for HF vector mode.
+ (avx512f_store<mode>_mask): Ditto.
+
+2021-09-16 Kewen Lin <linkw@linux.ibm.com>
+
+ * config/rs6000/rs6000.opt (-mtoc-fusion): Remove.
+
+2021-09-15 David Edelsohn <dje.gcc@gmail.com>
+
+ * config/rs6000/rs6000.c (rs6000_xcoff_encode_section_info):
+ Proceed if no symbol summary or the symbol alias flag is false.
+
+2021-09-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/88578
+ PR c++/102295
+ * varasm.c (output_constructor_regular_field): Instead of assertion
+ that array_size_for_constructor result is equal to size of
+ TREE_TYPE (local->val) in bytes, assert that the type size is greater
+ or equal to array_size_for_constructor result and use type size as
+ fieldsize.
+
+2021-09-15 Martin Liska <mliska@suse.cz>
+
+ PR target/102351
+ * config/i386/vxworks.h: Use new macro TARGET_CPU_P.
+
+2021-09-15 Martin Liska <mliska@suse.cz>
+
+ PR target/102349
+ * config/rs6000/rs6000.c (rs6000_xcoff_encode_section_info):
+ Check that we have a symbol summary for a symbol.
+
+2021-09-15 Richard Biener <rguenther@suse.de>
+
+ PR target/102348
+ * config/rs6000/lynx.h: Remove undef of PREFERRED_DEBUGGING_TYPE
+ to inherit from elfos.h
+
+2021-09-15 liuhongt <hongtao.liu@intel.com>
+
+ PR target/102327
+ * config/i386/i386-expand.c
+ (ix86_expand_vector_init_interleave): Use puncklwd to pack 2
+ HFmodes.
+ (ix86_expand_vector_set): Use blendw instead of pinsrw.
+ * config/i386/i386.c (ix86_can_change_mode_class): Adjust for
+ AVX512FP16 which supports 16bit vector load.
+ * config/i386/sse.md (avx512bw_interleave_highv32hi<mask_name>):
+ Rename to ..
+ (avx512bw_interleave_high<mode><mask_name>): .. this, and
+ extend to V32HFmode.
+ (avx2_interleave_highv16hi<mask_name>): Rename to ..
+ (avx2_interleave_high<mode><mask_name>): .. this, and extend
+ to V16HFmode.
+ (vec_interleave_highv8hi<mask_name>): Rename to ..
+ (vec_interleave_high<mode><mask_name>): .. this, and extend to V8HFmode.
+ (<mask_codefor>avx512bw_interleave_lowv32hi<mask_name>):
+ Rename to ..
+ (<mask_codefor>avx512bw_interleave_low<mode><mask_name>):
+ this, and extend to V32HFmode.
+ (avx2_interleave_lowv16hi<mask_name>): Rename to ..
+ (avx2_interleave_low<mode><mask_name>): .. this, and extend to V16HFmode.
+ (vec_interleave_lowv8hi<mask_name>): Rename to ..
+ (vec_interleave_low<mode><mask_name>): .. this, and extend to V8HFmode.
+ (sse4_1_pblendw): Rename to ..
+ (sse4_1_pblend<blendsuf>): .. this, and extend to V8HFmode.
+ (avx2_pblendph): New define_expand.
+ (<sse2p4_1>_pinsr<ssemodesuffix>): Refactor, use
+ sseintmodesuffix instead of ssemodesuffix.
+ (blendsuf): New mode attr.
+
+2021-09-15 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (dr_misalignment): Move out of line.
+ (dr_target_alignment): New.
+ (DR_TARGET_ALIGNMENT): Wrap dr_target_alignment.
+ (set_dr_target_alignment): New.
+ (SET_DR_TARGET_ALIGNMENT): Wrap set_dr_target_alignment.
+ * tree-vect-data-refs.c (dr_misalignment): Compute and
+ return the group members misalignment.
+ (vect_compute_data_ref_alignment): Use SET_DR_TARGET_ALIGNMENT.
+ (vect_analyze_data_refs_alignment): Compute alignment only
+ for the first element of a DR group.
+ (vect_slp_analyze_node_alignment): Likewise.
+
+2021-09-15 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/avx512fp16intrin.h: Adjust all builtin calls.
+ * config/i386/avx512fp16vlintrin.h: Likewise.
+ * config/i386/i386-builtin.def: Adjust builtin name and
+ enumeration to match AVX512F style.
+
+2021-09-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102318
+ * tree-vect-loop.c (vect_transform_cycle_phi): Revert
+ previous change and do the mode conversion separately from
+ the sign conversion.
+
+2021-09-15 Hongtao Liu <hongtao.liu@intel.com>
+ Peter Cordes <peter@cordes.ca>
+
+ PR target/91103
+ * config/i386/sse.md (extract_suf): Add V8SF/V8SI/V4DF/V4DI.
+ (*vec_extract<mode><ssescalarmodelower>_valign): Output
+ vextract{i,f}{32x4,64x2} instruction when byte_offset % 16 ==
+ 0.
+
+2021-09-15 Richard Biener <rguenther@suse.de>
+
+ * config.gcc: Remove vax-*-openbsd* configuration.
+
+2021-09-15 Richard Biener <rguenther@suse.de>
+
+ * config.gcc: Remove m68k-openbsd.
+
+2021-09-15 Max Filippov <jcmvbkbc@gmail.com>
+
+ PR target/102336
+ * config/xtensa/t-xtensa (TM_H): Add include/xtensa-config.h.
+
+2021-09-14 Peter Bergner <bergner@linux.ibm.com>
+
+ * config/rs6000/mma.md (unspec): Delete UNSPEC_MMA_XXSETACCZ.
+ (unspecv): Add UNSPECV_MMA_XXSETACCZ.
+ (*mma_xxsetaccz): Delete.
+ (mma_xxsetaccz): Change to define_insn. Remove operand 1.
+ Use UNSPECV_MMA_XXSETACCZ. Update comment.
+ * config/rs6000/rs6000.c (rs6000_rtx_costs): Use UNSPECV_MMA_XXSETACCZ.
+
+2021-09-14 Iain Sandoe <iain@sandoe.co.uk>
+
+ * Makefile.in: Remove variables related to applying no-PIE
+ to the exes on $build.
+ * configure: Regenerate.
+ * configure.ac: Remove configuration related to applying
+ no-PIE to the exes on $build.
+
+2021-09-14 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc.md (doloop_end): Add missing mode.
+ (loop_end): Likewise.
+
+2021-09-14 Jakub Jelinek <jakub@redhat.com>
+
+ * gimplify.c (goa_stabilize_expr): Add depth argument, propagate
+ it to recursive calls, for depth above 7 just gimplify or return.
+ Perform a test even for MODIFY_EXPR, ADDR_EXPR, COMPOUND_EXPR with
+ __builtin_clear_padding and TARGET_EXPR.
+ (gimplify_omp_atomic): Adjust goa_stabilize_expr callers.
+
+2021-09-14 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm_fpclass_sh_mask):
+ New intrinsic.
+ (_mm_mask_fpclass_sh_mask): Likewise.
+ (_mm512_mask_fpclass_ph_mask): Likewise.
+ (_mm512_fpclass_ph_mask): Likewise.
+ (_mm_getexp_sh): Likewise.
+ (_mm_mask_getexp_sh): Likewise.
+ (_mm_maskz_getexp_sh): Likewise.
+ (_mm512_getexp_ph): Likewise.
+ (_mm512_mask_getexp_ph): Likewise.
+ (_mm512_maskz_getexp_ph): Likewise.
+ (_mm_getexp_round_sh): Likewise.
+ (_mm_mask_getexp_round_sh): Likewise.
+ (_mm_maskz_getexp_round_sh): Likewise.
+ (_mm512_getexp_round_ph): Likewise.
+ (_mm512_mask_getexp_round_ph): Likewise.
+ (_mm512_maskz_getexp_round_ph): Likewise.
+ (_mm_getmant_sh): Likewise.
+ (_mm_mask_getmant_sh): Likewise.
+ (_mm_maskz_getmant_sh): Likewise.
+ (_mm512_getmant_ph): Likewise.
+ (_mm512_mask_getmant_ph): Likewise.
+ (_mm512_maskz_getmant_ph): Likewise.
+ (_mm_getmant_round_sh): Likewise.
+ (_mm_mask_getmant_round_sh): Likewise.
+ (_mm_maskz_getmant_round_sh): Likewise.
+ (_mm512_getmant_round_ph): Likewise.
+ (_mm512_mask_getmant_round_ph): Likewise.
+ (_mm512_maskz_getmant_round_ph): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_mask_fpclass_ph_mask):
+ New intrinsic.
+ (_mm_fpclass_ph_mask): Likewise.
+ (_mm256_mask_fpclass_ph_mask): Likewise.
+ (_mm256_fpclass_ph_mask): Likewise.
+ (_mm256_getexp_ph): Likewise.
+ (_mm256_mask_getexp_ph): Likewise.
+ (_mm256_maskz_getexp_ph): Likewise.
+ (_mm_getexp_ph): Likewise.
+ (_mm_mask_getexp_ph): Likewise.
+ (_mm_maskz_getexp_ph): Likewise.
+ (_mm256_getmant_ph): Likewise.
+ (_mm256_mask_getmant_ph): Likewise.
+ (_mm256_maskz_getmant_ph): Likewise.
+ (_mm_getmant_ph): Likewise.
+ (_mm_mask_getmant_ph): Likewise.
+ (_mm_maskz_getmant_ph): Likewise.
+ * config/i386/i386-builtin-types.def: Add corresponding builtin types.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/i386-expand.c
+ (ix86_expand_args_builtin): Handle new builtin types.
+ (ix86_expand_round_builtin): Ditto.
+ * config/i386/sse.md (vecmemsuffix): Add HF vector modes.
+ (<avx512>_getexp<mode><mask_name><round_saeonly_name>): Adjust
+ to support HF vector modes.
+ (avx512f_sgetexp<mode><mask_scalar_name><round_saeonly_scalar_name):
+ Ditto.
+ (avx512dq_fpclass<mode><mask_scalar_merge_name>): Ditto.
+ (avx512dq_vmfpclass<mode><mask_scalar_merge_name>): Ditto.
+ (<avx512>_getmant<mode><mask_name><round_saeonly_name>): Ditto.
+ (avx512f_vgetmant<mode><mask_scalar_name><round_saeonly_scalar_name>):
+ Ditto.
+
+2021-09-14 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h (_mm512_reduce_ph):
+ New intrinsic.
+ (_mm512_mask_reduce_ph): Likewise.
+ (_mm512_maskz_reduce_ph): Likewise.
+ (_mm512_reduce_round_ph): Likewise.
+ (_mm512_mask_reduce_round_ph): Likewise.
+ (_mm512_maskz_reduce_round_ph): Likewise.
+ (_mm_reduce_sh): Likewise.
+ (_mm_mask_reduce_sh): Likewise.
+ (_mm_maskz_reduce_sh): Likewise.
+ (_mm_reduce_round_sh): Likewise.
+ (_mm_mask_reduce_round_sh): Likewise.
+ (_mm_maskz_reduce_round_sh): Likewise.
+ (_mm512_roundscale_ph): Likewise.
+ (_mm512_mask_roundscale_ph): Likewise.
+ (_mm512_maskz_roundscale_ph): Likewise.
+ (_mm512_roundscale_round_ph): Likewise.
+ (_mm512_mask_roundscale_round_ph): Likewise.
+ (_mm512_maskz_roundscale_round_ph): Likewise.
+ (_mm_roundscale_sh): Likewise.
+ (_mm_mask_roundscale_sh): Likewise.
+ (_mm_maskz_roundscale_sh): Likewise.
+ (_mm_roundscale_round_sh): Likewise.
+ (_mm_mask_roundscale_round_sh): Likewise.
+ (_mm_maskz_roundscale_round_sh): Likewise.
+ * config/i386/avx512fp16vlintrin.h: (_mm_reduce_ph):
+ New intrinsic.
+ (_mm_mask_reduce_ph): Likewise.
+ (_mm_maskz_reduce_ph): Likewise.
+ (_mm256_reduce_ph): Likewise.
+ (_mm256_mask_reduce_ph): Likewise.
+ (_mm256_maskz_reduce_ph): Likewise.
+ (_mm_roundscale_ph): Likewise.
+ (_mm_mask_roundscale_ph): Likewise.
+ (_mm_maskz_roundscale_ph): Likewise.
+ (_mm256_roundscale_ph): Likewise.
+ (_mm256_mask_roundscale_ph): Likewise.
+ (_mm256_maskz_roundscale_ph): Likewise.
+ * config/i386/i386-builtin-types.def: Add corresponding builtin types.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/i386-expand.c
+ (ix86_expand_args_builtin): Handle new builtin types.
+ (ix86_expand_round_builtin): Ditto.
+ * config/i386/sse.md (<mask_codefor>reducep<mode><mask_name>):
+ Renamed to ...
+ (<mask_codefor>reducep<mode><mask_name><round_saeonly_name>):
+ ... this, and adjust for round operands.
+ (reduces<mode><mask_scalar_name>): Likewise, with ...
+ (reduces<mode><mask_scalar_name><round_saeonly_scalar_name):
+ ... this.
+ (<avx512>_rndscale<mode><mask_name><round_saeonly_name>):
+ Adjust for HF vector modes.
+ (avx512f_rndscale<mode><mask_scalar_name><round_saeonly_scalar_name>):
+ Ditto.
+ (*avx512f_rndscale<mode><round_saeonly_name>): Ditto.
+
+2021-09-14 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h: (_mm512_rcp_ph):
+ New intrinsic.
+ (_mm512_mask_rcp_ph): Likewise.
+ (_mm512_maskz_rcp_ph): Likewise.
+ (_mm_rcp_sh): Likewise.
+ (_mm_mask_rcp_sh): Likewise.
+ (_mm_maskz_rcp_sh): Likewise.
+ (_mm512_scalef_ph): Likewise.
+ (_mm512_mask_scalef_ph): Likewise.
+ (_mm512_maskz_scalef_ph): Likewise.
+ (_mm512_scalef_round_ph): Likewise.
+ (_mm512_mask_scalef_round_ph): Likewise.
+ (_mm512_maskz_scalef_round_ph): Likewise.
+ (_mm_scalef_sh): Likewise.
+ (_mm_mask_scalef_sh): Likewise.
+ (_mm_maskz_scalef_sh): Likewise.
+ (_mm_scalef_round_sh): Likewise.
+ (_mm_mask_scalef_round_sh): Likewise.
+ (_mm_maskz_scalef_round_sh): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_rcp_ph):
+ New intrinsic.
+ (_mm256_rcp_ph): Likewise.
+ (_mm_mask_rcp_ph): Likewise.
+ (_mm256_mask_rcp_ph): Likewise.
+ (_mm_maskz_rcp_ph): Likewise.
+ (_mm256_maskz_rcp_ph): Likewise.
+ (_mm_scalef_ph): Likewise.
+ (_mm256_scalef_ph): Likewise.
+ (_mm_mask_scalef_ph): Likewise.
+ (_mm256_mask_scalef_ph): Likewise.
+ (_mm_maskz_scalef_ph): Likewise.
+ (_mm256_maskz_scalef_ph): Likewise.
+ * config/i386/i386-builtin.def: Add new builtins.
+ * config/i386/sse.md (VFH_AVX512VL): New.
+ (avx512fp16_rcp<mode>2<mask_name>): Ditto.
+ (avx512fp16_vmrcpv8hf2<mask_scalar_name>): Ditto.
+ (avx512f_vmscalef<mode><mask_scalar_name><round_scalar_name>):
+ Adjust to support HF vector modes.
+ (<avx512>_scalef<mode><mask_name><round_name>): Ditto.
+
+2021-09-14 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h: (_mm512_sqrt_ph):
+ New intrinsic.
+ (_mm512_mask_sqrt_ph): Likewise.
+ (_mm512_maskz_sqrt_ph): Likewise.
+ (_mm512_sqrt_round_ph): Likewise.
+ (_mm512_mask_sqrt_round_ph): Likewise.
+ (_mm512_maskz_sqrt_round_ph): Likewise.
+ (_mm512_rsqrt_ph): Likewise.
+ (_mm512_mask_rsqrt_ph): Likewise.
+ (_mm512_maskz_rsqrt_ph): Likewise.
+ (_mm_rsqrt_sh): Likewise.
+ (_mm_mask_rsqrt_sh): Likewise.
+ (_mm_maskz_rsqrt_sh): Likewise.
+ (_mm_sqrt_sh): Likewise.
+ (_mm_mask_sqrt_sh): Likewise.
+ (_mm_maskz_sqrt_sh): Likewise.
+ (_mm_sqrt_round_sh): Likewise.
+ (_mm_mask_sqrt_round_sh): Likewise.
+ (_mm_maskz_sqrt_round_sh): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_sqrt_ph): New intrinsic.
+ (_mm256_sqrt_ph): Likewise.
+ (_mm_mask_sqrt_ph): Likewise.
+ (_mm256_mask_sqrt_ph): Likewise.
+ (_mm_maskz_sqrt_ph): Likewise.
+ (_mm256_maskz_sqrt_ph): Likewise.
+ (_mm_rsqrt_ph): Likewise.
+ (_mm256_rsqrt_ph): Likewise.
+ (_mm_mask_rsqrt_ph): Likewise.
+ (_mm256_mask_rsqrt_ph): Likewise.
+ (_mm_maskz_rsqrt_ph): Likewise.
+ (_mm256_maskz_rsqrt_ph): Likewise.
+ * config/i386/i386-builtin-types.def: Add corresponding builtin types.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/i386-expand.c
+ (ix86_expand_args_builtin): Handle new builtins.
+ (ix86_expand_round_builtin): Ditto.
+ * config/i386/sse.md (VF_AVX512FP16VL): New.
+ (sqrt<mode>2): Adjust for HF vector modes.
+ (<sse>_sqrt<mode>2<mask_name><round_name>): Likewise.
+ (<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>):
+ Likewise.
+ (<sse>_rsqrt<mode>2<mask_name>): New.
+ (avx512fp16_vmrsqrtv8hf2<mask_scalar_name>): Likewise.
+
+2021-09-13 Thomas Schwinge <thomas@codesourcery.com>
+
+ PR bootstrap/101574
+ * diagnostic-spec.c (warning_suppressed_at, copy_warning): Handle
+ 'RESERVED_LOCATION_P' locations.
+ * warning-control.cc (get_nowarn_spec, suppress_warning)
+ (copy_warning): Likewise.
+
+2021-09-13 Thomas Schwinge <thomas@codesourcery.com>
+
+ * diagnostic-spec.h (typedef xint_hash_t): Use 'location_t' instead of...
+ (typedef key_type_t): ... this. Remove.
+ (nowarn_map): Document.
+ * diagnostic-spec.c (nowarn_map): Likewise.
+ * warning-control.cc (convert_to_key): Evolve functions into...
+ (get_location): ... these. Adjust all users.
+
+2021-09-13 Thomas Schwinge <thomas@codesourcery.com>
+
+ * warning-control.cc (copy_warning): Remove 'nowarn_map' setup.
+
+2021-09-13 Jason Merrill <jason@redhat.com>
+
+ * params.opt: Add destructive-interference-size and
+ constructive-interference-size.
+ * doc/invoke.texi: Document them.
+ * config/aarch64/aarch64.c (aarch64_override_options_internal):
+ Set them.
+ * config/arm/arm.c (arm_option_override): Set them.
+ * config/i386/i386-options.c (ix86_option_override_internal):
+ Set them.
+
+2021-09-13 Martin Liska <mliska@suse.cz>
+ H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/101696
+ * common/config/i386/cpuinfo.h (cpu_indicator_init): Add support
+ for x86-64 micro levels for __builtin_cpu_supports.
+ * common/config/i386/i386-cpuinfo.h (enum feature_priority):
+ Add priorities for the micro-arch levels.
+ (enum processor_features): Add new features.
+ * common/config/i386/i386-isas.h: Add micro-arch features.
+ * config/i386/i386-builtins.c (get_builtin_code_for_version):
+ Support the micro-arch levels by callsing
+ __builtin_cpu_supports.
+ * doc/extend.texi: Document that the levels are support by
+ __builtin_cpu_supports.
+
+2021-09-13 Andrew Pinski <apinski@marvell.com>
+
+ PR target/95969
+ * config/aarch64/aarch64-builtins.c (aarch64_fold_builtin_lane_check):
+ New function.
+ (aarch64_general_fold_builtin): Handle AARCH64_SIMD_BUILTIN_LANE_CHECK.
+ (aarch64_general_gimple_fold_builtin): Likewise.
+
+2021-09-13 Andrew Pinski <apinski@marvell.com>
+
+ * config.gcc: Add m32r-*-linux* and m32rle-*-linux*
+ to the Unsupported targets list.
+ Remove support for m32r-*-linux* and m32rle-*-linux*.
+ * config/m32r/linux.h: Removed.
+ * config/m32r/t-linux: Removed.
+
+2021-09-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/102252
+ * config/aarch64/aarch64.c (aarch64_classify_address): Don't allow
+ register index for SVE predicate modes.
+
+2021-09-13 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c
+ (back_threader_profitability::profitable_path_p): Remove FSM
+ references.
+ (back_threader_registry::register_path): Same.
+ * tree-ssa-threadedge.c
+ (jump_threader::simplify_control_stmt_condition): Same.
+ * tree-ssa-threadupdate.c (jt_path_registry::jt_path_registry):
+ Add backedge_threads argument.
+ (fwd_jt_path_registry::fwd_jt_path_registry): Pass
+ backedge_threads argument.
+ (back_jt_path_registry::back_jt_path_registry): Same.
+ (dump_jump_thread_path): Adjust for FSM removal.
+ (back_jt_path_registry::rewire_first_differing_edge): Same.
+ (back_jt_path_registry::adjust_paths_after_duplication): Same.
+ (back_jt_path_registry::update_cfg): Same.
+ (jt_path_registry::register_jump_thread): Same.
+ * tree-ssa-threadupdate.h (enum jump_thread_edge_type): Remove
+ EDGE_FSM_THREAD.
+ (class back_jt_path_registry): Add backedge_threads to
+ constructor.
+
+2021-09-13 Martin Liska <mliska@suse.cz>
+
+ PR c++/101331
+ * asan.h (sanitize_coverage_p): Handle when fn == NULL.
+
+2021-09-13 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/101935
+ * config/i386/i386.h (TARGET_AVX256_MOVE_BY_PIECES): New.
+ (TARGET_AVX256_STORE_BY_PIECES): Likewise.
+ (MOVE_MAX): Check TARGET_AVX256_MOVE_BY_PIECES and
+ TARGET_AVX256_STORE_BY_PIECES instead of
+ TARGET_AVX256_SPLIT_UNALIGNED_LOAD and
+ TARGET_AVX256_SPLIT_UNALIGNED_STORE.
+ (STORE_MAX_PIECES): Check TARGET_AVX256_STORE_BY_PIECES instead
+ of TARGET_AVX256_SPLIT_UNALIGNED_STORE.
+ * config/i386/x86-tune.def (X86_TUNE_AVX256_MOVE_BY_PIECES): New.
+ (X86_TUNE_AVX256_STORE_BY_PIECES): Likewise.
+
+2021-09-13 liuhongt <hongtao.liu@intel.com>
+
+ PR bootstrap/102302
+ * expmed.c (extract_bit_field_using_extv): Use
+ gen_lowpart_if_possible instead of gen_lowpart to avoid ICE.
+
+2021-09-13 Aldy Hernandez <aldyh@redhat.com>
+
+ * Makefile.in (OBJS): Add value-pointer-equiv.o.
+ * gimple-ssa-evrp.c (class ssa_equiv_stack): Move to
+ value-pointer-equiv.*.
+ (ssa_equiv_stack::ssa_equiv_stack): Same.
+ (ssa_equiv_stack::enter): Same.
+ (ssa_equiv_stack::leave): Same.
+ (ssa_equiv_stack::push_replacement): Same.
+ (ssa_equiv_stack::get_replacement): Same.
+ (is_pointer_ssa): Same.
+ (class pointer_equiv_analyzer): Same.
+ (pointer_equiv_analyzer::pointer_equiv_analyzer): Same.
+ (pointer_equiv_analyzer::~pointer_equiv_analyzer): Same.
+ (pointer_equiv_analyzer::set_global_equiv): Same.
+ (pointer_equiv_analyzer::set_cond_equiv): Same.
+ (pointer_equiv_analyzer::get_equiv): Same.
+ (pointer_equiv_analyzer::enter): Same.
+ (pointer_equiv_analyzer::leave): Same.
+ (pointer_equiv_analyzer::get_equiv_expr): Same.
+ (pta_valueize): Same.
+ (pointer_equiv_analyzer::visit_stmt): Same.
+ (pointer_equiv_analyzer::visit_edge): Same.
+ (hybrid_folder::value_of_expr): Same.
+ (hybrid_folder::value_on_edge): Same.
+ * value-pointer-equiv.cc: New file.
+ * value-pointer-equiv.h: New file.
+
+2021-09-13 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/102125
+ * gimple-fold.c (gimple_fold_builtin_memory_op): Allow folding
+ memcpy if the size is not more than MOVE_MAX * MOVE_RATIO.
+
+2021-09-13 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/102125
+ * config/arm/arm.md (movmisaligndi): New define_expand.
+ * config/arm/vec-common.md (movmisalign<mode>): Iterate over VDQ mode.
+
+2021-09-13 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/102125
+ * emit-rtl.c (gen_highpart): Use adjust_address to handle
+ MEM rather than calling simplify_gen_subreg.
+
+2021-09-13 Jan-Benedict Glaw <jbglaw@ług-owl.de>
+
+ * config/alpha/vms.h (INIT_CUMULATIVE_ARGS): Wrap multi-statment
+ define into a block.
+
+2021-09-13 Richard Biener <rguenther@suse.de>
+
+ * config/darwin.h (DARWIN_PREFER_DWARF): Do not define.
+ * config/i386/darwin.h (PREFERRED_DEBUGGING_TYPE): Do not
+ change based on DARWIN_PREFER_DWARF not being defined.
+
+2021-09-13 Richard Biener <rguenther@suse.de>
+
+ * config/i386/lynx.h: Remove undef of PREFERRED_DEBUGGING_TYPE
+ to inherit from elfos.h
+
+2021-09-13 Richard Biener <rguenther@suse.de>
+
+ * config.gcc: Add cr16-*-* to the list of obsoleted targets.
+
+2021-09-13 Richard Biener <rguenther@suse.de>
+
+ * config/avr/elf.h (PREFERRED_DEBUGGING_TYPE): Remove
+ override, pick up DWARF2_DEBUG define from elfos.h
+
+2021-09-13 Richard Biener <rguenther@suse.de>
+
+ * config/rx/rx.h (PREFERRED_DEBUGGING_TYPE): Always define to
+ DWARF2_DEBUG.
+
+2021-09-13 Richard Biener <rguenther@suse.de>
+
+ * config/alpha/vms.h (PREFERRED_DEBUGGING_TYPE): Define to
+ DWARF2_DEBUG.
+
+2021-09-13 Richard Biener <rguenther@suse.de>
+
+ * config/i386/cygming.h: Always default to DWARF2 debugging.
+ Do not define DBX_DEBUGGING_INFO, that's done via dbxcoff.h
+ already.
+ * doc/install.texi: Document binutils 2.16 as minimum
+ requirement for mingw.
+
+2021-09-13 Kewen Lin <linkw@linux.ibm.com>
+
+ * config/rs6000/rs6000.c (struct rs6000_cost_data): New members
+ nstmts, nloads and extra_ctor_cost.
+ (rs6000_density_test): Add load density related heuristics. Do
+ extra costing on vector construction statements if need.
+ (rs6000_init_cost): Init new members.
+ (rs6000_update_target_cost_per_stmt): New function.
+ (rs6000_add_stmt_cost): Factor vect_nonmem hunk out to function
+ rs6000_update_target_cost_per_stmt and call it.
+
+2021-09-13 Kewen Lin <linkw@linux.ibm.com>
+
+ * config/rs6000/rs6000.c (struct rs6000_cost_data): Remove typedef.
+ (rs6000_init_cost): Adjust.
+
+2021-09-13 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/i386.md: (UNSPEC_COPYSIGN): Remove.
+ (UNSPEC_XORSIGN): Ditto.
+
+2021-09-12 Roger Sayle <roger@nextmovesoftware.com>
+
+ * expr.c (convert_move): Preserve SUBREG_PROMOTED_VAR_P when
+ creating a (wider) partial subreg from a SUBREG_PROMOTED_VAR_P
+ subreg.
+
+2021-09-11 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-ssa-threadbackward.c (class back_threader_registry): Use
+ back_jt_path_registry.
+ * tree-ssa-threadedge.c (jump_threader::jump_threader): Use
+ fwd_jt_path_registry.
+ * tree-ssa-threadedge.h (class jump_threader): Same..
+ * tree-ssa-threadupdate.c
+ (jump_thread_path_registry::jump_thread_path_registry): Rename...
+ (jt_path_registry::jt_path_registry): ...to this.
+ (jump_thread_path_registry::~jump_thread_path_registry): Rename...
+ (jt_path_registry::~jt_path_registry): ...this.
+ (fwd_jt_path_registry::fwd_jt_path_registry): New.
+ (fwd_jt_path_registry::~fwd_jt_path_registry): New.
+ (jump_thread_path_registry::allocate_thread_edge): Rename...
+ (jt_path_registry::allocate_thread_edge): ...to this.
+ (jump_thread_path_registry::allocate_thread_path): Rename...
+ (jt_path_registry::allocate_thread_path): ...to this.
+ (jump_thread_path_registry::lookup_redirection_data): Rename...
+ (fwd_jt_path_registry::lookup_redirection_data): ...to this.
+ (jump_thread_path_registry::thread_block_1): Rename...
+ (fwd_jt_path_registry::thread_block_1): ...to this.
+ (jump_thread_path_registry::thread_block): Rename...
+ (fwd_jt_path_registry::thread_block): ...to this.
+ (jt_path_registry::thread_through_loop_header): Rename...
+ (fwd_jt_path_registry::thread_through_loop_header): ...to this.
+ (jump_thread_path_registry::mark_threaded_blocks): Rename...
+ (fwd_jt_path_registry::mark_threaded_blocks): ...to this.
+ (jump_thread_path_registry::debug_path): Rename...
+ (jt_path_registry::debug_path): ...to this.
+ (jump_thread_path_registry::dump): Rename...
+ (jt_path_registry::debug): ...to this.
+ (jump_thread_path_registry::rewire_first_differing_edge): Rename...
+ (back_jt_path_registry::rewire_first_differing_edge): ...to this.
+ (jump_thread_path_registry::adjust_paths_after_duplication): Rename...
+ (back_jt_path_registry::adjust_paths_after_duplication): ...to this.
+ (jump_thread_path_registry::duplicate_thread_path): Rename...
+ (back_jt_path_registry::duplicate_thread_path): ...to this. Also,
+ drop ill-formed candidates.
+ (jump_thread_path_registry::remove_jump_threads_including): Rename...
+ (fwd_jt_path_registry::remove_jump_threads_including): ...to this.
+ (jt_path_registry::thread_through_all_blocks): New.
+ (back_jt_path_registry::update_cfg): New.
+ (fwd_jt_path_registry::update_cfg): New.
+ (jump_thread_path_registry::register_jump_thread): Rename...
+ (jt_path_registry::register_jump_thread): ...to this.
+ * tree-ssa-threadupdate.h (class jump_thread_path_registry):
+ Abstract to...
+ (class jt_path_registry): ...here.
+ (class fwd_jt_path_registry): New.
+ (class back_jt_path_registry): New.
+
+2021-09-10 liuhongt <hongtao.liu@intel.com>
+
+ Revert:
+ 2021-09-01 liuhongt <hongtao.liu@intel.com>
+
+ * emit-rtl.c (validate_subreg): Get rid of all float-int
+ special cases.
+
+2021-09-10 Jakub Jelinek <jakub@redhat.com>
+
+ * tree-core.h (enum omp_memory_order): Add OMP_MEMORY_ORDER_MASK,
+ OMP_FAIL_MEMORY_ORDER_UNSPECIFIED, OMP_FAIL_MEMORY_ORDER_RELAXED,
+ OMP_FAIL_MEMORY_ORDER_ACQUIRE, OMP_FAIL_MEMORY_ORDER_RELEASE,
+ OMP_FAIL_MEMORY_ORDER_ACQ_REL, OMP_FAIL_MEMORY_ORDER_SEQ_CST and
+ OMP_FAIL_MEMORY_ORDER_MASK enumerators.
+ (OMP_FAIL_MEMORY_ORDER_SHIFT): Define.
+ * gimple-pretty-print.c (dump_gimple_omp_atomic_load,
+ dump_gimple_omp_atomic_store): Print [weak] for weak atomic
+ load/store.
+ * gimple.h (enum gf_mask): Change GF_OMP_ATOMIC_MEMORY_ORDER
+ to 6-bit mask, adjust GF_OMP_ATOMIC_NEED_VALUE value and add
+ GF_OMP_ATOMIC_WEAK.
+ (gimple_omp_atomic_weak_p, gimple_omp_atomic_set_weak): New inline
+ functions.
+ * tree.h (OMP_ATOMIC_WEAK): Define.
+ * tree-pretty-print.c (dump_omp_atomic_memory_order): Adjust for
+ fail memory order being encoded in the same enum and also print
+ fail clause if present.
+ (dump_generic_node): Print weak clause if OMP_ATOMIC_WEAK.
+ * gimplify.c (goa_stabilize_expr): Add target_expr and rhs arguments,
+ handle pre_p == NULL case as a test mode that only returns value
+ but doesn't change gimplify nor change anything otherwise, adjust
+ recursive calls, add MODIFY_EXPR, ADDR_EXPR, COND_EXPR, TARGET_EXPR
+ and CALL_EXPR handling, adjust COMPOUND_EXPR handling for
+ __builtin_clear_padding calls, for !rhs gimplify as lvalue rather
+ than rvalue.
+ (gimplify_omp_atomic): Adjust goa_stabilize_expr caller. Handle
+ COND_EXPR rhs. Set weak flag on gimple load/store for
+ OMP_ATOMIC_WEAK.
+ * omp-expand.c (omp_memory_order_to_fail_memmodel): New function.
+ (omp_memory_order_to_memmodel): Adjust for fail clause encoded
+ in the same enum.
+ (expand_omp_atomic_cas): New function.
+ (expand_omp_atomic_pipeline): Use omp_memory_order_to_fail_memmodel
+ function.
+ (expand_omp_atomic): Attempt to optimize atomic compare and exchange
+ using expand_omp_atomic_cas.
+
+2021-09-10 Aldy Hernandez <aldyh@redhat.com>
+ Michael Matz <matz@suse.de>
+
+ * tree-pass.h (PROP_loop_opts_done): New.
+ * gimple-range-path.cc (path_range_query::internal_range_of_expr):
+ Intersect with global range.
+ * tree-ssa-loop.c (tree_ssa_loop_done): Set PROP_loop_opts_done.
+ * tree-ssa-threadbackward.c
+ (back_threader_profitability::profitable_path_p): Disable
+ threading through latches until after loop optimizations have run.
+
+2021-09-10 David Faust <david.faust@oracle.com>
+
+ * doc/invoke.texi: Document BPF -mcpu, -mjmpext, -mjmp32 and -malu32
+ options.
+
+2021-09-10 David Faust <david.faust@oracle.com>
+
+ * config/bpf/bpf-opts.h (bpf_isa_version): New enum.
+ * config/bpf/bpf-protos.h (bpf_expand_cbranch): New.
+ * config/bpf/bpf.c (bpf_option_override): Handle -mcpu option.
+ (bpf_expand_cbranch): New function.
+ * config/bpf/bpf.md (AM mode iterator): Conditionalize support for SI
+ mode.
+ (zero_extendsidi2): Only use mov32 instruction if it is available.
+ (SIM mode iterator): Conditionalize support for SI mode.
+ (JM mode iterator): New.
+ (cbranchdi4): Update name, use new JM iterator. Use bpf_expand_cbranch.
+ (*branch_on_di): Update name, use new JM iterator.
+ * config/bpf/bpf.opt: (mjmpext): New option.
+ (malu32): Likewise.
+ (mjmp32): Likewise.
+ (mcpu): Likewise.
+ (bpf_isa): New enum.
+
+2021-09-10 David Faust <david.faust@oracle.com>
+
+ * config/bpf/bpf.md (zero_extendhidi2): Add new output template
+ for register-to-register extensions.
+ (zero_extendqidi2): Likewise.
+
+2021-09-10 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/102273
+ * internal-fn.c (expand_DEFERRED_INIT): Always expand non-SSA vars.
+
+2021-09-10 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/102269
+ * gimplify.c (is_var_need_auto_init): Empty types do not need
+ initialization.
+
+2021-09-10 Richard Biener <rguenther@suse.de>
+
+ * configure.ac (--with-stabs): Remove.
+ * configure: Regenerate.
+ * doc/install.texi: Remove --with-stabs documentation.
+
+2021-09-10 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h: (_mm512_cmp_ph_mask):
+ New intrinsic.
+ (_mm512_mask_cmp_ph_mask): Likewise.
+ (_mm512_cmp_round_ph_mask): Likewise.
+ (_mm512_mask_cmp_round_ph_mask): Likewise.
+ (_mm_cmp_sh_mask): Likewise.
+ (_mm_mask_cmp_sh_mask): Likewise.
+ (_mm_cmp_round_sh_mask): Likewise.
+ (_mm_mask_cmp_round_sh_mask): Likewise.
+ (_mm_comieq_sh): Likewise.
+ (_mm_comilt_sh): Likewise.
+ (_mm_comile_sh): Likewise.
+ (_mm_comigt_sh): Likewise.
+ (_mm_comige_sh): Likewise.
+ (_mm_comineq_sh): Likewise.
+ (_mm_ucomieq_sh): Likewise.
+ (_mm_ucomilt_sh): Likewise.
+ (_mm_ucomile_sh): Likewise.
+ (_mm_ucomigt_sh): Likewise.
+ (_mm_ucomige_sh): Likewise.
+ (_mm_ucomineq_sh): Likewise.
+ (_mm_comi_round_sh): Likewise.
+ (_mm_comi_sh): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_cmp_ph_mask): New intrinsic.
+ (_mm_mask_cmp_ph_mask): Likewise.
+ (_mm256_cmp_ph_mask): Likewise.
+ (_mm256_mask_cmp_ph_mask): Likewise.
+ * config/i386/i386-builtin-types.def: Add corresponding builtin types.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/i386-expand.c
+ (ix86_expand_args_builtin): Handle new builtin types.
+ (ix86_expand_round_builtin): Ditto.
+ * config/i386/i386.md (ssevecmode): Add HF mode.
+ (MODEFH): New mode iterator.
+ * config/i386/sse.md
+ (V48H_AVX512VL): New mode iterator to support HF vector modes.
+ Ajdust corresponding description.
+ (ssecmpintprefix): New.
+ (VI12_AVX512VL): Adjust to support HF vector modes.
+ (cmp_imm_predicate): Likewise.
+ (<avx512>_cmp<mode>3<mask_scalar_merge_name><round_saeonly_name>):
+ Likewise.
+ (avx512f_vmcmp<mode>3<round_saeonly_name>): Likewise.
+ (avx512f_vmcmp<mode>3_mask<round_saeonly_name>): Likewise.
+ (<sse>_<unord>comi<round_saeonly_name>): Likewise.
+
+2021-09-10 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/avx512fp16intrin.h: (_mm512_max_ph): New intrinsic.
+ (_mm512_mask_max_ph): Likewise.
+ (_mm512_maskz_max_ph): Likewise.
+ (_mm512_min_ph): Likewise.
+ (_mm512_mask_min_ph): Likewise.
+ (_mm512_maskz_min_ph): Likewise.
+ (_mm512_max_round_ph): Likewise.
+ (_mm512_mask_max_round_ph): Likewise.
+ (_mm512_maskz_max_round_ph): Likewise.
+ (_mm512_min_round_ph): Likewise.
+ (_mm512_mask_min_round_ph): Likewise.
+ (_mm512_maskz_min_round_ph): Likewise.
+ (_mm_max_sh): Likewise.
+ (_mm_mask_max_sh): Likewise.
+ (_mm_maskz_max_sh): Likewise.
+ (_mm_min_sh): Likewise.
+ (_mm_mask_min_sh): Likewise.
+ (_mm_maskz_min_sh): Likewise.
+ (_mm_max_round_sh): Likewise.
+ (_mm_mask_max_round_sh): Likewise.
+ (_mm_maskz_max_round_sh): Likewise.
+ (_mm_min_round_sh): Likewise.
+ (_mm_mask_min_round_sh): Likewise.
+ (_mm_maskz_min_round_sh): Likewise.
+ * config/i386/avx512fp16vlintrin.h (_mm_max_ph): New intrinsic.
+ (_mm256_max_ph): Likewise.
+ (_mm_mask_max_ph): Likewise.
+ (_mm256_mask_max_ph): Likewise.
+ (_mm_maskz_max_ph): Likewise.
+ (_mm256_maskz_max_ph): Likewise.
+ (_mm_min_ph): Likewise.
+ (_mm256_min_ph): Likewise.
+ (_mm_mask_min_ph): Likewise.
+ (_mm256_mask_min_ph): Likewise.
+ (_mm_maskz_min_ph): Likewise.
+ (_mm256_maskz_min_ph): Likewise.
+ * config/i386/i386-builtin-types.def: Add corresponding builtin types.
+ * config/i386/i386-builtin.def: Add corresponding new builtins.
+ * config/i386/i386-expand.c
+ (ix86_expand_args_builtin): Handle new builtin types.
+ * config/i386/sse.md
+ (<code><mode>3<mask_name><round_saeonly_name>): Adjust to
+ support HF vector modes.
+ (*<code><mode>3<mask_name><round_saeonly_name>): Likewise.
+ (ieee_<ieee_maxmin><mode>3<mask_name><round_saeonly_name>):
+ Likewise.
+ (<sse>_vm<code><mode>3<mask_scalar_name><round_saeonly_scalar_name>):
+ Likewise.
+ * config/i386/subst.md (round_saeonly_mode512bit_condition):
+ Adjust for HF vector modes.
+
+2021-09-10 Liu, Hongtao <hongtao.liu@intel.com>
+[...]
[diff truncated at 524288 bytes]
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