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* [gcc(refs/vendors/microsoft/heads/main)] Merge commit '532fb1203554983b0395dc012fc24600cd48d370' into merge-master-532fb1203554983b0395dc012f
@ 2023-06-27 21:21 Eugene Rozenfeld
0 siblings, 0 replies; only message in thread
From: Eugene Rozenfeld @ 2023-06-27 21:21 UTC (permalink / raw)
To: gcc-cvs, libstdc++-cvs
https://gcc.gnu.org/g:4e68af223e31f0957267837b7ec09a822786b035
commit 4e68af223e31f0957267837b7ec09a822786b035
Merge: 48a89a21655 532fb120355
Author: MS Automation <gnutools@microsoft.com>
Date: Wed Jun 14 10:29:16 2023 +0000
Merge commit '532fb1203554983b0395dc012fc24600cd48d370' into merge-master-532fb1203554983b0395dc012fc24600cd48d370-2023-06-14T10-29-13
Diff:
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gcc/testsuite/gcc.target/aarch64/sve/adr_1.c | 24 +-
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gcc/testsuite/gcc.target/aarch64/sve/peel_ind_2.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/pr109505.c | 12 +
gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c | 2 +-
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gcc/testsuite/gcc.target/aarch64/sve/slp_4.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/spill_3.c | 8 +-
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gcc/testsuite/gcc.target/aarch64/sve/vcond_18.c | 14 +-
gcc/testsuite/gcc.target/aarch64/sve/vcond_19.c | 34 +-
gcc/testsuite/gcc.target/aarch64/sve/vcond_2.c | 248 +-
gcc/testsuite/gcc.target/aarch64/sve/vcond_20.c | 34 +-
gcc/testsuite/gcc.target/aarch64/sve/vcond_3.c | 26 +-
gcc/testsuite/gcc.target/aarch64/sve/vcond_7.c | 198 +-
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gcc/testsuite/gcc.target/aarch64/swar_to_vec_cmp.c | 72 +
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.../intrinsics/mve_vstore_scatter_shifted_offset.c | 141 -
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.../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +-
.../arm/mve/intrinsics/vcmpgeq_n_f32-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +-
.../arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c | 12 -
.../arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c | 12 -
.../arm/mve/intrinsics/vcmpgtq_n_f16-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 4 +-
.../arm/mve/intrinsics/vcmpgtq_n_f32-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +-
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.../arm/mve/intrinsics/vcmpleq_m_n_f16-1.c | 12 -
.../arm/mve/intrinsics/vcmpleq_m_n_f32-1.c | 12 -
.../arm/mve/intrinsics/vcmpleq_n_f16-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +-
.../arm/mve/intrinsics/vcmpleq_n_f32-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +-
.../arm/mve/intrinsics/vcmpltq_m_n_f16-1.c | 12 -
.../arm/mve/intrinsics/vcmpltq_m_n_f32-1.c | 12 -
.../arm/mve/intrinsics/vcmpltq_n_f16-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +-
.../arm/mve/intrinsics/vcmpltq_n_f32-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +-
.../arm/mve/intrinsics/vcmpneq_m_n_f16-1.c | 12 -
.../arm/mve/intrinsics/vcmpneq_m_n_f32-1.c | 12 -
.../arm/mve/intrinsics/vcmpneq_n_f16-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 2 +-
.../arm/mve/intrinsics/vcmpneq_n_f32-1.c | 12 -
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.../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 19 +-
.../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 19 +-
.../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 24 +-
.../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 24 +-
.../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 31 +-
.../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 31 +-
.../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 23 +-
.../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 23 +-
.../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 28 +-
.../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 28 +-
.../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 36 +-
.../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 36 +-
.../intrinsics/vldrdq_gather_shifted_offset_s64.c | 28 +-
.../intrinsics/vldrdq_gather_shifted_offset_u64.c | 28 +-
.../vldrdq_gather_shifted_offset_z_s64.c | 36 +-
.../vldrdq_gather_shifted_offset_z_u64.c | 36 +-
.../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 20 +-
.../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 28 +-
.../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 28 +-
.../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 28 +-
.../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 28 +-
.../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 28 +-
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.../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 36 +-
.../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 36 +-
.../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 36 +-
.../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 36 +-
.../intrinsics/vldrhq_gather_shifted_offset_f16.c | 28 +-
.../intrinsics/vldrhq_gather_shifted_offset_s16.c | 28 +-
.../intrinsics/vldrhq_gather_shifted_offset_s32.c | 28 +-
.../intrinsics/vldrhq_gather_shifted_offset_u16.c | 28 +-
.../intrinsics/vldrhq_gather_shifted_offset_u32.c | 28 +-
.../vldrhq_gather_shifted_offset_z_f16.c | 36 +-
.../vldrhq_gather_shifted_offset_z_s16.c | 36 +-
.../vldrhq_gather_shifted_offset_z_s32.c | 36 +-
.../vldrhq_gather_shifted_offset_z_u16.c | 36 +-
.../vldrhq_gather_shifted_offset_z_u32.c | 36 +-
.../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 20 +-
.../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 20 +-
.../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 20 +-
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.../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 25 +-
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.../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 19 +-
.../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 19 +-
.../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 22 +-
.../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 22 +-
.../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 22 +-
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.../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 28 +-
.../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 28 +-
.../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 23 +-
.../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 23 +-
.../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 23 +-
.../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 28 +-
.../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 28 +-
.../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 28 +-
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.../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 36 +-
.../intrinsics/vldrwq_gather_shifted_offset_f32.c | 28 +-
.../intrinsics/vldrwq_gather_shifted_offset_s32.c | 28 +-
.../intrinsics/vldrwq_gather_shifted_offset_u32.c | 28 +-
.../vldrwq_gather_shifted_offset_z_f32.c | 36 +-
.../vldrwq_gather_shifted_offset_z_s32.c | 36 +-
.../vldrwq_gather_shifted_offset_z_u32.c | 36 +-
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.../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 18 +-
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.../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 23 +-
.../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 23 +-
.../arm/mve/intrinsics/vmaxnmavq_f16-1.c | 12 -
.../arm/mve/intrinsics/vmaxnmavq_f32-1.c | 12 -
.../arm/mve/intrinsics/vmaxnmavq_p_f16-1.c | 12 -
.../arm/mve/intrinsics/vmaxnmavq_p_f32-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c | 12 -
.../arm/mve/intrinsics/vmaxnmvq_p_f16-1.c | 12 -
.../arm/mve/intrinsics/vmaxnmvq_p_f32-1.c | 12 -
.../arm/mve/intrinsics/vminnmavq_f16-1.c | 12 -
.../arm/mve/intrinsics/vminnmavq_f32-1.c | 12 -
.../arm/mve/intrinsics/vminnmavq_p_f16-1.c | 12 -
.../arm/mve/intrinsics/vminnmavq_p_f32-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c | 12 -
.../arm/mve/intrinsics/vminnmvq_p_f16-1.c | 12 -
.../arm/mve/intrinsics/vminnmvq_p_f32-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 40 +-
.../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 40 +-
.../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 40 +-
.../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 40 +-
.../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 40 +-
.../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 40 +-
.../gcc.target/arm/mve/intrinsics/vmladavq_s16.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmladavq_s32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmladavq_s8.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmladavq_u16.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmladavq_u32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmladavq_u8.c | 32 +-
.../arm/mve/intrinsics/vmladavxq_p_s16.c | 40 +-
.../arm/mve/intrinsics/vmladavxq_p_s32.c | 40 +-
.../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 40 +-
.../gcc.target/arm/mve/intrinsics/vmladavxq_s16.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmladavxq_s32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmladavxq_s8.c | 32 +-
.../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 40 +-
.../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 40 +-
.../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 56 +-
.../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 56 +-
.../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 44 +-
.../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 44 +-
.../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 2 +-
.../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 2 +-
.../arm/mve/intrinsics/vmlaldavaxq_s16.c | 2 +-
.../arm/mve/intrinsics/vmlaldavaxq_s32.c | 2 +-
.../arm/mve/intrinsics/vmlaldavq_p_s16.c | 40 +-
.../arm/mve/intrinsics/vmlaldavq_p_s32.c | 40 +-
.../arm/mve/intrinsics/vmlaldavq_p_u16.c | 40 +-
.../arm/mve/intrinsics/vmlaldavq_p_u32.c | 40 +-
.../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 32 +-
.../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 40 +-
.../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 40 +-
.../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 42 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 42 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 42 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 58 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 58 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 58 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 44 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 44 +-
.../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 44 +-
.../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 33 +-
.../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 24 +-
.../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 33 +-
.../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 33 +-
.../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c | 24 +-
.../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 32 +-
.../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c | 24 +-
.../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 32 +-
.../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c | 24 +-
.../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 32 +-
.../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 32 +-
.../arm/mve/intrinsics/vmlsldavaxq_s16.c | 24 +-
.../arm/mve/intrinsics/vmlsldavaxq_s32.c | 24 +-
.../arm/mve/intrinsics/vmlsldavq_p_s16.c | 32 +-
.../arm/mve/intrinsics/vmlsldavq_p_s32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c | 24 +-
.../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 32 +-
.../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 32 +-
.../gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_s16.c | 28 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_s8.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_u16.c | 28 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_u8.c | 28 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_s16.c | 28 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_s8.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_u16.c | 28 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_u8.c | 28 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmovntq_s16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmovntq_s32.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmovntq_u16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmovntq_u32.c | 24 +-
.../arm/mve/intrinsics/vmulq_m_n_f16-1.c | 12 -
.../arm/mve/intrinsics/vmulq_m_n_f32-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c | 12 -
.../arm/mve/intrinsics/vmulq_x_n_f16-1.c | 12 -
.../arm/mve/intrinsics/vmulq_x_n_f32-1.c | 12 -
.../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c | 37 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c | 37 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c | 37 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c | 37 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c | 33 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c | 17 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c | 19 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c | 19 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c | 19 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_s16.c | 28 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_s32.c | 28 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_s8.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_u16.c | 28 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_u32.c | 28 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_u8.c | 28 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 34 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 34 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 34 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 34 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 34 +-
.../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 34 +-
.../gcc.target/arm/mve/intrinsics/vornq_f16.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vornq_f32.c | 24 +-
.../gcc.target/arm/mve/intrinsics/vornq_m_f16.c | 34 +-
.../gcc.target/arm/mve/intrinsics/vornq_m_f32.c | 34 +-
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.../arm/mve/intrinsics/vqshluq_m_n_s16.c | 37 +-
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.../gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c | 37 +-
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.../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 38 +-
.../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 38 +-
.../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 34 +-
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.../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c | 28 +-
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.../arm/mve/intrinsics/vqshruntq_n_s16.c | 24 +-
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gcc/testsuite/gcc.target/avr/pr109907.c | 156 +
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gcc/testsuite/gcc.target/i386/pr105776.c | 43 +
gcc/testsuite/gcc.target/i386/pr108804.c | 15 +
gcc/testsuite/gcc.target/i386/pr108938-1.c | 79 +
gcc/testsuite/gcc.target/i386/pr108938-2.c | 35 +
gcc/testsuite/gcc.target/i386/pr108938-3.c | 26 +
gcc/testsuite/gcc.target/i386/pr108938-load-1.c | 69 +
gcc/testsuite/gcc.target/i386/pr108938-load-2.c | 30 +
gcc/testsuite/gcc.target/i386/pr109173-1.c | 57 +
gcc/testsuite/gcc.target/i386/pr109174-1.c | 45 +
gcc/testsuite/gcc.target/i386/pr109807.c | 4 +
gcc/testsuite/gcc.target/i386/pr109825.c | 4 +
gcc/testsuite/gcc.target/i386/pr109900.c | 95 +
gcc/testsuite/gcc.target/i386/pr109944-1.c | 30 +
gcc/testsuite/gcc.target/i386/pr109944-2.c | 17 +
gcc/testsuite/gcc.target/i386/pr109973-1.c | 13 +
gcc/testsuite/gcc.target/i386/pr109973-2.c | 13 +
gcc/testsuite/gcc.target/i386/pr110067.c | 77 +
gcc/testsuite/gcc.target/i386/pr110083.c | 26 +
gcc/testsuite/gcc.target/i386/pr110108-2.c | 14 +
gcc/testsuite/gcc.target/i386/pr110108-3.c | 22 +
gcc/testsuite/gcc.target/i386/pr110108.c | 16 +
gcc/testsuite/gcc.target/i386/pr110232.c | 12 +
gcc/testsuite/gcc.target/i386/pr64731.c | 14 +
gcc/testsuite/gcc.target/i386/pr78103-2.c | 2 +
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gcc/testsuite/gcc.target/i386/pr92658-sse4-4b.c | 26 +
gcc/testsuite/gcc.target/i386/pr92658-sse4-8b.c | 71 +
.../gcc.target/i386/sse2-shiftqihi-constant-1.c | 4 +-
gcc/testsuite/gcc.target/i386/stc-1.c | 21 +
gcc/testsuite/gcc.target/i386/vec_pack_fp16-1.c | 34 +
gcc/testsuite/gcc.target/i386/vec_pack_fp16-2.c | 9 +
gcc/testsuite/gcc.target/i386/vec_pack_fp16-3.c | 8 +
gcc/testsuite/gcc.target/i386/vect-mulv4qi.c | 24 +
gcc/testsuite/gcc.target/i386/vect-mulv8qi.c | 28 +
gcc/testsuite/gcc.target/i386/vect-shiftv4qi.c | 43 +
gcc/testsuite/gcc.target/i386/vect-shiftv8qi.c | 43 +
gcc/testsuite/gcc.target/i386/vect-vshiftv4qi.c | 28 +
gcc/testsuite/gcc.target/i386/vect-vshiftv8qi.c | 28 +
gcc/testsuite/gcc.target/nvptx/brev-1.c | 8 +
gcc/testsuite/gcc.target/nvptx/brev-2.c | 94 +
gcc/testsuite/gcc.target/nvptx/brevll-1.c | 8 +
gcc/testsuite/gcc.target/nvptx/brevll-2.c | 154 +
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.../powerpc/builtin_altivec_tr_stxvr_runnable.c | 104 +
gcc/testsuite/gcc.target/powerpc/darwin-abi-13-0.c | 23 +
gcc/testsuite/gcc.target/powerpc/darwin-abi-13-1.c | 27 +
gcc/testsuite/gcc.target/powerpc/darwin-abi-13-2.c | 27 +
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.../gcc.target/powerpc/fold-vec-extract-int.p8.c | 4 +-
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gcc/testsuite/gcc.target/powerpc/pr100106-sa.c | 16 +
gcc/testsuite/gcc.target/powerpc/pr106708.c | 10 +-
gcc/testsuite/gcc.target/powerpc/pr109566.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr109932-1.c | 17 +
gcc/testsuite/gcc.target/powerpc/pr109932-2.c | 17 +
gcc/testsuite/gcc.target/powerpc/pr110011.c | 42 +
gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c | 3 +-
gcc/testsuite/gcc.target/riscv/and-extend-1.c | 30 +
gcc/testsuite/gcc.target/riscv/and-extend-2.c | 28 +
gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +
gcc/testsuite/gcc.target/riscv/arch-21.c | 5 +
gcc/testsuite/gcc.target/riscv/pr106888.c | 12 +
gcc/testsuite/gcc.target/riscv/predef-26.c | 51 +
gcc/testsuite/gcc.target/riscv/predef-27.c | 55 +
.../gcc.target/riscv/rvv/autovec/align-1.c | 12 +
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.../gcc.target/riscv/rvv/autovec/binop/narrow-1.c | 31 +
.../gcc.target/riscv/rvv/autovec/binop/narrow-2.c | 32 +
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.../riscv/rvv/autovec/binop/narrow_run-1.c | 50 +
.../riscv/rvv/autovec/binop/narrow_run-2.c | 46 +
.../riscv/rvv/autovec/binop/narrow_run-3.c | 46 +
.../gcc.target/riscv/rvv/autovec/binop/shift-run.c | 51 +
.../riscv/rvv/autovec/binop/shift-rv32gcv.c | 12 +
.../riscv/rvv/autovec/binop/shift-rv64gcv.c | 8 +
.../riscv/rvv/autovec/binop/shift-scalar-run.c | 4 +
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.../gcc.target/riscv/rvv/autovec/binop/vadd-run.c | 69 +
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.../gcc.target/riscv/rvv/autovec/binop/vand-run.c | 69 +
.../riscv/rvv/autovec/binop/vand-rv32gcv.c | 7 +
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.../gcc.target/riscv/rvv/autovec/binop/vdiv-run.c | 47 +
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.../riscv/rvv/autovec/binop/vdiv-rv64gcv.c | 10 +
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.../gcc.target/riscv/rvv/autovec/binop/vmax-run.c | 47 +
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.../gcc.target/riscv/rvv/autovec/binop/vmin-run.c | 47 +
.../riscv/rvv/autovec/binop/vmin-rv32gcv.c | 7 +
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.../gcc.target/riscv/rvv/autovec/binop/vmul-run.c | 47 +
.../riscv/rvv/autovec/binop/vmul-rv32gcv.c | 6 +
.../riscv/rvv/autovec/binop/vmul-rv64gcv.c | 6 +
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.../gcc.target/riscv/rvv/autovec/binop/vor-run.c | 69 +
.../riscv/rvv/autovec/binop/vor-rv32gcv.c | 7 +
.../riscv/rvv/autovec/binop/vor-rv64gcv.c | 7 +
.../riscv/rvv/autovec/binop/vor-template.h | 56 +
.../gcc.target/riscv/rvv/autovec/binop/vrem-run.c | 47 +
.../riscv/rvv/autovec/binop/vrem-rv32gcv.c | 10 +
.../riscv/rvv/autovec/binop/vrem-rv64gcv.c | 10 +
.../riscv/rvv/autovec/binop/vrem-template.h | 34 +
.../gcc.target/riscv/rvv/autovec/binop/vsub-run.c | 75 +
.../riscv/rvv/autovec/binop/vsub-rv32gcv.c | 7 +
.../riscv/rvv/autovec/binop/vsub-rv64gcv.c | 7 +
.../riscv/rvv/autovec/binop/vsub-template.h | 62 +
.../gcc.target/riscv/rvv/autovec/binop/vxor-run.c | 69 +
.../riscv/rvv/autovec/binop/vxor-rv32gcv.c | 7 +
.../riscv/rvv/autovec/binop/vxor-rv64gcv.c | 7 +
.../riscv/rvv/autovec/binop/vxor-template.h | 56 +
.../gcc.target/riscv/rvv/autovec/cmp/vcond-1.c | 157 +
.../gcc.target/riscv/rvv/autovec/cmp/vcond-2.c | 75 +
.../gcc.target/riscv/rvv/autovec/cmp/vcond-3.c | 13 +
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.../gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c | 6 +
.../gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c | 35 +
.../riscv/rvv/autovec/conversions/vfcvt_rtz-run.c | 52 +
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.../riscv/rvv/autovec/conversions/vzext-run.c | 35 +
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.../riscv/rvv/autovec/conversions/vzext-rv64gcv.c | 8 +
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.../riscv/rvv/autovec/partial/multiple_rgroup-1.c | 6 +
.../riscv/rvv/autovec/partial/multiple_rgroup-1.h | 304 +
.../riscv/rvv/autovec/partial/multiple_rgroup-2.c | 6 +
.../riscv/rvv/autovec/partial/multiple_rgroup-2.h | 546 +
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.../riscv/rvv/autovec/partial/multiple_rgroup-4.c | 75 +
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.../rvv/autovec/partial/multiple_rgroup_run-4.c | 15 +
.../riscv/rvv/autovec/partial/select_vl-1.c | 26 +
.../gcc.target/riscv/rvv/autovec/partial/slp-1.c | 22 +
.../gcc.target/riscv/rvv/autovec/partial/slp-10.c | 32 +
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.../riscv/rvv/autovec/partial/slp_run-9.c | 30 +
.../gcc.target/riscv/rvv/autovec/scalable-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/series-1.c | 50 +
.../gcc.target/riscv/rvv/autovec/series_run-1.c | 20 +
.../gcc.target/riscv/rvv/autovec/ternop/ternop-1.c | 28 +
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.../riscv/rvv/autovec/ternop/ternop_run-5.c | 104 +
.../riscv/rvv/autovec/ternop/ternop_run-6.c | 104 +
.../gcc.target/riscv/rvv/autovec/unop/abs-run.c | 38 +
.../riscv/rvv/autovec/unop/abs-rv32gcv.c | 8 +
.../riscv/rvv/autovec/unop/abs-rv64gcv.c | 8 +
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.../gcc.target/riscv/rvv/autovec/unop/vneg-run.c | 29 +
.../riscv/rvv/autovec/unop/vneg-rv32gcv.c | 6 +
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gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c | 7 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c | 4 +-
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2023-06-27 21:21 [gcc(refs/vendors/microsoft/heads/main)] Merge commit '532fb1203554983b0395dc012fc24600cd48d370' into merge-master-532fb1203554983b0395dc012f Eugene Rozenfeld
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