[gcc r14-2275] Daily bump.

[gcc r14-2275] Daily bump.

[GCC Administrator]

https://gcc.gnu.org/g:092f54cb294ffc28a61a50480d7c167d787e8f85

commit r14-2275-g092f54cb294ffc28a61a50480d7c167d787e8f85
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date:   Tue Jul 4 00:17:38 2023 +0000

    Daily bump.

Diff:
---
 gcc/ChangeLog           | 255 ++++++++++++++++++++++++++++++++++++++++++++++++
 gcc/DATESTAMP           |   2 +-
 gcc/ada/ChangeLog       |  38 ++++++++
 gcc/m2/ChangeLog        |  65 ++++++++++++
 gcc/testsuite/ChangeLog | 165 +++++++++++++++++++++++++++++++
 libstdc++-v3/ChangeLog  |  23 +++++
 6 files changed, 547 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 030c97cb60c..65b6be4cbb5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,258 @@
+2023-07-03  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* common/config/riscv/riscv-common.cc: Add support for zvbb,
+	zvbc, zvkg, zvkned, zvknha, zvknhb, zvksed, zvksh, zvkn,
+	zvknc, zvkng, zvks, zvksc, zvksg, zvkt and the implied subsets.
+	* config/riscv/arch-canonicalize: Add canonicalization info for
+	zvkn, zvknc, zvkng, zvks, zvksc, zvksg.
+	* config/riscv/riscv-opts.h (MASK_ZVBB): New macro.
+	(MASK_ZVBC): Likewise.
+	(TARGET_ZVBB): Likewise.
+	(TARGET_ZVBC): Likewise.
+	(MASK_ZVKG): Likewise.
+	(MASK_ZVKNED): Likewise.
+	(MASK_ZVKNHA): Likewise.
+	(MASK_ZVKNHB): Likewise.
+	(MASK_ZVKSED): Likewise.
+	(MASK_ZVKSH): Likewise.
+	(MASK_ZVKN): Likewise.
+	(MASK_ZVKNC): Likewise.
+	(MASK_ZVKNG): Likewise.
+	(MASK_ZVKS): Likewise.
+	(MASK_ZVKSC): Likewise.
+	(MASK_ZVKSG): Likewise.
+	(MASK_ZVKT): Likewise.
+	(TARGET_ZVKG): Likewise.
+	(TARGET_ZVKNED): Likewise.
+	(TARGET_ZVKNHA): Likewise.
+	(TARGET_ZVKNHB): Likewise.
+	(TARGET_ZVKSED): Likewise.
+	(TARGET_ZVKSH): Likewise.
+	(TARGET_ZVKN): Likewise.
+	(TARGET_ZVKNC): Likewise.
+	(TARGET_ZVKNG): Likewise.
+	(TARGET_ZVKS): Likewise.
+	(TARGET_ZVKSC): Likewise.
+	(TARGET_ZVKSG): Likewise.
+	(TARGET_ZVKT): Likewise.
+	* config/riscv/riscv.opt: Introduction of riscv_zv{b,k}_subext.
+
+2023-07-03  Andrew Pinski  <apinski@marvell.com>
+
+	PR middle-end/110510
+	* except.h (struct eh_landing_pad_d): Add chain_next GTY.
+
+2023-07-03  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* config/darwin.h: Avoid duplicate multiply_defined specs on
+	earlier Darwin versions with shared libgcc.
+
+2023-07-03  Uros Bizjak  <ubizjak@gmail.com>
+
+	* tree.h (tree_int_cst_equal): Change return type from int to bool.
+	(operand_equal_for_phi_arg_p): Ditto.
+	(tree_map_base_marked_p): Ditto.
+	* tree.cc (contains_placeholder_p): Update function body
+	for bool return type.
+	(type_cache_hasher::equal): Ditto.
+	(tree_map_base_hash): Change return type
+	from int to void and adjust function body accordingly.
+	(tree_int_cst_equal): Ditto.
+	(operand_equal_for_phi_arg_p): Ditto.
+	(get_narrower): Change "first" variable to bool.
+	(cl_option_hasher::equal): Update function body for bool return type.
+	* ggc.h (ggc_set_mark): Change return type from int to bool.
+	(ggc_marked_p): Ditto.
+	* ggc-page.cc (gt_ggc_mx): Change return type
+	from int to void and adjust function body accordingly.
+	(ggc_set_mark): Ditto.
+
+2023-07-03  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/autovec.md: Change order of
+	LEN_MASK_LOAD/LEN_MASK_STORE/LEN_LOAD/LEN_STORE arguments.
+	* config/riscv/riscv-v.cc (expand_load_store): Ditto.
+	* doc/md.texi: Ditto.
+	* gimple-fold.cc (gimple_fold_partial_load_store_mem_ref): Ditto.
+	* internal-fn.cc (len_maskload_direct): Ditto.
+	(len_maskstore_direct): Ditto.
+	(add_len_and_mask_args): New function.
+	(expand_partial_load_optab_fn): Change order of
+	LEN_MASK_LOAD/LEN_MASK_STORE/LEN_LOAD/LEN_STORE arguments.
+	(expand_partial_store_optab_fn): Ditto.
+	(internal_fn_len_index): New function.
+	(internal_fn_mask_index): Change order of
+	LEN_MASK_LOAD/LEN_MASK_STORE/LEN_LOAD/LEN_STORE arguments.
+	(internal_fn_stored_value_index): Ditto.
+	(internal_len_load_store_bias): Ditto.
+	* internal-fn.h (internal_fn_len_index): New function.
+	* tree-ssa-dse.cc (initialize_ao_ref_for_dse): Change order of
+	LEN_MASK_LOAD/LEN_MASK_STORE/LEN_LOAD/LEN_STORE arguments.
+	* tree-vect-stmts.cc (vectorizable_store): Ditto.
+	(vectorizable_load): Ditto.
+
+2023-07-03  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/110125
+	* doc/gm2.texi (Semantic checking): Include examples using
+	-Wuninit-variable-checking.
+
+2023-07-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/autovec-opt.md (*double_widen_fnma<mode>): New pattern.
+	(*single_widen_fnma<mode>): Ditto.
+	(*double_widen_fms<mode>): Ditto.
+	(*single_widen_fms<mode>): Ditto.
+	(*double_widen_fnms<mode>): Ditto.
+	(*single_widen_fnms<mode>): Ditto.
+
+2023-07-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/autovec-opt.md (@pred_single_widen_mul<any_extend:su><mode>): Change "@"
+	into "*" in pattern name which simplifies build files.
+	(*pred_single_widen_mul<any_extend:su><mode>): Ditto.
+	(*pred_single_widen_mul<mode>): New pattern.
+
+2023-07-03  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-simd.md (vec_extract<mode><Vhalf>): Expect
+	the index to be 0 or 1.
+
+2023-07-03  Lehua Ding  <lehua.ding@rivai.ai>
+
+	Revert:
+	2023-07-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/autovec-opt.md (*double_widen_fnma<mode>): New pattern.
+	(*single_widen_fnma<mode>): Ditto.
+	(*double_widen_fms<mode>): Ditto.
+	(*single_widen_fms<mode>): Ditto.
+	(*double_widen_fnms<mode>): Ditto.
+	(*single_widen_fnms<mode>): Ditto.
+
+2023-07-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/autovec-opt.md (*double_widen_fnma<mode>): New pattern.
+	(*single_widen_fnma<mode>): Ditto.
+	(*double_widen_fms<mode>): Ditto.
+	(*single_widen_fms<mode>): Ditto.
+	(*double_widen_fnms<mode>): Ditto.
+	(*single_widen_fnms<mode>): Ditto.
+
+2023-07-03  Pan Li  <pan2.li@intel.com>
+
+	* config/riscv/vector.md: Fix typo.
+
+2023-07-03  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/110506
+	* tree-vect-patterns.cc (vect_recog_rotate_pattern): Re-order
+	TYPE_PRECISION access with INTEGRAL_TYPE_P check.
+
+2023-07-03  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/110506
+	* tree-ssa-ccp.cc (get_value_for_expr): Check for integral
+	type before relying on TYPE_PRECISION to produce a nonzero mask.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* config/mips/mips.md(*and<mode>3_mips16): Generates
+	ZEB/ZEH instructions.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* config/mips/mips.cc(mips_9bit_offset_address_p): Restrict the
+	address register to M16_REGS for MIPS16.
+	(BUILTIN_AVAIL_MIPS16E2): Defined a new macro.
+	(AVAIL_MIPS16E2_OR_NON_MIPS16): Same as above.
+	(AVAIL_NON_MIPS16 (cache..)): Update to
+	AVAIL_MIPS16E2_OR_NON_MIPS16.
+	* config/mips/mips.h (ISA_HAS_CACHE): Add clause for ISA_HAS_MIPS16E2.
+	* config/mips/mips.md (mips_cache): Mark as extended MIPS16.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause
+	for ISA_HAS_MIPS16E2.
+	(ISA_HAS_SYNC): Same as above.
+	(ISA_HAS_LL_SC): Same as above.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* config/mips/mips.cc(mips_expand_ins_as_unaligned_store):
+	Add logics for generating instruction.
+	* config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for ISA_HAS_MIPS16E2.
+	* config/mips/mips.md(mov_<load>l): Generates instructions.
+	(mov_<load>r): Same as above.
+	(mov_<store>l): Adjusted for the conditions above.
+	(mov_<store>r): Same as above.
+	(mov_<store>l_mips16e2): Add machine description for `define_insn mov_<store>l_mips16e2`.
+	(mov_<store>r_mips16e2): Add machine description for `define_insn mov_<store>r_mips16e2`.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction.
+	(mips_const_insns): Same as above.
+	(mips_output_move): Same as above.
+	(mips_output_function_prologue): Same as above.
+	* config/mips/mips.md: Same as above
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* config/mips/constraints.md(Yz): New constraints for mips16e2.
+	* config/mips/mips-protos.h(mips_bit_clear_p): Declared new function.
+	(mips_bit_clear_info): Same as above.
+	* config/mips/mips.cc(mips_bit_clear_info): New function for
+	generating instructions.
+	(mips_bit_clear_p): Same as above.
+	* config/mips/mips.h(ISA_HAS_EXT_INS): Add clause for ISA_HAS_MIPS16E2.
+	* config/mips/mips.md(extended_mips16): Generates EXT and INS instructions.
+	(*and<mode>3): Generates INS instruction.
+	(*and<mode>3_mips16): Generates EXT, INS and ANDI instructions.
+	(ior<mode>3): Add logics for ORI instruction.
+	(*ior<mode>3_mips16_asmacro): Generates ORI instrucion.
+	(*ior<mode>3_mips16): Add logics for XORI instruction.
+	(*xor<mode>3_mips16): Generates XORI instrucion.
+	(*extzv<mode>): Add logics for EXT instruction.
+	(*insv<mode>): Add logics for INS instruction.
+	* config/mips/predicates.md(bit_clear_operand): New predicate for
+	generating bitwise instructions.
+	(and_reg_operand): Add logics for generating bitwise instructions.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* config/mips/mips.cc(mips_regno_mode_ok_for_base_p): Generate instructions
+	that uses global pointer register.
+	(mips16_unextended_reference_p): Same as above.
+	(mips_pic_base_register): Same as above.
+	(mips_init_relocs): Same as above.
+	* config/mips/mips.h(MIPS16_GP_LOADS): Defined a new macro.
+	(GLOBAL_POINTER_REGNUM): Moved to machine description `mips.md`.
+	* config/mips/mips.md(GLOBAL_POINTER_REGNUM): Moved to here from above.
+	(*lowsi_mips16_gp):New `define_insn *low<mode>_mips16`.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* config/mips/mips.h(ISA_HAS_CONDMOVE): Add condition for ISA_HAS_MIPS16E2.
+	* config/mips/mips.md(*mov<GPR:mode>_on_<MOVECC:mode>): Add logics for MOVx insts.
+	(*mov<GPR:mode>_on_<MOVECC:mode>_mips16e2): Generate MOVx instruction.
+	(*mov<GPR:mode>_on_<GPR2:mode>_ne): Add logics for MOVx insts.
+	(*mov<GPR:mode>_on_<GPR2:mode>_ne_mips16e2): Generate MOVx instruction.
+	* config/mips/predicates.md(reg_or_0_operand_mips16e2): New predicate for MOVx insts.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* config/mips/mips.cc(mips_file_start): Add mips16e2 info
+	for output file.
+	* config/mips/mips.h(__mips_mips16e2): Defined a new
+	predefine macro.
+	(ISA_HAS_MIPS16E2): Defined a new macro.
+	(ASM_SPEC): Pass mmips16e2 to the assembler.
+	* config/mips/mips.opt: Add -m(no-)mips16e2 option.
+	* config/mips/predicates.md: Add clause for TARGET_MIPS16E2.
+	* doc/invoke.texi: Add -m(no-)mips16e2 option..
+
 2023-07-02  Jakub Jelinek  <jakub@redhat.com>
 
 	PR tree-optimization/110508
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4686be8f754..a75b56cd2f4 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230703
+20230704
diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index fb2c3d9f9d0..20fdaa68b27 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,41 @@
+2023-07-03  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* exp_ch3.ads (Build_Variant_Record_Equality): Add Spec_Id as second
+	parameter.
+	* exp_ch3.adb (Build_Variant_Record_Equality): For unchecked union
+	types, build the additional parameters as extra formal parameters.
+	(Expand_Freeze_Record_Type.Build_Variant_Record_Equality): Pass
+	Empty as Spec_Id in call to Build_Variant_Record_Equality.
+	* exp_ch4.ads (Expand_Unchecked_Union_Equality): New procedure.
+	* exp_ch4.adb (Expand_Composite_Equality): In the presence of a
+	function implementing composite equality, do not special case the
+	unchecked union types, and only convert the operands if the base
+	types are not the same like in Build_Equality_Call.
+	(Build_Equality_Call): Do not special case the unchecked union types
+	and relocate the operands only once.
+	(Expand_N_Op_Eq): Do not special case the unchecked union types.
+	(Expand_Unchecked_Union_Equality): New procedure implementing the
+	specific expansion of calls to the predefined equality function.
+	* exp_ch6.adb (Is_Unchecked_Union_Equality): New predicate.
+	(Expand_Call): Call Is_Unchecked_Union_Equality to determine whether
+	to call Expand_Unchecked_Union_Equality or Expand_Call_Helper.
+	* exp_ch8.adb (Build_Body_For_Renaming): Set Has_Delayed_Freeze flag
+	earlier on Id and pass Id in call to Build_Variant_Record_Equality.
+
+2023-07-03  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* exp_ch3.adb (Build_Untagged_Equality): Rename into...
+	(Build_Untagged_Record_Equality): ...this.
+	(Expand_Freeze_Record_Type): Adjust to above renaming and invoke
+	the procedure also for discriminated types without a variant part.
+
+2023-07-03  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* sem_util.adb (Has_Inferable_Discriminants): In the case of a
+	component with a per-object constraint, also return true if the
+	enclosing object is not of an unchecked union type.
+	In the default case, remove a useless call to Base_Type.
+
 2023-06-29  Richard Sandiford  <richard.sandiford@arm.com>
 
 	* gcc-interface/decl.cc (gt_pch_nx): Remove overloads for Entity_Id.
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index d8b180d1a3e..53cce9c929d 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,68 @@
+2023-07-03  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/110125
+	* Make-lang.in (GM2-COMP-BOOT-DEFS): Add M2SymInit.def.
+	(GM2-COMP-BOOT-MODS): Add M2SymInit.mod.
+	* gm2-compiler/M2BasicBlock.mod: Formatting changes.
+	* gm2-compiler/M2Code.mod: Remove import of VariableAnalysis from
+	M2Quads.  Import VariableAnalysis from M2SymInit.mod.
+	* gm2-compiler/M2GCCDeclare.mod (PrintVerboseFromList):
+	Add debugging print for a component.
+	(TypeConstFullyDeclared): Call RememberType for every type.
+	* gm2-compiler/M2GenGCC.mod (CodeReturnValue): Add parameter to
+	GetQuadOtok.
+	(CodeBecomes): Add parameter to GetQuadOtok.
+	(CodeXIndr): Add parameter to GetQuadOtok.
+	* gm2-compiler/M2Optimize.mod (ReduceBranch): Reformat and
+	preserve operand token positions when reducing the branch
+	quadruples.
+	(ReduceGoto): Reformat.
+	(FoldMultipleGoto): Reformat.
+	(KnownReachable): Reformat.
+	* gm2-compiler/M2Options.def (UninitVariableChecking): New
+	variable declared and exported.
+	(SetUninitVariableChecking): New procedure.
+	* gm2-compiler/M2Options.mod (SetWall): Set
+	UninitVariableChecking.
+	(SetUninitVariableChecking): New procedure.
+	* gm2-compiler/M2Quads.def (PutQuadOtok): Exported and declared.
+	(VariableAnalysis): Removed.
+	* gm2-compiler/M2Quads.mod (PutQuadOtok): New procedure.
+	(doVal): Reformatted.
+	(MarkAsWrite): Reformatted.
+	(MarkArrayAsWritten): Reformatted.
+	(doIndrX): Use PutQuadOtok.
+	(MakeRightValue): Use GenQuadOtok.
+	(MakeLeftValue): Use GenQuadOtok.
+	(CheckReadBeforeInitialized): Remove.
+	(IsNeverAltered): Reformat.
+	(DebugLocation): New procedure.
+	(BuildDesignatorPointer): Use GenQuadO to preserve operand token
+	position.
+	(BuildRelOp): Use GenQuadOtok ditto.
+	* gm2-compiler/SymbolTable.def (VarCheckReadInit): New procedure.
+	(VarInitState): New procedure.
+	(PutVarInitialized): New procedure.
+	(PutVarFieldInitialized): New procedure function.
+	(GetVarFieldInitialized): New procedure function.
+	(PrintInitialized): New procedure.
+	* gm2-compiler/SymbolTable.mod (VarCheckReadInit): New procedure.
+	(VarInitState): New procedure.
+	(PutVarInitialized): New procedure.
+	(PutVarFieldInitialized): New procedure function.
+	(GetVarFieldInitialized): New procedure function.
+	(PrintInitialized): New procedure.
+	(LRInitDesc): New type.
+	(SymVar): InitState new field.
+	(MakeVar): Initialize InitState.
+	* gm2-gcc/m2options.h (M2Options_SetUninitVariableChecking):
+	New function declaration.
+	* gm2-lang.cc (gm2_langhook_handle_option): Detect
+	OPT_Wuninit_variable_checking and call SetUninitVariableChecking.
+	* lang.opt: Add Wuninit-variable-checking.
+	* gm2-compiler/M2SymInit.def: New file.
+	* gm2-compiler/M2SymInit.mod: New file.
+
 2023-06-30  Iain Sandoe  <iain@sandoe.co.uk>
 
 	PR testsuite/108835
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 235915ed544..1fad2a5e1ee 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,168 @@
+2023-07-03  Christoph Müllner  <christoph.muellner@vrull.eu>
+
+	* gcc.target/riscv/zvbb.c: New test.
+	* gcc.target/riscv/zvbc.c: New test.
+	* gcc.target/riscv/zvkg.c: New test.
+	* gcc.target/riscv/zvkn-1.c: New test.
+	* gcc.target/riscv/zvkn.c: New test.
+	* gcc.target/riscv/zvknc-1.c: New test.
+	* gcc.target/riscv/zvknc-2.c: New test.
+	* gcc.target/riscv/zvknc.c: New test.
+	* gcc.target/riscv/zvkned.c: New test.
+	* gcc.target/riscv/zvkng-1.c: New test.
+	* gcc.target/riscv/zvkng-2.c: New test.
+	* gcc.target/riscv/zvkng.c: New test.
+	* gcc.target/riscv/zvknha.c: New test.
+	* gcc.target/riscv/zvknhb.c: New test.
+	* gcc.target/riscv/zvks-1.c: New test.
+	* gcc.target/riscv/zvks.c: New test.
+	* gcc.target/riscv/zvksc-1.c: New test.
+	* gcc.target/riscv/zvksc-2.c: New test.
+	* gcc.target/riscv/zvksc.c: New test.
+	* gcc.target/riscv/zvksed.c: New test.
+	* gcc.target/riscv/zvksg-1.c: New test.
+	* gcc.target/riscv/zvksg-2.c: New test.
+	* gcc.target/riscv/zvksg.c: New test.
+	* gcc.target/riscv/zvksh.c: New test.
+	* gcc.target/riscv/zvkt.c: New test.
+
+2023-07-03  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* lib/g++.exp: Remove additional flag handled by Darwin specs.
+	* lib/obj-c++.exp: Likewise.
+
+2023-07-03  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/110125
+	* gm2/switches/uninit-variable-checking/fail/testinit.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testlarge.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testlarge2.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testrecinit.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testrecinit2.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testrecinit5.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testsmallrec.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testsmallrec2.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testsmallvec.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testvarinit.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testwithnoptr.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testwithptr.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testwithptr2.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/testwithptr3.mod: New test.
+	* gm2/switches/uninit-variable-checking/pass/testrecinit3.mod: New test.
+	* gm2/switches/uninit-variable-checking/pass/testrecinit5.mod: New test.
+	* gm2/switches/uninit-variable-checking/pass/testsmallrec.mod: New test.
+	* gm2/switches/uninit-variable-checking/pass/testsmallrec2.mod: New test.
+	* gm2/switches/uninit-variable-checking/pass/testvarinit.mod: New test.
+	* gm2/switches/uninit-variable-checking/pass/testwithptr.mod: New test.
+	* gm2/switches/uninit-variable-checking/pass/testwithptr2.mod: New test.
+	* gm2/switches/uninit-variable-checking/pass/testwithptr3.mod: New test.
+	* gm2/switches/uninit-variable-checking/fail/switches-uninit-variable-checking-fail.exp: New file.
+	* gm2/switches/uninit-variable-checking/pass/switches-uninit-variable-checking-pass.exp: New file.
+
+2023-07-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/widen/widen-10.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-11.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-12.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: New test.
+
+2023-07-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/widen/widen-3.c: Add floating-point.
+	* gcc.target/riscv/rvv/autovec/widen/widen-7.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: New test.
+
+2023-07-03  Lehua Ding  <lehua.ding@rivai.ai>
+
+	Revert:
+	2023-07-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/widen/widen-10.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-11.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-12.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: New test.
+
+2023-07-03  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/widen/widen-10.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-11.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-12.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: New test.
+	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: New test.
+
+2023-07-03  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/110506
+	* gcc.dg/pr110506-2.c: New testcase.
+
+2023-07-03  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/110506
+	* gcc.dg/pr110506.c: New testcase.
+
+2023-07-03  Andrew Pinski  <apinski@marvell.com>
+
+	PR tree-optimization/110381
+	* gcc.dg/vect/pr110381.c: Add vect_float_strict.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* gcc.target/mips/mips16e2-cache.c: New tests for mips16e2.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* gcc.target/mips/mips16e2.c: New tests for mips16e2.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* gcc.target/mips/mips16e2.c: Add new tests for mips16e2.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* gcc.target/mips/mips16e2.c: New tests for mips16e2.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* gcc.target/mips/mips16e2-gp.c: New tests for mips16e2.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* gcc.target/mips/mips16e2-cmov.c: Added tests for MOVx instructions.
+
+2023-07-03  Jie Mei  <jie.mei@oss.cipunited.com>
+
+	* gcc.target/mips/mips.exp(mips_option_groups): Add -mmips16e2
+	option.
+	(mips-dg-init): Handle the recognization of mips16e2 targets.
+	(mips-dg-options): Add dependencies for mips16e2.
+
 2023-07-02  Iain Buclaw  <ibuclaw@gdcproject.org>
 
 	* gdc.dg/Wbuiltin_declaration_mismatch2.d: Fix failed tests.
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 94fe320a32b..299aa7bdac2 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,26 @@
+2023-07-03  Jonathan Wakely  <jwakely@redhat.com>
+
+	* testsuite/27_io/headers/iosfwd/synopsis.cc: Make wsyncbuf and
+	wosyncstream depend on _GLIBCXX_USE_CXX11_ABI.
+
+2023-07-03  Jonathan Wakely  <jwakely@redhat.com>
+
+	* include/pstl/pstl_config.h (_PSTL_PRAGMA_SIMD_SCAN,
+	_PSTL_PRAGMA_SIMD_INCLUSIVE_SCAN, _PSTL_PRAGMA_SIMD_EXCLUSIVE_SCAN):
+	Define to OpenMP 5.0 pragmas even for GCC 10.0+.
+	(_PSTL_UDS_PRESENT): Define to 1 for GCC 10.0+.
+
+2023-07-03  Jonathan Wakely  <jwakely@redhat.com>
+
+	* include/bits/alloc_traits.h (_Destroy): Qualify call.
+	* include/bits/stl_construct.h (_Destroy, _Destroy_n): Likewise.
+	* testsuite/23_containers/vector/cons/destroy-adl.cc: New test.
+
+2023-07-03  Iain Sandoe  <iain@sandoe.co.uk>
+
+	* testsuite/lib/libstdc++.exp: Remove additional flag handled
+	by Darwin specs.
+
 2023-06-30  Jonathan Wakely  <jwakely@redhat.com>
 
 	PR libstdc++/110432