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* [gcc r14-6891] Rotate ChangeLog files.
@ 2024-01-03 10:29 Jakub Jelinek
0 siblings, 0 replies; only message in thread
From: Jakub Jelinek @ 2024-01-03 10:29 UTC (permalink / raw)
To: gcc-cvs, libstdc++-cvs
https://gcc.gnu.org/g:8c22aed4b09ce6ffa7bd669377355e38f04614d6
commit r14-6891-g8c22aed4b09ce6ffa7bd669377355e38f04614d6
Author: Jakub Jelinek <jakub@redhat.com>
Date: Wed Jan 3 11:28:42 2024 +0100
Rotate ChangeLog files.
Rotate ChangeLog files for ChangeLogs with yearly cadence.
Diff:
---
gcc/ChangeLog | 54877 +---------------------------------------
gcc/ChangeLog-2023 | 54880 +++++++++++++++++++++++++++++++++++++++++
gcc/ada/ChangeLog | 6974 +-----
gcc/ada/ChangeLog-2023 | 6978 ++++++
gcc/cp/ChangeLog | 4093 +--
gcc/cp/ChangeLog-2023 | 4097 +++
gcc/d/ChangeLog | 489 +-
gcc/d/ChangeLog-2023 | 493 +
gcc/fortran/ChangeLog | 2191 +-
gcc/fortran/ChangeLog-2023 | 2195 ++
gcc/testsuite/ChangeLog | 53050 +--------------------------------------
gcc/testsuite/ChangeLog-2023 | 53054 +++++++++++++++++++++++++++++++++++++++
libgfortran/ChangeLog | 732 +-
libgfortran/ChangeLog-2023 | 736 +
libstdc++-v3/ChangeLog | 8350 +------
libstdc++-v3/ChangeLog-2023 | 8354 +++++++
16 files changed, 130795 insertions(+), 130748 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 81595a03082..a935ce0fb69 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -56,54883 +56,8 @@
PR target/113112
* config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
pointer type liveness count.
-
-2023-12-31 Uros Bizjak <ubizjak@gmail.com>
- Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/43644
- * config/i386/i386.md (*add<dwi>3_doubleword_concat_zext): Tweak
- order of instructions after split, to minimize number of moves.
-
-2023-12-29 Jan Hubicka <jh@suse.cz>
-
- * config/i386/x86-tune.def (X86_TUNE_AVOID_128FMA_CHAINS,
- X86_TUNE_AVOID_256FMA_CHAINS): Enable for znver4 and Core.
-
-2023-12-29 Tamar Christina <tamar.christina@arm.com>
-
- PR target/110625
- * config/aarch64/aarch64.cc (aarch64_vector_costs::add_stmt_cost):
- Adjust throughput and latency calculations for vector conversions.
- (class aarch64_vector_costs): Add m_num_last_promote_demote.
-
-2023-12-29 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (bstrins_<mode>_for_ior_mask):
- For the condition, remove unneeded trailing "\" and move "&&" to
- follow GNU coding style. NFC.
-
-2023-12-29 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/predicates.md
- (symbolic_pcrel_offset_operand): New define_predicate.
- (mem_simple_ldst_operand): Likewise.
- * config/loongarch/loongarch-protos.h
- (loongarch_rewrite_mem_for_simple_ldst): Declare.
- * config/loongarch/loongarch.cc
- (loongarch_rewrite_mem_for_simple_ldst): Implement.
- * config/loongarch/loongarch.md (simple_load<mode>): New
- define_insn_and_rewrite.
- (simple_load_<su>ext<SUBDI:mode><GPR:mode>): Likewise.
- (simple_store<mode>): Likewise.
- (define_peephole2): Remove la.local/[f]ld peepholes.
-
-2023-12-29 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/113133
- * config/i386/i386.md
- (TARGET_USE_VECTOR_FP_CONVERTS SF->DF float_extend splitter):
- Do not handle xmm16+ with TARGET_EVEX512.
-
-2023-12-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (is_vlmax_len_p): New function.
- (expand_load_store): Disallow transformation into VLMAX when len is in range of [0,31]
- (expand_cond_len_op): Ditto.
- (expand_gather_scatter): Ditto.
- (expand_lanes_load_store): Ditto.
- (expand_fold_extract_last): Ditto.
-
-2023-12-28 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.cc (ix86_unary_operator_ok): Move from here...
- * config/i386/i386-expand.cc (ix86_unary_operator_ok): ... to here.
- * config/i386/i386-protos.h: Re-arrange ix86_{unary|binary}_operator_ok
- and ix86_expand_{unary|binary}_operator prototypes.
- * config/i386/i386.md: Cosmetic changes with the usage of
- TARGET_APX_NDD in ix86_expand_{unary|binary}_operator
- and ix86_{unary|binary}_operator_ok function calls.
-
-2023-12-28 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (is_gimple_assign_or_call): Change interface.
- (get_live_range): New function.
-
-2023-12-27 Xi Ruoyao <xry111@xry111.site>
-
- PR target/113148
- * config/loongarch/loongarch.cc (loongarch_secondary_reload):
- Check if regno == -1 besides MEM_P (x) for reloading FCCmode
- from/to FPR to/from memory.
-
-2023-12-27 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (rotl<mode>3):
- New define_expand.
- * config/loongarch/simd.md (vrotl<mode>3): Likewise.
- (rotl<mode>3): Likewise.
-
-2023-12-27 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/113112
- * config/riscv/riscv-vector-costs.cc (is_gimple_assign_or_call): New function.
- (get_first_lane_point): Ditto.
- (get_last_lane_point): Ditto.
- (max_number_of_live_regs): Refine live point dump.
- (compute_estimated_lmul): Make unknown NITERS loop be aware of liveness.
- (costs::better_main_loop_than_p): Ditto.
- * config/riscv/riscv-vector-costs.h (struct stmt_point): Add new member.
-
-2023-12-27 Chenghui Pan <panchenghui@loongson.cn>
-
- * config/loongarch/lasx.md: Use loongarch_split_move and
- loongarch_split_move_p directly.
- * config/loongarch/loongarch-protos.h
- (loongarch_split_move): Remove unnecessary argument.
- (loongarch_split_move_insn_p): Delete.
- (loongarch_split_move_insn): Delete.
- * config/loongarch/loongarch.cc
- (loongarch_split_move_insn_p): Delete.
- (loongarch_load_store_insns): Use loongarch_split_move_p
- directly.
- (loongarch_split_move): remove the unnecessary processing.
- (loongarch_split_move_insn): Delete.
- * config/loongarch/lsx.md: Use loongarch_split_move and
- loongarch_split_move_p directly.
-
-2023-12-27 Chenghui Pan <panchenghui@loongson.cn>
-
- * config/loongarch/lasx.md (vec_concatv4di): Delete.
- (vec_concatv8si): Delete.
- (vec_concatv16hi): Delete.
- (vec_concatv32qi): Delete.
- (vec_concatv4df): Delete.
- (vec_concatv8sf): Delete.
- (vec_concat<mode>): New template with insn output fixed.
-
-2023-12-27 Li Wei <liwei@loongson.cn>
-
- * config/loongarch/loongarch.md: Adjust.
-
-2023-12-27 Haochen Gui <guihaoc@gcc.gnu.org>
-
- * config/rs6000/rs6000-string.cc (expand_block_compare): Assert
- only P7 above can enter this function. Remove P7 CPU test and let
- P7 BE do the expand.
-
-2023-12-27 Haochen Gui <guihaoc@gcc.gnu.org>
-
- * config/rs6000/rs6000.md (cmpmemsi): Fail when optimizing for size.
-
-2023-12-27 Haochen Gui <guihaoc@gcc.gnu.org>
-
- * config/rs6000/rs6000.h (TARGET_EFFICIENT_OVERLAPPING_UNALIGNED):
- Remove.
- * config/rs6000/rs6000-string.cc (select_block_compare_mode):
- Replace TARGET_EFFICIENT_OVERLAPPING_UNALIGNED with
- targetm.slow_unaligned_access.
- (expand_block_compare_gpr): Likewise.
- (expand_block_compare): Likewise.
- (expand_strncmp_gpr_sequence): Likewise.
-
-2023-12-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/113112
- * config/riscv/riscv-vector-costs.cc (compute_estimated_lmul): Tweak LMUL estimation.
- (has_unexpected_spills_p): Ditto.
- (costs::record_potential_unexpected_spills): Ditto.
-
-2023-12-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (compute_estimated_lmul): Allow
- fractional vecrtor.
- (preferred_new_lmul_p): Move RVV V_REGS liveness computation into analyze_loop_vinfo.
- (has_unexpected_spills_p): New function.
- (costs::record_potential_unexpected_spills): Ditto.
- (costs::better_main_loop_than_p): Move RVV V_REGS liveness computation into
- analyze_loop_vinfo.
- * config/riscv/riscv-vector-costs.h: New functions and variables.
-
-2023-12-25 Tamar Christina <tamar.christina@arm.com>
-
- PR bootstrap/113132
- * tree-vect-loop.cc (vect_create_epilog_for_reduction): Initialize vec_stmts;
-
-2023-12-25 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
- Peter Bergner <bergner@linux.ibm.com>
-
- PR target/110320
- * config/rs6000/rs6000.cc (rs6000_conditional_register_usage): Change
- GPR2 to volatile and non-fixed register for PCREL.
- * config/rs6000/rs6000.h (FIXED_REGISTERS): Modify GPR2 to not fixed.
-
-2023-12-25 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR tree-optimization/19832
- * match.pd (`(a != b) ? (a + b) : (2 * a)`): Add `:c`
- on the plus operator.
-
-2023-12-24 Tamar Christina <tamar.christina@arm.com>
-
- * doc/sourcebuild.texi (check_effective_target_vect_early_break_hw,
- check_effective_target_vect_early_break): Document.
-
-2023-12-24 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64-simd.md (cbranch<mode>4): New.
-
-2023-12-24 Tamar Christina <tamar.christina@arm.com>
-
- * tree-if-conv.cc (idx_within_array_bound): Expose.
- * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): New.
- (vect_analyze_data_ref_dependences): Use it.
- * tree-vect-loop-manip.cc (vect_iv_increment_position): New.
- (vect_set_loop_controls_directly,
- vect_set_loop_condition_partial_vectors,
- vect_set_loop_condition_partial_vectors_avx512,
- vect_set_loop_condition_normal): Support multiple exits.
- (slpeel_tree_duplicate_loop_to_edge_cfg): Support LCSAA peeling for
- multiple exits.
- (slpeel_can_duplicate_loop_p): Change vectorizer from looking at BB
- count and instead look at loop shape.
- (vect_update_ivs_after_vectorizer): Drop asserts.
- (vect_gen_vector_loop_niters_mult_vf): Support peeled vector iterations.
- (vect_do_peeling): Support multiple exits.
- (vect_loop_versioning): Likewise.
- * tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Initialise
- early_breaks.
- (vect_analyze_loop_form): Support loop flows with more than single BB
- loop body.
- (vect_create_loop_vinfo): Support niters analysis for multiple exits.
- (vect_analyze_loop): Likewise.
- (vect_get_vect_def): New.
- (vect_create_epilog_for_reduction): Support early exit reductions.
- (vectorizable_live_operation_1): New.
- (find_connected_edge): New.
- (vectorizable_live_operation): Support early exit live operations.
- (move_early_exit_stmts): New.
- (vect_transform_loop): Use it.
- * tree-vect-patterns.cc (vect_init_pattern_stmt): Support gcond.
- (vect_recog_bitfield_ref_pattern): Support gconds and bools.
- (vect_recog_gcond_pattern): New.
- (possible_vector_mask_operation_p): Support gcond masks.
- (vect_determine_mask_precision): Likewise.
- (vect_mark_pattern_stmts): Set gcond def type.
- (can_vectorize_live_stmts): Force early break inductions to be live.
- * tree-vect-stmts.cc (vect_stmt_relevant_p): Add relevancy analysis for
- early breaks.
- (vect_mark_stmts_to_be_vectorized): Process gcond usage.
- (perm_mask_for_reverse): Expose.
- (vectorizable_comparison_1): New.
- (vectorizable_early_exit): New.
- (vect_analyze_stmt): Support early break and gcond.
- (vect_transform_stmt): Likewise.
- (vect_is_simple_use): Likewise.
- (vect_get_vector_types_for_stmt): Likewise.
- * tree-vectorizer.cc (pass_vectorize::execute): Update exits for value
- numbering.
- * tree-vectorizer.h (enum vect_def_type): Add vect_condition_def.
- (LOOP_VINFO_EARLY_BREAKS, LOOP_VINFO_EARLY_BRK_STORES,
- LOOP_VINFO_EARLY_BREAKS_VECT_PEELED, LOOP_VINFO_EARLY_BRK_DEST_BB,
- LOOP_VINFO_EARLY_BRK_VUSES): New.
- (is_loop_header_bb_p): Drop assert.
- (class loop): Add early_breaks, early_break_stores, early_break_dest_bb,
- early_break_vuses.
- (vect_iv_increment_position, perm_mask_for_reverse,
- ref_within_array_bound): New.
- (slpeel_tree_duplicate_loop_to_edge_cfg): Update for early breaks.
-
-2023-12-24 Tamar Christina <tamar.christina@arm.com>
-
- * tree-ssa-loop-im.cc (determine_max_movement): Import insn-codes.h
- and optabs-tree.h and check for vector compare motion out of gcond.
-
-2023-12-24 Hans-Peter Nilsson <hp@axis.com>
-
- PR middle-end/113109
- * config/cris/cris.cc (cris_eh_return_handler_rtx): New function.
- * config/cris/cris-protos.h (cris_eh_return_handler_rtx): Prototype.
- * config/cris/cris.h (EH_RETURN_HANDLER_RTX): Redefine to call
- cris_eh_return_handler_rtx.
-
-2023-12-23 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (rotrsi3_extend): New
- define_insn.
-
-2023-12-23 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-tune.h
- (loongarch_rtx_cost_data::movcf2gr): New field.
- (loongarch_rtx_cost_data::movcf2gr_): New method.
- (loongarch_rtx_cost_data::use_movcf2gr): New method.
- * config/loongarch/loongarch-def.cc
- (loongarch_rtx_cost_data::loongarch_rtx_cost_data): Set movcf2gr
- to COSTS_N_INSNS (7) and movgr2cf to COSTS_N_INSNS (15), based
- on timing on LA464.
- (loongarch_cpu_rtx_cost_data): Set movcf2gr and movgr2cf to
- COSTS_N_INSNS (1) for LA664.
- (loongarch_rtx_cost_optimize_size): Set movcf2gr and movgr2cf to
- COSTS_N_INSNS (1) + 1.
- * config/loongarch/predicates.md (loongarch_fcmp_operator): New
- predicate.
- * config/loongarch/loongarch.md (movfcc): Change to
- define_expand.
- (movfcc_internal): New define_insn.
- (fcc_to_<X:mode>): New define_insn.
- (cstore<ANYF:mode>4): New define_expand.
- * config/loongarch/loongarch.cc
- (loongarch_hard_regno_mode_ok_uncached): Allow FCCmode in GPRs
- and GPRs.
- (loongarch_secondary_reload): Reload FCCmode via FPR and/or GPR.
- (loongarch_emit_float_compare): Call gen_reg_rtx instead of
- loongarch_allocate_fcc.
- (loongarch_allocate_fcc): Remove.
- (loongarch_move_to_gpr_cost): Handle FCC_REGS -> GR_REGS.
- (loongarch_move_from_gpr_cost): Handle GR_REGS -> FCC_REGS.
- (loongarch_register_move_cost): Handle FCC_REGS -> FCC_REGS,
- FCC_REGS -> FP_REGS, and FP_REGS -> FCC_REGS.
-
-2023-12-23 YunQiang Su <syq@gcc.gnu.org>
-
- * config/mips/driver-native.cc (host_detect_local_cpu):
- don't add nan2008 option for -mtune=native.
-
-2023-12-23 YunQiang Su <syq@gcc.gnu.org>
-
- PR target/112759
- * config/mips/driver-native.cc (host_detect_local_cpu):
- Put the ret to the end of args of reconcat.
-
-2023-12-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/113112
- * config/riscv/riscv-vector-costs.cc (max_number_of_live_regs): Refine dump information.
- (preferred_new_lmul_p): Make PHI initial value into live regs calculation.
-
-2023-12-22 Sandra Loosemore <sandra@codesourcery.com>
-
- * omp-general.cc (omp_context_name_list_prop): Remove static qualifer.
- * omp-general.h (omp_context_name_list_prop): Declare.
- * tree-cfg.cc (dump_function_to_file): Intercept
- "omp declare variant base" attribute for special handling.
- * tree-pretty-print.cc: Include omp-general.h.
- (dump_omp_context_selector): New.
- (print_omp_context_selector): New.
- * tree-pretty-print.h (print_omp_context_selector): Declare.
-
-2023-12-22 Jakub Jelinek <jakub@redhat.com>
-
- PR rtl-optimization/112758
- * combine.cc (make_compopund_operation_int): Optimize AND of a SUBREG
- based on nonzero_bits of SUBREG_REG and constant mask on
- WORD_REGISTER_OPERATIONS targets only if it is a zero extending
- MEM load.
-
-2023-12-22 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112941
- * symtab-thunks.cc (expand_thunk): Check aggregate_value_p regardless
- of whether is_gimple_reg_type (restype) or not.
-
-2023-12-22 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/113102
- * gimple-lower-bitint.cc (gimple_lower_bitint): Handle unreleased
- large/huge _BitInt SSA_NAMEs.
-
-2023-12-22 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/113102
- * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Only
- use m_data[save_data_cnt] if it is non-NULL.
-
-2023-12-22 Christophe Lyon <christophe.lyon@linaro.org>
-
- * Makefile.in: Allow overriding EXEPCT.
-
-2023-12-22 chenxiaolong <chenxiaolong@loongson.cn>
-
- * doc/extend.texi:Add modifiers to the vector of asm in the doc.
- * doc/md.texi:Refine the description of the modifier 'f' in the doc.
-
-2023-12-21 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR middle-end/112951
- * doc/md.texi (cond_copysign): Document.
- (cond_len_copysign): Likewise.
- * optabs.def: Reorder cond_copysign to be before
- cond_fmin. Likewise for cond_len_copysign.
-
-2023-12-21 Andre Vieira (lists) <andre.simoesdiasvieira@arm.com>
-
- PR middle-end/113040
- * omp-simd-clone.cc (simd_clone_adjust_argument_types): Add multiple
- vector arguments where simdlen is larger than veclen.
-
-2023-12-21 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/113044
- * config/i386/i386.md (*ashlqi_ext<mode>_1): Move from the
- high register of the input operand.
- (*<insn>qi_ext<mode>_1): Ditto.
-
-2023-12-21 Vladimir N. Makarov <vmakarov@redhat.com>
-
- Revert:
- 2023-12-18 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/112918
- * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
- (in_class_p): Restrict condition for narrowing class in case of
- allow_all_reload_class_changes_p.
- (process_alt_operands): Pass true for
- allow_all_reload_class_changes_p in calls of in_class_p.
- (curr_insn_transform): Ditto for reg operand win.
-
-2023-12-21 Julian Brown <julian@codesourcery.com>
-
- * gimplify.cc (omp_segregate_mapping_groups): Handle "present" groups.
- (gimplify_scan_omp_clauses): Use mapping group functionality to
- iterate through mapping nodes. Remove most gimplification of
- OMP_CLAUSE_MAP nodes from here, but still populate ctx->variables
- splay tree.
- (gimplify_adjust_omp_clauses): Move most gimplification of
- OMP_CLAUSE_MAP nodes here.
-
-2023-12-21 Alex Coplan <alex.coplan@arm.com>
-
- PR target/113093
- * config/aarch64/aarch64-ldp-fusion.cc (latest_hazard_before):
- If the insn is throwing, record the previous insn as a hazard to
- prevent moving it from the end of the BB.
-
-2023-12-21 Jakub Jelinek <jakub@redhat.com>
-
- * gimple-fold.cc (maybe_fold_comparisons_from_match_pd):
- Use unsigned char buffers for lhs1 and lhs2 instead of allocating
- them through XALLOCA.
- * collect2.cc (maybe_run_lto_and_relink): Swap xcalloc arguments.
-
-2023-12-21 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/113094
- * config/aarch64/aarch64-early-ra.cc (apply_allocation): Stub
- out instructions that are going to be deleted before iterating
- over the rest.
-
-2023-12-21 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/112948
- * config/aarch64/aarch64-early-ra.cc (find_strided_accesses): Fix
- cut-&-pasto.
-
-2023-12-21 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112941
- * gimple-lower-bitint.cc (gimple_lower_bitint): Disallow merging
- a cast with multiplication, division or conversion to floating point
- if rhs1 of the cast is result of another single use cast in the same
- bb.
-
-2023-12-21 chenxiaolong <chenxiaolong@loongson.cn>
-
- * doc/extend.texi:According to the documents submitted earlier,
- Two problems with function return types and using the actual types
- of parameters instead of variable names were found and fixed.
-
-2023-12-21 Jiajie Chen <c@jia.je>
-
- * doc/extend.texi(__lsx_vabsd_di): remove extra `i' in name.
- (__lsx_vfrintrm_d, __lsx_vfrintrm_s, __lsx_vfrintrne_d,
- __lsx_vfrintrne_s, __lsx_vfrintrp_d, __lsx_vfrintrp_s, __lsx_vfrintrz_d,
- __lsx_vfrintrz_s): fix return types.
- (__lsx_vld, __lsx_vldi, __lsx_vldrepl_b, __lsx_vldrepl_d,
- __lsx_vldrepl_h, __lsx_vldrepl_w, __lsx_vmaxi_b, __lsx_vmaxi_d,
- __lsx_vmaxi_h, __lsx_vmaxi_w, __lsx_vmini_b, __lsx_vmini_d,
- __lsx_vmini_h, __lsx_vmini_w, __lsx_vsrani_d_q, __lsx_vsrarni_d_q,
- __lsx_vsrlni_d_q, __lsx_vsrlrni_d_q, __lsx_vssrani_d_q,
- __lsx_vssrarni_d_q, __lsx_vssrarni_du_q, __lsx_vssrlni_d_q,
- __lsx_vssrlrni_du_q, __lsx_vst, __lsx_vstx, __lsx_vssrani_du_q,
- __lsx_vssrlni_du_q, __lsx_vssrlrni_d_q): add missing semicolon.
- (__lsx_vpickve2gr_bu, __lsx_vpickve2gr_hu): fix typo in return
- type.
- (__lsx_vstelm_b, __lsx_vstelm_d, __lsx_vstelm_h,
- __lsx_vstelm_w): use imm type for the last argument.
- (__lsx_vsigncov_b, __lsx_vsigncov_h, __lsx_vsigncov_w,
- __lsx_vsigncov_d): remove duplicate definitions.
-
-2023-12-21 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/lasx.md: Use zero expansion instruction.
- * config/loongarch/lsx.md: Ditto.
-
-2023-12-21 Alexandre Oliva <oliva@adacore.com>
-
- PR target/112778
- * builtins.cc (try_store_by_multiple_pieces): Drop obsolete
- comment.
-
-2023-12-21 Kewen Lin <linkw@linux.ibm.com>
-
- PR rtl-optimization/112995
- * sel-sched.cc (try_replace_dest_reg): Check the validity of the
- replaced insn before actually replacing dest in expr.
-
-2023-12-21 Kewen Lin <linkw@linux.ibm.com>
-
- * dbgcnt.def (sched_block): Remove.
- * sched-rgn.cc (schedule_region): Remove the support of debug count
- sched_block.
-
-2023-12-21 Jason Merrill <jason@redhat.com>
-
- PR c++/37722
- * doc/extend.texi: Document that computed goto does not
- call destructors.
-
-2023-12-21 Jason Merrill <jason@redhat.com>
-
- PR c++/106213
- * opts-common.cc (control_warning_option): Call
- handle_generated_option for all cl_var_types.
-
-2023-12-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/113087
- * config/riscv/riscv-v.cc (expand_select_vl): Optimize SELECT_VL.
-
-2023-12-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/113087
- * config/riscv/riscv-vsetvl.cc: Disallow fusion when VL modification pollutes non AVL use.
-
-2023-12-20 Rimvydas Jasinskas <rimvydas.jas@gmail.com>
-
- * doc/invoke.texi: Document the new file extensions
-
-2023-12-20 Richard Sandiford <richard.sandiford@arm.com>
-
- PR rtl-optimization/111702
- * cse.cc (set::mode): Move earlier.
- (set::src_in_memory, set::src_volatile): Convert to bitfields.
- (set::is_fake_set): New member variable.
- (add_to_set): Add an is_fake_set parameter.
- (find_sets_in_insn): Update calls accordingly.
- (cse_insn): Do not apply REG_EQUAL notes to fake sets. Do not
- try to optimize them either, or validate changes to them.
-
-2023-12-20 Kuan-Lin Chen <rufus@andestech.com>
-
- * config/riscv/predicates.md (move_operand): Reject symbolic operands
- with a type SYMBOL_FORCE_TO_MEM.
- (call_insn_operand): Support for CM_Large.
- (pcrel_symbol_operand): New.
- * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add builtin_define
- "__riscv_cmodel_large".
- * config/riscv/riscv-opts.h (riscv_code_model): Add CM_LARGE.
- * config/riscv/riscv-protos.h (riscv_symbol_type): Add
- SYMBOL_FORCE_TO_MEM.
- * config/riscv/riscv.cc (riscv_classify_symbol) Support CM_LARGE model.
- (riscv_symbol_insns) Add SYMBOL_FORCE_TO_MEM.
- (riscv_cannot_force_const_mem): Ditto.
- (riscv_split_symbol): Ditto.
- (riscv_force_address): Check pseudo reg available before force_reg.
- (riscv_size_ok_for_small_data_p): Disable in CM_LARGE model.
- (riscv_can_use_per_function_literal_pools_p): New.
- (riscv_elf_select_rtx_section): Handle per-function literal pools.
- (riscv_output_mi_thunk): Add riscv_in_thunk_func.
- (riscv_option_override): Support CM_LARGE model.
- (riscv_function_ok_for_sibcall): Disable sibcalls in CM_LARGE model.
- (riscv_in_thunk_func): New static.
- * config/riscv/riscv.md (unspec): Define UNSPEC_FORCE_FOR_MEM.
- (*large_load_address): New.
- * config/riscv/riscv.opt (code_model): New.
-
-2023-12-20 Wang Pengcheng <wangpengcheng.pp@bytedance.com>
-
- * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix condition.
-
-2023-12-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- PR target/112787
- * tree-vect-generic.cc (type_for_widest_vector_mode): Change function to
- use original vector type and check widest vector mode has at most the
- same number of elements.
- (get_compute_type): Pass original vector type rather than the element
- type to type_for_widest_vector_mode and remove now obsolete check for
- the number of elements.
-
-2023-12-20 Siddhesh Poyarekar <siddhesh@gotplt.org>
-
- * tree-object-size.cc (object_size_info): Remove UNKNOWNS.
- Drop all references to it.
- (object_sizes_set): Move unknowns propagation code to...
- (gimplify_size_expressions): ... here. Also free reexamine
- bitmap.
- (propagate_unknowns): New parameter UNKNOWNS. Update callers.
-
-2023-12-20 Thomas Schwinge <thomas@codesourcery.com>
-
- * config/gcn/gcn.h (LIBSTDCXX): Define to "gcc".
-
-2023-12-20 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (vect_transform_slp_perm_load_1): Also handle
- CTOR and VIEW_CONVERT up to the load when performing chain DCE.
-
-2023-12-20 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.cc
- (loongarch_expand_vector_init_same): Remove "temp2" and reuse
- "temp" instead.
- (loongarch_expand_vector_init): Use gcc_unreachable () instead
- of gcc_assert (0), and fix the comment for it.
-
-2023-12-20 Xi Ruoyao <xry111@xry111.site>
-
- PR target/113033
- * config/loongarch/loongarch.cc
- (loongarch_expand_vector_init_same): Replace gen_reg_rtx +
- emit_move_insn with force_reg.
- (loongarch_expand_vector_init): Likewise.
-
-2023-12-20 Xi Ruoyao <xry111@xry111.site>
-
- PR target/113034
- * config/loongarch/lasx.md (UNSPEC_LASX_XVFCMP_*): Remove.
- (lasx_xvfcmp_caf_<flasxfmt>): Remove.
- (lasx_xvfcmp_cune_<FLASX:flasxfmt>): Remove.
- (FSC256_UNS): Remove.
- (fsc256): Remove.
- (lasx_xvfcmp_<vfcond:fcc>_<FLASX:flasxfmt>): Remove.
- (lasx_xvfcmp_<fsc256>_<FLASX:flasxfmt>): Remove.
- * config/loongarch/lsx.md (UNSPEC_LSX_XVFCMP_*): Remove.
- (lsx_vfcmp_caf_<flsxfmt>): Remove.
- (lsx_vfcmp_cune_<FLSX:flsxfmt>): Remove.
- (vfcond): Remove.
- (fcc): Remove.
- (FSC_UNS): Remove.
- (fsc): Remove.
- (lsx_vfcmp_<vfcond:fcc>_<FLSX:flsxfmt>): Remove.
- (lsx_vfcmp_<fsc>_<FLSX:flsxfmt>): Remove.
- * config/loongarch/simd.md
- (fcond_simd): New define_code_iterator.
- (<simd_isa>_<x>vfcmp_<fcond:fcond_simd>_<simdfmt>):
- New define_insn.
- (fcond_simd_rev): New define_code_iterator.
- (fcond_rev_asm): New define_code_attr.
- (<simd_isa>_<x>vfcmp_<fcond:fcond_simd_rev>_<simdfmt>):
- New define_insn.
- (fcond_inv): New define_code_iterator.
- (fcond_inv_rev): New define_code_iterator.
- (fcond_inv_rev_asm): New define_code_attr.
- (<simd_isa>_<x>vfcmp_<fcond_inv>_<simdfmt>): New define_insn.
- (<simd_isa>_<x>vfcmp_<fcond_inv:fcond_inv_rev>_<simdfmt>):
- New define_insn.
- (UNSPEC_SIMD_FCMP_CAF, UNSPEC_SIMD_FCMP_SAF,
- UNSPEC_SIMD_FCMP_SEQ, UNSPEC_SIMD_FCMP_SUN,
- UNSPEC_SIMD_FCMP_SUEQ, UNSPEC_SIMD_FCMP_CNE,
- UNSPEC_SIMD_FCMP_SOR, UNSPEC_SIMD_FCMP_SUNE): New unspecs.
- (SIMD_FCMP): New define_int_iterator.
- (fcond_unspec): New define_int_attr.
- (<simd_isa>_<x>vfcmp_<fcond_unspec>_<simdfmt>): New define_insn.
- * config/loongarch/loongarch.cc (loongarch_expand_lsx_cmp):
- Remove unneeded special cases.
-
-2023-12-20 demin.han <demin.han@starfivetech.com>
-
- * config/riscv/riscv-vector-costs.cc (max_number_of_live_regs): Fix
- max live vregs calc
- (preferred_new_lmul_p): Ditto
-
-2023-12-20 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112962
- * config/i386/i386-builtins.cc (ix86_builtins): Increase by one
- element.
- (def_builtin): If not -fnon-call-exceptions, set TREE_NOTHROW on
- the builtin FUNCTION_DECL. Add leaf attribute to DECL_ATTRIBUTES.
- (ix86_add_new_builtins): Likewise.
-
-2023-12-20 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112941
- * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): If
- save_cast_conditional, instead of adding assignment of t4 to
- m_data[save_data_cnt + 1] before m_gsi, add phi nodes such that
- t4 propagates to m_bb loop. For constant idx, use
- m_data[save_data_cnt] rather than m_data[save_data_cnt + 1] if inside
- of the m_bb loop.
- (bitint_large_huge::lower_mergeable_stmt): Clear m_bb when no longer
- expanding inside of that loop.
- (bitint_large_huge::lower_comparison_stmt): Likewise.
- (bitint_large_huge::lower_addsub_overflow): Likewise.
- (bitint_large_huge::lower_mul_overflow): Likewise.
- (bitint_large_huge::lower_bit_query): Likewise.
-
-2023-12-20 Jakub Jelinek <jakub@redhat.com>
-
- * doc/invoke.texi (-Walloc-size): Add to the list of
- warning options, remove unnecessary line-break.
- (-Wcalloc-transposed-args): Document new warning.
-
-2023-12-20 Alex Coplan <alex.coplan@arm.com>
-
- PR target/113062
- * config/aarch64/aarch64-ldp-fusion.cc
- (ldp_bb_info::track_access): Punt on accesses with invalid
- register operands, move definition of mem_size closer to its
- first use.
-
-2023-12-20 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (rvv_builder::npatterns_vid_diff_repeated_p):
- New function to predicate the diff to vid is repeated or not.
- (expand_const_vector): Add restriction
- for the vid-diff code gen and implement general one.
-
-2023-12-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_legitimize_move): Fix ICE.
-
-2023-12-20 Alexandre Oliva <oliva@adacore.com>
-
- PR middle-end/112917
- * builtins.cc (expand_bultin_stack_address): Add
- STACK_POINTER_OFFSET.
- * doc/extend.texi (__builtin_stack_address): Adjust.
-
-2023-12-20 Alexandre Oliva <oliva@adacore.com>
-
- PR rtl-optimization/113002
- * cfgrtl.cc (commit_one_edge_insertion): Tolerate jumps in the
- inserted sequence during expand.
-
-2023-12-20 Alexandre Oliva <oliva@adacore.com>
-
- * builtins.cc (delta_type): New template class.
- (set_apply_args_size, get_apply_args_size): Replace with...
- (saved_apply_args_size): ... this.
- (set_apply_result_size, get_apply_result_size): Replace with...
- (saved_apply_result_size): ... this.
- (apply_args_size, apply_result_size): Adjust.
-
-2023-12-20 Jeff Law <jlaw@ventanamicro.com>
-
- * config/mcore/mcore.h (CC1_SPEC): Do not set -funsigned-bitfields.
-
-2023-12-20 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512bwintrin.h: Allow 64 bit mask intrin usage
- for -mno-evex512.
- * config/i386/i386-builtin.def: Remove OPTION_MASK_ISA2_EVEX512
- for 64 bit mask builtins.
- * config/i386/i386.cc (ix86_hard_regno_mode_ok): Allow 64 bit
- mask register for -mno-evex512.
- * config/i386/i386.md (SWI1248_AVX512BWDQ_64): Remove
- TARGET_EVEX512.
- (*zero_extendsidi2): Change isa attribute to avx512bw.
- (kmov_isa): Ditto.
- (*anddi_1): Ditto.
- (*andn<mode>_1): Remove TARGET_EVEX512.
- (*one_cmplsi2_1_zext): Change isa attribute to avx512bw.
- (*ashl<mode>3_1): Ditto.
- (*lshr<mode>3_1): Ditto.
- * config/i386/sse.md (SWI1248_AVX512BWDQ): Remove TARGET_EVEX512.
- (SWI1248_AVX512BW): Ditto.
- (SWI1248_AVX512BWDQ2): Ditto.
- (*knotsi_1_zext): Ditto.
- (kunpckdi): Ditto.
- (SWI24_MASK): Removed.
- (vec_pack_trunc_<mode>): Change iterator from SWI24_MASK to SWI24.
- (vec_unpacks_lo_di): Remove TARGET_EVEX512.
- (SWI48x_MASK): Removed.
- (vec_unpacks_hi_<mode>): Change iterator from SWI48x_MASK to SWI48x.
-
-2023-12-20 Siddhesh Poyarekar <siddhesh@gotplt.org>
-
- PR tree-optimization/113012
- * tree-object-size.cc (compute_builtin_object_size): Expand
- comment for dynamic object sizes.
- (collect_object_sizes_for): Always set COMPUTED bitmap for
- dynamic object sizes.
-
-2023-12-20 Alexandre Oliva <oliva@adacore.com>
-
- * ipa-strub.cc (gsi_insert_finally_seq_after_call): Likewise.
- (pass_ipa_strub::adjust_at_calls_call): Likewise.
-
-2023-12-20 Alexandre Oliva <oliva@adacore.com>
-
- * gcc.cc (process_command): Use LD_PIE_SPEC only if defined.
-
-2023-12-19 Marek Polacek <polacek@redhat.com>
-
- PR tree-optimization/113069
- * gimple-ssa-sccopy.cc (scc_discovery): Remove unused member.
-
-2023-12-19 Sandra Loosemore <sandra@codesourcery.com>
-
- * omp-general.cc (vendor_properties): Add "hpe".
- (atomic_default_mem_order_properties): Add "acquire" and "release".
- (omp_context_selector_matches): Handle "acquire" and "release".
-
-2023-12-19 Sandra Loosemore <sandra@codesourcery.com>
-
- * omp-selectors.h: New file.
- * omp-general.h: Include omp-selectors.h.
- (OMP_TSS_CODE, OMP_TSS_NAME): New.
- (OMP_TS_CODE, OMP_TS_NAME): New.
- (make_trait_set_selector, make_trait_selector): Adjust declarations.
- (omp_construct_traits_to_codes): Likewise.
- (omp_context_selector_set_compare): Likewise.
- (omp_get_context_selector): Likewise.
- (omp_get_context_selector_list): New.
- * omp-general.cc (omp_construct_traits_to_codes): Pass length in
- as argument instead of returning it. Make it table-driven.
- (omp_tss_map): New.
- (kind_properties, vendor_properties, extension_properties): New.
- (atomic_default_mem_order_properties): New.
- (omp_ts_map): New.
- (omp_check_context_selector): Simplify lookup and dispatch logic.
- (omp_mark_declare_variant): Ignore variants with unknown construct
- selectors. Adjust for new representation.
- (make_trait_set_selector, make_trait_selector): Adjust for new
- representations.
- (omp_context_selector_matches): Simplify dispatch logic. Avoid
- fixed-sized buffers and adjust call to omp_construct_traits_to_codes.
- (omp_context_selector_props_compare): Adjust for new representations
- and simplify dispatch logic.
- (omp_context_selector_set_compare): Likewise.
- (omp_context_selector_compare): Likewise.
- (omp_get_context_selector): Adjust for new representations, and split
- out...
- (omp_get_context_selector_list): New function.
- (omp_lookup_tss_code): New.
- (omp_lookup_ts_code): New.
- (omp_context_compute_score): Adjust for new representations. Avoid
- fixed-sized buffers and magic numbers. Adjust call to
- omp_construct_traits_to_codes.
- * gimplify.cc (omp_construct_selector_matches): Avoid use of
- fixed-size buffer. Adjust call to omp_construct_traits_to_codes.
-
-2023-12-19 Sandra Loosemore <sandra@codesourcery.com>
-
- * omp-general.h (OMP_TP_NAMELIST_NODE): New.
- * omp-general.cc (omp_context_name_list_prop): Move earlier
- in the file, and adjust for new representation.
- (omp_check_context_selector): Adjust this too.
- (omp_context_selector_props_compare): Likewise.
-
-2023-12-19 Sandra Loosemore <sandra@codesourcery.com>
-
- * omp-general.h (OMP_TS_SCORE_NODE): New.
- (OMP_TSS_ID, OMP_TSS_TRAIT_SELECTORS): New.
- (OMP_TS_ID, OMP_TS_SCORE, OMP_TS_PROPERTIES): New.
- (OMP_TP_NAME, OMP_TP_VALUE): New.
- (make_trait_set_selector): Declare.
- (make_trait_selector): Declare.
- (make_trait_property): Declare.
- (omp_constructor_traits_to_codes): Rename to
- omp_construct_traits_to_codes.
- * omp-general.cc (omp_constructor_traits_to_codes): Rename
- to omp_construct_traits_to_codes. Use new accessors.
- (omp_check_context_selector): Use new accessors.
- (make_trait_set_selector): New.
- (make_trait_selector): New.
- (make_trait_property): New.
- (omp_context_name_list_prop): Use new accessors.
- (omp_context_selector_matches): Use new accessors.
- (omp_context_selector_props_compare): Use new accessors.
- (omp_context_selector_set_compare): Use new accessors.
- (omp_get_context_selector): Use new accessors.
- (omp_context_compute_score): Use new accessors.
- * gimplify.cc (omp_construct_selector_matches): Adjust for renaming
- of omp_constructor_traits_to_codes.
-
-2023-12-19 David Faust <david.faust@oracle.com>
-
- PR debug/111735
- * btfout.cc (btf_fwd_to_enum_p): New.
- (btf_asm_type_ref): Special case references to enum forwards.
- (btf_asm_type): Special case enum forwards. Rename btf_size_type to
- btf_size, and change chained ifs switching on btf_kind into else ifs.
-
-2023-12-19 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/113080
- * tree-scalar-evolution.cc (expression_expensive_p): Allow
- a tiny bit of growth due to expansion of shared trees.
- (final_value_replacement_loop): Add comment.
-
-2023-12-19 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/113073
- * tree-vect-stmts.cc (vectorizable_load): Properly ensure
- to exempt only vector-size aligned overreads.
-
-2023-12-19 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-expand.cc
- (ix86_convert_const_wide_int_to_broadcast): Remove static.
- (ix86_expand_move): Don't attempt to convert wide constants
- to SSE using ix86_convert_const_wide_int_to_broadcast here.
- (ix86_split_long_move): Always un-cprop multi-word constants.
- * config/i386/i386-expand.h
- (ix86_convert_const_wide_int_to_broadcast): Prototype here.
- * config/i386/i386-features.cc: Include i386-expand.h.
- (timode_scalar_chain::convert_insn): When converting TImode to
- V1TImode, try ix86_convert_const_wide_int_to_broadcast.
-
-2023-12-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (expand_const_vector): Use builder.inner_mode ().
-
-2023-12-19 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112816
- * config/i386/mmx.md (signbitv2sf2, signbit<mode>2): Force operands[1]
- into a REG.
-
-2023-12-19 Alex Coplan <alex.coplan@arm.com>
-
- PR target/113061
- * config/aarch64/predicates.md (aarch64_stp_reg_operand): Fix
- parentheses to match intent.
-
-2023-12-19 Jiufu Guo <guojiufu@linux.ibm.com>
-
- PR rtl-optimization/112525
- PR target/30271
- * dse.cc (get_group_info): Add arg_pointer_rtx as frame_related.
- (check_mem_read_rtx): Add parameter to indicate if it is checking mem
- for call insn.
- (scan_insn): Add mem checking on call usage.
-
-2023-12-19 Feng Wang <wangfeng@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
- Add new macro for match function.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
- Add one more parameter for macro expanding.
- (handle_pragma_vector): Add match function calls.
- * config/riscv/riscv-vector-builtins.h (enum required_ext):
- Add enum defination for required extension.
- (struct function_group_info): Add one more parameter for checking required-ext.
-
-2023-12-18 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/112918
- * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
- (in_class_p): Restrict condition for narrowing class in case of
- allow_all_reload_class_changes_p.
- (process_alt_operands): Pass true for
- allow_all_reload_class_changes_p in calls of in_class_p.
- (curr_insn_transform): Ditto for reg operand win.
-
-2023-12-18 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (redundant compare peephole2):
- New peephole2 pattern.
-
-2023-12-18 Andreas Krebbel <krebbel@linux.ibm.com>
-
- * config/s390/s390.cc (s390_encode_section_info): Replace
- SYMBOL_REF_LOCAL_P with decl_binds_to_current_def_p.
-
-2023-12-18 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR tree-optimization/113054
- * gimple-ssa-sccopy.cc: Wrap the local types
- with an anonymous namespace.
-
-2023-12-18 Richard Biener <rguenther@suse.de>
-
- PR middle-end/111975
- * tree-pretty-print.cc (dump_generic_node): Dump
- sizetype as __SIZETYPE__ with TDF_GIMPLE.
- Dump unnamed vector types as T [[gnu::vector_size(n)]] with
- TDF_GIMPLE.
- * tree-ssa-address.cc (create_mem_ref_raw): Never generate
- a NULL STEP when INDEX is specified.
-
-2023-12-18 Gerald Pfeifer <gerald@pfeifer.com>
-
- PR target/69374
- * doc/install.texi (Specific) <hppa*-hp-hpux10>: Remove section.
- (Specific) <hppa*-hp-hpux11>: Remove references to GCC 2.95 and
- 3.0. Also libffi has been ported now.
-
-2023-12-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112432
- * config/riscv/riscv.md (none,W21,W42,W84,W43,W86,W87): Add W0.
- (none,W21,W42,W84,W43,W86,W87,W0): Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-12-18 Richard Biener <rguenther@suse.de>
-
- PR c/111975
- * tree-pretty-print.cc (dump_mem_ref): Use TDF_GIMPLE path
- also for TARGET_MEM_REF and amend it.
-
-2023-12-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.cc (riscv_regmode_natural_size): Fix ICE for
- FIXED-VLMAX of -march=rv32gc_zve32f.
-
-2023-12-18 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/113013
- * tree-object-size.cc (alloc_object_size): Return size_unknown if
- corresponding argument(s) don't have integral type or have integral
- type with higher precision than sizetype. Don't check arg1 >= 0
- uselessly. Compare argument indexes against gimple_call_num_args
- in unsigned type rather than int. Formatting fixes.
-
-2023-12-18 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (expand_const_vector): Take step2
- instead of step1 for second series.
-
-2023-12-18 liushuyu <liushuyu011@gmail.com>
-
- * config.gcc: Add loongarch-d.o to d_target_objs for LoongArch
- architecture.
- * config/loongarch/t-loongarch: Add object target for loongarch-d.cc.
- * config/loongarch/loongarch-d.cc
- (loongarch_d_target_versions): add interface function to define builtin
- D versions for LoongArch architecture.
- (loongarch_d_handle_target_float_abi): add interface function to define
- builtin D traits for LoongArch architecture.
- (loongarch_d_register_target_info): add interface function to register
- loongarch_d_handle_target_float_abi function.
- * config/loongarch/loongarch-d.h
- (loongarch_d_target_versions): add function prototype.
- (loongarch_d_register_target_info): Likewise.
-
-2023-12-18 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/vector.md: Add viota avl_type attribute.
-
-2023-12-18 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv.cc (riscv_expand_mult_with_const_int):
- Change int into HOST_WIDE_INT.
- (riscv_legitimize_poly_move): Ditto.
-
-2023-12-17 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (alslsi3_extend): New
- define_insn.
-
-2023-12-17 Xi Ruoyao <xry111@xry111.site>
-
- PR target/112936
- * config/loongarch/loongarch-def.cc
- (loongarch_rtx_cost_data::loongarch_rtx_cost_data): Update
- instruction costs per micro-benchmark results.
- (loongarch_rtx_cost_optimize_size): Set all instruction costs
- to (COSTS_N_INSNS (1) + 1).
- * config/loongarch/loongarch.cc (loongarch_rtx_costs): Remove
- special case for multiplication when optimizing for size.
- Adjust division cost when TARGET_64BIT && !TARGET_DIV32.
- Account the extra cost when TARGET_CHECK_ZERO_DIV and
- optimizing for speed.
-
-2023-12-17 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-def.cc (rtl.h): Include.
- (COSTS_N_INSNS): Remove the macro definition.
-
-2023-12-17 Gerald Pfeifer <gerald@pfeifer.com>
-
- PR target/69374
- * doc/install.texi (Specific) <hppa*-hp-hpux*>: Remove a note on
- GCC 4.3.
- Remove details on how the HP assembler, which we document as not
- working, breaks.
- <hppa*-hp-hpux11>: Note that only the HP linker is supported.
-
-2023-12-17 Gerald Pfeifer <gerald@pfeifer.com>
-
- PR other/69374
- * doc/install.texi (Installing GCC): Remove reference to
- buildstat.html.
- (Testing): Ditto.
- (Final install): Remove section on submitting information for
- buildstat.html. Adjust the request for feedback.
-
-2023-12-16 David Malcolm <dmalcolm@redhat.com>
-
- * json.cc (print_escaped_json_string): New, taken from
- string::print.
- (object::print): Use it for printing keys.
- (string::print): Move implementation to
- print_escaped_json_string.
- (selftest::test_writing_objects): Add a key containing
- quote, backslash, and control characters.
-
-2023-12-16 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * config/aarch64/aarch64-feature-deps.h (fmv_deps_<FEAT_NAME>):
- Define aarch64_feature_flags mask foreach FMV feature.
- * config/aarch64/aarch64-option-extensions.def: Use new macros
- to define FMV feature extensions.
- * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
- Check for target_version attribute after processing target
- attribute.
- (aarch64_fmv_feature_data): New.
- (aarch64_parse_fmv_features): New.
- (aarch64_process_target_version_attr): New.
- (aarch64_option_valid_version_attribute_p): New.
- (get_feature_mask_for_version): New.
- (compare_feature_masks): New.
- (aarch64_compare_version_priority): New.
- (build_ifunc_arg_type): New.
- (make_resolver_func): New.
- (add_condition_to_bb): New.
- (dispatch_function_versions): New.
- (aarch64_generate_version_dispatcher_body): New.
- (aarch64_get_function_versions_dispatcher): New.
- (aarch64_common_function_versions): New.
- (aarch64_mangle_decl_assembler_name): New.
- (TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P): New implementation.
- (TARGET_OPTION_EXPANDED_CLONES_ATTRIBUTE): New implementation.
- (TARGET_OPTION_FUNCTION_VERSIONS): New implementation.
- (TARGET_COMPARE_VERSION_PRIORITY): New implementation.
- (TARGET_GENERATE_VERSION_DISPATCHER_BODY): New implementation.
- (TARGET_GET_FUNCTION_VERSIONS_DISPATCHER): New implementation.
- (TARGET_MANGLE_DECL_ASSEMBLER_NAME): New implementation.
- * config/aarch64/aarch64.h (TARGET_HAS_FMV_TARGET_ATTRIBUTE):
- Set target macro.
- * config/arm/aarch-common.h (enum aarch_parse_opt_result): Add
- new value to report duplicate FMV feature.
- * common/config/aarch64/cpuinfo.h: New file.
-
-2023-12-16 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * attribs.cc (decl_attributes): Pass attribute name to target.
- (is_function_default_version): Update comment to specify
- incompatibility with target_version attributes.
- * cgraphclones.cc (cgraph_node::create_version_clone_with_body):
- Call valid_version_attribute_p for target_version attributes.
- * defaults.h (TARGET_HAS_FMV_TARGET_ATTRIBUTE): New macro.
- * target.def (valid_version_attribute_p): New hook.
- * doc/tm.texi.in: Add new hook.
- * doc/tm.texi: Regenerate.
- * multiple_target.cc (create_dispatcher_calls): Remove redundant
- is_function_default_version check.
- (expand_target_clones): Use target macro to pick attribute name.
- * targhooks.cc (default_target_option_valid_version_attribute_p):
- New.
- * targhooks.h (default_target_option_valid_version_attribute_p):
- New.
- * tree.h (DECL_FUNCTION_VERSIONED): Update comment to include
- target_version attributes.
-
-2023-12-16 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * common/config/aarch64/aarch64-common.cc
- (struct aarch64_option_extension): Remove unused field.
- (all_extensions): Ditto.
- (aarch64_get_extension_string_for_isa_flags): Remove filtering
- of features without native detection.
- * config/aarch64/driver-aarch64.cc (host_detect_local_cpu):
- Explicitly add expected features that lack cpuinfo detection.
-
-2023-12-16 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * common/config/aarch64/aarch64-common.cc
- (aarch64_get_extension_string_for_isa_flags): Fix generation of
- the "+nocrypto" extension.
- * config/aarch64/aarch64.h (AARCH64_ISA_CRYPTO): Remove.
- (TARGET_CRYPTO): Remove.
- * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
- Don't use TARGET_CRYPTO.
-
-2023-12-15 Mary Bennett <mary.bennett@embecosm.com>
-
- * config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
- * config/riscv/corev.md: Likewise.
-
-2023-12-15 Mary Bennett <mary.bennett@embecosm.com>
-
- * common/config/riscv/riscv-common.cc: Add XCVelw.
- * config/riscv/corev.def: Likewise.
- * config/riscv/corev.md: Likewise.
- * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
- * config/riscv/riscv-ftypes.def: Likewise.
- * config/riscv/riscv.opt: Likewise.
- * doc/extend.texi: Add XCVelw builtin documentation.
- * doc/sourcebuild.texi: Likewise.
-
-2023-12-15 Jeff Law <jlaw@ventanamicro.com>
-
- PR target/110201
- * config/riscv/constraints.md (D03, DsA): Remove unused constraints.
- * config/riscv/predicates.md (const_0_3_operand): New predicate.
- (const_0_10_operand): Likewise.
- * config/riscv/crypto.md (riscv_aes32dsi): Use new predicate. Drop
- unnecessary constraint.
- (riscv_aes32dsmi, riscv_aes64im, riscv_aes32esi): Likewise.
- (riscv_aes32esmi, *riscv_<sm4_op>_si): Likewise.
- (riscv_<sm4_op>_di_extend, riscv_<sm4_op>_si): Likewise.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- * config.gcc: Add aarch64-ldp-fusion.o to extra_objs for aarch64.
- * config/aarch64/aarch64-passes.def: Add copies of pass_ldp_fusion
- before and after RA.
- * config/aarch64/aarch64-protos.h (make_pass_ldp_fusion): Declare.
- * config/aarch64/aarch64.opt (-mearly-ldp-fusion): New.
- (-mlate-ldp-fusion): New.
- (--param=aarch64-ldp-alias-check-limit): New.
- (--param=aarch64-ldp-writeback): New.
- * config/aarch64/t-aarch64: Add rule for aarch64-ldp-fusion.o.
- * config/aarch64/aarch64-ldp-fusion.cc: New file.
- * doc/invoke.texi (AArch64 Options): Document new
- -m{early,late}-ldp-fusion options.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- * config/aarch64/aarch64-ldpstp.md: Abstract ldp/stp
- representation from peepholes, allowing use of new form.
- * config/aarch64/aarch64-modes.def (V2x4QImode): Define.
- * config/aarch64/aarch64-protos.h
- (aarch64_finish_ldpstp_peephole): Declare.
- (aarch64_swap_ldrstr_operands): Delete declaration.
- (aarch64_gen_load_pair): Adjust parameters.
- (aarch64_gen_store_pair): Likewise.
- * config/aarch64/aarch64-simd.md (load_pair<DREG:mode><DREG2:mode>):
- Delete.
- (vec_store_pair<DREG:mode><DREG2:mode>): Delete.
- (load_pair<VQ:mode><VQ2:mode>): Delete.
- (vec_store_pair<VQ:mode><VQ2:mode>): Delete.
- * config/aarch64/aarch64.cc (aarch64_pair_mode_for_mode): New.
- (aarch64_gen_store_pair): Adjust to use new unspec form of stp.
- Drop second mem from parameters.
- (aarch64_gen_load_pair): Likewise.
- (aarch64_pair_mem_from_base): New.
- (aarch64_save_callee_saves): Emit REG_CFA_OFFSET notes for
- frame-related saves. Adjust call to aarch64_gen_store_pair
- (aarch64_restore_callee_saves): Adjust calls to
- aarch64_gen_load_pair to account for change in interface.
- (aarch64_process_components): Likewise.
- (aarch64_classify_address): Handle 32-byte pair mems in
- LDP_STP_N case.
- (aarch64_print_operand): Likewise.
- (aarch64_copy_one_block_and_progress_pointers): Adjust calls to
- account for change in aarch64_gen_{load,store}_pair interface.
- (aarch64_set_one_block_and_progress_pointer): Likewise.
- (aarch64_finish_ldpstp_peephole): New.
- (aarch64_gen_adjusted_ldpstp): Adjust to use generation helper.
- * config/aarch64/aarch64.md (ldpstp): New attribute.
- (load_pair_sw_<SX:mode><SX2:mode>): Delete.
- (load_pair_dw_<DX:mode><DX2:mode>): Delete.
- (load_pair_dw_<TX:mode><TX2:mode>): Delete.
- (*load_pair_<ldst_sz>): New.
- (*load_pair_16): New.
- (store_pair_sw_<SX:mode><SX2:mode>): Delete.
- (store_pair_dw_<DX:mode><DX2:mode>): Delete.
- (store_pair_dw_<TX:mode><TX2:mode>): Delete.
- (*store_pair_<ldst_sz>): New.
- (*store_pair_16): New.
- (*load_pair_extendsidi2_aarch64): Adjust to use new form.
- (*zero_extendsidi2_aarch64): Likewise.
- * config/aarch64/iterators.md (VPAIR): New.
- * config/aarch64/predicates.md (aarch64_mem_pair_operand): Change to
- a special predicate derived from aarch64_mem_pair_operator.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_ldpstp_operand_mode_p): Declare.
- * config/aarch64/aarch64.cc (aarch64_gen_storewb_pair): Build RTL
- directly instead of invoking named pattern.
- (aarch64_gen_loadwb_pair): Likewise.
- (aarch64_ldpstp_operand_mode_p): New.
- * config/aarch64/aarch64.md (loadwb_pair<GPI:mode>_<P:mode>): Replace with
- ...
- (*loadwb_post_pair_<ldst_sz>): ... this. Generalize as described
- in cover letter.
- (loadwb_pair<GPF:mode>_<P:mode>): Delete (superseded by the
- above).
- (*loadwb_post_pair_16): New.
- (*loadwb_pre_pair_<ldst_sz>): New.
- (loadwb_pair<TX:mode>_<P:mode>): Delete.
- (*loadwb_pre_pair_16): New.
- (storewb_pair<GPI:mode>_<P:mode>): Replace with ...
- (*storewb_pre_pair_<ldst_sz>): ... this. Generalize as
- described in cover letter.
- (*storewb_pre_pair_16): New.
- (storewb_pair<GPF:mode>_<P:mode>): Delete.
- (*storewb_post_pair_<ldst_sz>): New.
- (storewb_pair<TX:mode>_<P:mode>): Delete.
- (*storewb_post_pair_16): New.
- * config/aarch64/predicates.md (aarch64_mem_pair_operator): New.
- (pmode_plus_operator): New.
- (aarch64_ldp_reg_operand): New.
- (aarch64_stp_reg_operand): New.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_print_address_internal): Handle SVE
- modes when printing ldp/stp addresses.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_const_zero_rtx_p): New.
- * config/aarch64/aarch64.cc (aarch64_const_zero_rtx_p): New.
- Use it ...
- (aarch64_print_operand): ... here. Recognize CONST0_RTXes in
- modes other than VOIDmode.
-
-2023-12-15 Xiao Zeng <zengxiao@eswincomputing.com>
-
- * common/config/riscv/riscv-common.cc:
- (riscv_implied_info): Add zvfbfmin item.
- (riscv_ext_version_table): Ditto.
- (riscv_ext_flag_table): Ditto.
- * config/riscv/riscv.opt:
- (MASK_ZVFBFMIN): New macro.
- (MASK_VECTOR_ELEN_BF_16): Ditto.
- (TARGET_ZVFBFMIN): Ditto.
-
-2023-12-15 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- * config/aarch64/aarch64.opt (aarch64_mops_memmove_size_threshold):
- Change default.
- * config/aarch64/aarch64.md (cpymemdi): Add a parameter.
- (movmemdi): Call aarch64_expand_cpymem.
- * config/aarch64/aarch64.cc (aarch64_copy_one_block): Rename function,
- simplify, support storing generated loads/stores.
- (aarch64_expand_cpymem): Support expansion of memmove.
- * config/aarch64/aarch64-protos.h (aarch64_expand_cpymem): Add bool arg.
-
-2023-12-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (shuffle_merge_patterns): Fix bug.
-
-2023-12-15 Jakub Jelinek <jakub@redhat.com>
-
- * target.h (struct bitint_info): Add abi_limb_mode member, adjust
- comment.
- * target.def (bitint_type_info): Mention abi_limb_mode instead of
- limb_mode.
- * varasm.cc (output_constant): Use abi_limb_mode rather than
- limb_mode.
- * stor-layout.cc (finish_bitfield_representative): Likewise. Assert
- that if precision is smaller or equal to abi_limb_mode precision or
- if info.big_endian is different from WORDS_BIG_ENDIAN, info.limb_mode
- must be the same as info.abi_limb_mode.
- (layout_type): Use abi_limb_mode rather than limb_mode.
- * gimple-fold.cc (clear_padding_bitint_needs_padding_p): Likewise.
- (clear_padding_type): Likewise.
- * config/i386/i386.cc (ix86_bitint_type_info): Also set
- info->abi_limb_mode.
- * doc/tm.texi: Regenerated.
-
-2023-12-15 Julian Brown <julian@codesourcery.com>
-
- * gimplify.cc (extract_base_bit_offset): Add VARIABLE_OFFSET parameter.
- (omp_get_attachment, omp_group_last, omp_group_base,
- omp_directive_maps_explicitly): Add GOMP_MAP_STRUCT_UNORD support.
- (omp_accumulate_sibling_list): Update calls to extract_base_bit_offset.
- Support GOMP_MAP_STRUCT_UNORD.
- (omp_build_struct_sibling_lists, gimplify_scan_omp_clauses,
- gimplify_adjust_omp_clauses, gimplify_omp_target_update): Add
- GOMP_MAP_STRUCT_UNORD support.
- * omp-low.cc (lower_omp_target): Add GOMP_MAP_STRUCT_UNORD support.
- * tree-pretty-print.cc (dump_omp_clause): Likewise.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- PR target/112906
- * config/aarch64/aarch64-sve.md (@aarch64_vec_duplicate_vq<mode>_le):
- Use force_reload_address to reload addresses that aren't suitable for
- ld1rq in the pre-RA splitter.
-
-2023-12-15 Alex Coplan <alex.coplan@arm.com>
-
- PR target/112906
- * emit-rtl.cc (address_reload_context::emit_autoinc): New.
- (force_reload_address): New.
- * emit-rtl.h (struct address_reload_context): Declare.
- (force_reload_address): Declare.
- * lra-constraints.cc (class lra_autoinc_reload_context): New.
- (emit_inc): Drop IN parameter, invoke
- code moved to emit-rtl.cc:address_reload_context::emit_autoinc.
- (curr_insn_transform): Drop redundant IN parameter in call to
- emit_inc.
- * recog.h (class recog_data_saver): New.
-
-2023-12-15 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/113024
- * match.pd (two conversions in a row): Simplify scalar integer
- sign-extension followed by truncation.
-
-2023-12-15 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/113003
- * gimple-lower-bitint.cc (arith_overflow_arg_kind): New function.
- (gimple_lower_bitint): Use it to catch .{ADD,SUB,MUL}_OVERFLOW
- calls with large/huge INTEGER_CST arguments.
-
-2023-12-15 Gerald Pfeifer <gerald@pfeifer.com>
-
- * doc/install.texi (Specific) <nvptx-*-none>: Update nvptx-tools
- Github link.
-
-2023-12-15 Hongyu Wang <hongyu.wang@intel.com>
-
- PR target/112824
- * config/i386/i386-options.cc (ix86_option_override_internal):
- Sync ix86_move_max/ix86_store_max with prefer_vector_width when
- it is explicitly set.
-
-2023-12-15 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/driver-i386.cc (host_detect_local_cpu): Do not
- set Grand Ridge depending on RAO-INT.
- * config/i386/i386.h: Remove PTA_RAOINT from PTA_GRANDRIDGE.
- * doc/invoke.texi: Adjust documentation.
-
-2023-12-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112387
- * config/riscv/riscv.cc: Adapt generic cost model same ARM SVE.
-
-2023-12-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111153
- * tree-vect-loop.cc (vect_estimate_min_profitable_iters):
- Remove address cost for select_vl/decrement IV.
-
-2023-12-14 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR middle-end/111260
- * optabs.cc (emit_conditional_move): Change the modes to be
- equal before forcing the constant to a register.
-
-2023-12-14 Di Zhao <dizhao@os.amperecomputing.com>
-
- PR tree-optimization/110279
- * doc/invoke.texi: New parameter fully-pipelined-fma.
- * params.opt: New parameter fully-pipelined-fma.
- * tree-ssa-reassoc.cc (get_mult_latency_consider_fma): Return
- the latency of MULT_EXPRs that can't be hidden by the FMAs.
- (get_reassociation_width): Search for a smaller width
- considering the benefit of fully pipelined FMA.
- (rank_ops_for_fma): Return the number of MULT_EXPRs.
- (reassociate_bb): Pass the number of MULT_EXPRs to
- get_reassociation_width; avoid calling
- get_reassociation_width twice.
-
-2023-12-14 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112999
- * expmed.cc (extract_bit_field_1): Ensure better mode
- has fitting unit_precision.
-
-2023-12-14 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112773
- * config/riscv/autovec.md (vec_extract<mode>bi): New expander
- calling vec_extract<mode>qi.
- * config/riscv/riscv-protos.h (riscv_legitimize_poly_move):
- Export.
- (emit_vec_extract): Change argument from poly_int64 to rtx.
- * config/riscv/riscv-v.cc (shuffle_extract_and_slide1up_patterns):
- Ditto.
- * config/riscv/riscv.cc (riscv_legitimize_poly_move): Export.
- (riscv_legitimize_move): Use rtx instead of poly_int64.
- * expmed.cc (store_bit_field_1): Change BITSIZE to PRECISION.
- (extract_bit_field_1): Change BITSIZE to PRECISION and use
- return mode from insn_data as target mode.
-
-2023-12-14 Alex Coplan <alex.coplan@arm.com>
-
- * doc/extend.texi: Document AArch64 Operand Modifiers.
-
-2023-12-14 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/113018
- * tree-vect-slp.cc (vect_slp_check_for_roots): Only start
- SLP discovery from stmts with a LHS.
-
-2023-12-14 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112793
- * tree-vect-slp.cc (vect_schedule_slp_node): Already
- code-generated constant/external nodes are OK.
-
-2023-12-14 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-early-ra.cc (allocno_info::is_equiv): New
- member variable.
- (allocno_info::equiv_allocno): Replace with...
- (allocno_info::related_allocno): ...this member variable.
- (allocno_info::chain_prev): Put into an enum with...
- (allocno_info::last_use_point): ...this new member variable.
- (color_info::num_fpr_preferences): New member variable.
- (early_ra::m_shared_allocnos): Likewise.
- (allocno_info::is_shared): New member function.
- (allocno_info::is_equiv_to): Likewise.
- (early_ra::dump_allocnos): Dump sharing information. Tweak column
- widths.
- (early_ra::fpr_preference): Check ALLOWS_NONFPR before returning -2.
- (early_ra::start_new_region): Handle m_shared_allocnos.
- (early_ra::create_allocno_group): Set related_allocno rather than
- equiv_allocno.
- (early_ra::record_allocno_use): Likewise. Detect multiple calls
- for the same program point. Update last_use_point and is_equiv.
- Clear is_strong_copy_src rather than is_strong_copy_dest.
- (early_ra::record_allocno_def): Use related_allocno rather than
- equiv_allocno. Update last_use_point.
- (early_ra::valid_equivalence_p): Replace with...
- (early_ra::find_related_start): ...this new function.
- (early_ra::record_copy): Look for cases where a destination copy chain
- can be shared with the source allocno.
- (early_ra::find_strided_accesses): Update for equiv_allocno->
- related_allocno change. Only call consider_strong_copy_src_chain
- at the head of a copy chain.
- (early_ra::is_chain_candidate): Skip shared allocnos. Update for
- new representation of equivalent allocnos.
- (early_ra::chain_allocnos): Update for new representation of
- equivalent allocnos.
- (early_ra::try_to_chain_allocnos): Likewise.
- (early_ra::merge_fpr_info): New function, split out from...
- (early_ra::set_single_color_rep): ...here.
- (early_ra::form_chains): Handle shared allocnos.
- (early_ra::process_copies): Count the number of FPR preferences.
- (early_ra::cmp_decreasing_size): Rename to...
- (early_ra::cmp_allocation_order): ...this. Sort equal-sized groups
- by the number of FPR preferences.
- (early_ra::finalize_allocation): Handle shared allocnos.
- (early_ra::process_region): Reset chain_prev as well as chain_next.
-
-2023-12-14 Alexandre Oliva <oliva@adacore.com>
-
- PR middle-end/112938
- * ipa-strub.cc (pass_ipa_strub::execute): Pass volatile args
- by reference to internal strub wrapped bodies.
-
-2023-12-14 Alexandre Oliva <oliva@adacore.com>
-
- PR middle-end/112938
- * ipa-strub.cc (pass_ipa_strub::execute): Handle promoted
- volatile args in internal strub. Simplify.
-
-2023-12-14 Thomas Schwinge <thomas@codesourcery.com>
-
- * gimple-ssa-sccopy.cc: '#define INCLUDE_ALGORITHM' instead of
- '#include <algorithm>'.
-
-2023-12-14 Feng Wang <wangfeng@eswincomputing.com>
-
- Revert:
- 2023-12-12 Feng Wang <wangfeng@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION):
- Add AVAIL argument.
- (read_vl): Using AVAIL argument default value.
- (vlenb): Ditto.
- (vsetvl): Ditto.
- (vsetvlmax): Ditto.
- (vle): Ditto.
- (vse): Ditto.
- (vlm): Ditto.
- (vsm): Ditto.
- (vlse): Ditto.
- (vsse): Ditto.
- (vluxei8): Ditto.
- (vluxei16): Ditto.
- (vluxei32): Ditto.
- (vluxei64): Ditto.
- (vloxei8): Ditto.
- (vloxei16): Ditto.
- (vloxei32): Ditto.
- (vloxei64): Ditto.
- (vsuxei8): Ditto.
- (vsuxei16): Ditto.
- (vsuxei32): Ditto.
- (vsuxei64): Ditto.
- (vsoxei8): Ditto.
- (vsoxei16): Ditto.
- (vsoxei32): Ditto.
- (vsoxei64): Ditto.
- (vleff): Ditto.
- (vadd): Ditto.
- (vsub): Ditto.
- (vrsub): Ditto.
- (vneg): Ditto.
- (vwaddu): Ditto.
- (vwsubu): Ditto.
- (vwadd): Ditto.
- (vwsub): Ditto.
- (vwcvt_x): Ditto.
- (vwcvtu_x): Ditto.
- (vzext): Ditto.
- (vsext): Ditto.
- (vadc): Ditto.
- (vmadc): Ditto.
- (vsbc): Ditto.
- (vmsbc): Ditto.
- (vand): Ditto.
- (vor): Ditto.
- (vxor): Ditto.
- (vnot): Ditto.
- (vsll): Ditto.
- (vsra): Ditto.
- (vsrl): Ditto.
- (vnsrl): Ditto.
- (vnsra): Ditto.
- (vncvt_x): Ditto.
- (vmseq): Ditto.
- (vmsne): Ditto.
- (vmsltu): Ditto.
- (vmslt): Ditto.
- (vmsleu): Ditto.
- (vmsle): Ditto.
- (vmsgtu): Ditto.
- (vmsgt): Ditto.
- (vmsgeu): Ditto.
- (vmsge): Ditto.
- (vminu): Ditto.
- (vmin): Ditto.
- (vmaxu): Ditto.
- (vmax): Ditto.
- (vmul): Ditto.
- (vmulh): Ditto.
- (vmulhu): Ditto.
- (vmulhsu): Ditto.
- (vdivu): Ditto.
- (vdiv): Ditto.
- (vremu): Ditto.
- (vrem): Ditto.
- (vwmul): Ditto.
- (vwmulu): Ditto.
- (vwmulsu): Ditto.
- (vmacc): Ditto.
- (vnmsac): Ditto.
- (vmadd): Ditto.
- (vnmsub): Ditto.
- (vwmaccu): Ditto.
- (vwmacc): Ditto.
- (vwmaccsu): Ditto.
- (vwmaccus): Ditto.
- (vmerge): Ditto.
- (vmv_v): Ditto.
- (vsaddu): Ditto.
- (vsadd): Ditto.
- (vssubu): Ditto.
- (vssub): Ditto.
- (vaaddu): Ditto.
- (vaadd): Ditto.
- (vasubu): Ditto.
- (vasub): Ditto.
- (vsmul): Ditto.
- (vssrl): Ditto.
- (vssra): Ditto.
- (vnclipu): Ditto.
- (vnclip): Ditto.
- (vfadd): Ditto.
- (vfsub): Ditto.
- (vfrsub): Ditto.
- (vfadd_frm): Ditto.
- (vfsub_frm): Ditto.
- (vfrsub_frm): Ditto.
- (vfwadd): Ditto.
- (vfwsub): Ditto.
- (vfwadd_frm): Ditto.
- (vfwsub_frm): Ditto.
- (vfmul): Ditto.
- (vfdiv): Ditto.
- (vfrdiv): Ditto.
- (vfmul_frm): Ditto.
- (vfdiv_frm): Ditto.
- (vfrdiv_frm): Ditto.
- (vfwmul): Ditto.
- (vfwmul_frm): Ditto.
- (vfmacc): Ditto.
- (vfnmsac): Ditto.
- (vfmadd): Ditto.
- (vfnmsub): Ditto.
- (vfnmacc): Ditto.
- (vfmsac): Ditto.
- (vfnmadd): Ditto.
- (vfmsub): Ditto.
- (vfmacc_frm): Ditto.
- (vfnmacc_frm): Ditto.
- (vfmsac_frm): Ditto.
- (vfnmsac_frm): Ditto.
- (vfmadd_frm): Ditto.
- (vfnmadd_frm): Ditto.
- (vfmsub_frm): Ditto.
- (vfnmsub_frm): Ditto.
- (vfwmacc): Ditto.
- (vfwnmacc): Ditto.
- (vfwmsac): Ditto.
- (vfwnmsac): Ditto.
- (vfwmacc_frm): Ditto.
- (vfwnmacc_frm): Ditto.
- (vfwmsac_frm): Ditto.
- (vfwnmsac_frm): Ditto.
- (vfsqrt): Ditto.
- (vfsqrt_frm): Ditto.
- (vfrsqrt7): Ditto.
- (vfrec7): Ditto.
- (vfrec7_frm): Ditto.
- (vfmin): Ditto.
- (vfmax): Ditto.
- (vfsgnj): Ditto.
- (vfsgnjn): Ditto.
- (vfsgnjx): Ditto.
- (vfneg): Ditto.
- (vfabs): Ditto.
- (vmfeq): Ditto.
- (vmfne): Ditto.
- (vmflt): Ditto.
- (vmfle): Ditto.
- (vmfgt): Ditto.
- (vmfge): Ditto.
- (vfclass): Ditto.
- (vfmerge): Ditto.
- (vfmv_v): Ditto.
- (vfcvt_x): Ditto.
- (vfcvt_xu): Ditto.
- (vfcvt_rtz_x): Ditto.
- (vfcvt_rtz_xu): Ditto.
- (vfcvt_f): Ditto.
- (vfcvt_x_frm): Ditto.
- (vfcvt_xu_frm): Ditto.
- (vfcvt_f_frm): Ditto.
- (vfwcvt_x): Ditto.
- (vfwcvt_xu): Ditto.
- (vfwcvt_rtz_x): Ditto.
- (vfwcvt_rtz_xu) Ditto.:
- (vfwcvt_f): Ditto.
- (vfwcvt_x_frm): Ditto.
- (vfwcvt_xu_frm) Ditto.:
- (vfncvt_x): Ditto.
- (vfncvt_xu): Ditto.
- (vfncvt_rtz_x): Ditto.
- (vfncvt_rtz_xu): Ditto.
- (vfncvt_f): Ditto.
- (vfncvt_rod_f): Ditto.
- (vfncvt_x_frm): Ditto.
- (vfncvt_xu_frm): Ditto.
- (vfncvt_f_frm): Ditto.
- (vredsum): Ditto.
- (vredmaxu): Ditto.
- (vredmax): Ditto.
- (vredminu): Ditto.
- (vredmin): Ditto.
- (vredand): Ditto.
- (vredor): Ditto.
- (vredxor): Ditto.
- (vwredsum): Ditto.
- (vwredsumu): Ditto.
- (vfredusum): Ditto.
- (vfredosum): Ditto.
- (vfredmax): Ditto.
- (vfredmin): Ditto.
- (vfredusum_frm): Ditto.
- (vfredosum_frm): Ditto.
- (vfwredosum): Ditto.
- (vfwredusum): Ditto.
- (vfwredosum_frm): Ditto.
- (vfwredusum_frm): Ditto.
- (vmand): Ditto.
- (vmnand): Ditto.
- (vmandn): Ditto.
- (vmxor): Ditto.
- (vmor): Ditto.
- (vmnor): Ditto.
- (vmorn): Ditto.
- (vmxnor): Ditto.
- (vmmv): Ditto.
- (vmclr): Ditto.
- (vmset): Ditto.
- (vmnot): Ditto.
- (vcpop): Ditto.
- (vfirst): Ditto.
- (vmsbf): Ditto.
- (vmsif): Ditto.
- (vmsof): Ditto.
- (viota): Ditto.
- (vid): Ditto.
- (vmv_x): Ditto.
- (vmv_s): Ditto.
- (vfmv_f): Ditto.
- (vfmv_s): Ditto.
- (vslideup): Ditto.
- (vslidedown): Ditto.
- (vslide1up): Ditto.
- (vslide1down): Ditto.
- (vfslide1up): Ditto.
- (vfslide1down): Ditto.
- (vrgather): Ditto.
- (vrgatherei16): Ditto.
- (vcompress): Ditto.
- (vundefined): Ditto.
- (vreinterpret): Ditto.
- (vlmul_ext): Ditto.
- (vlmul_trunc): Ditto.
- (vset): Ditto.
- (vget): Ditto.
- (vcreate): Ditto.
- (vlseg): Ditto.
- (vsseg): Ditto.
- (vlsseg): Ditto.
- (vssseg): Ditto.
- (vluxseg): Ditto.
- (vloxseg): Ditto.
- (vsuxseg): Ditto.
- (vsoxseg): Ditto.
- (vlsegff): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION): Using variadic macro.
- * config/riscv/riscv-vector-builtins.h (struct function_group_info):
- Add avail function interface into struct.
- * config/riscv/t-riscv: Add dependency
- * config/riscv/riscv-vector-builtins-avail.h: New file.The definition of AVAIL marco.
-
-2023-12-14 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112994
- * match.pd ((t * u) / (t * v) -> (u / v)): New simplification.
-
-2023-12-14 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112994
- * match.pd ((t * 2) / 2 -> t): Adjust comment to use u instead of 2.
- Punt without range checks if TYPE_OVERFLOW_SANITIZED.
- ((t * u) / v -> t * (u / v)): New simplification.
-
-2023-12-14 Filip Kastl <fkastl@suse.cz>
-
- * Makefile.in: Added sccopy pass.
- * passes.def: Added sccopy pass before LTO streaming and before
- RTL expansion.
- * tree-pass.h (make_pass_sccopy): Added sccopy pass.
- * gimple-ssa-sccopy.cc: New file.
-
-2023-12-14 Martin Jambor <mjambor@suse.cz>
-
- PR tree-optimization/111807
- * tree-sra.cc (build_ref_for_model): Allow offset smaller than
- model->offset when gsi is non-NULL. Adjust function comment.
-
-2023-12-14 liuhongt <hongtao.liu@intel.com>
-
- PR target/112992
- * config/i386/i386-expand.cc
- (ix86_convert_const_wide_int_to_broadcast): Don't convert to
- broadcast for vec_dup{v4di,v8si} when TARGET_AVX2 is not
- available.
- (ix86_broadcast_from_constant): Allow broadcast for V4DI/V8SI
- when !TARGET_AVX2 since it will be forced to memory later.
- (ix86_expand_vector_move): Force constant to mem for
- vec_dup{vssi,v4di} when TARGET_AVX2 is not available.
-
-2023-12-14 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111153
- * config/riscv/riscv-protos.h (struct common_vector_cost): New struct.
- (struct scalable_vector_cost): Ditto.
- (struct cpu_vector_cost): Ditto.
- * config/riscv/riscv-vector-costs.cc (costs::add_stmt_cost): Add RVV
- builtin vectorization cost
- * config/riscv/riscv.cc (struct riscv_tune_param): Ditto.
- (get_common_costs): New function.
- (riscv_builtin_vectorization_cost): Ditto.
- (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): New targethook.
-
-2023-12-13 Richard Ball <richard.ball@arm.com>
-
- * config.gcc: Adds new header to config.
- * config/aarch64/aarch64-builtins.cc (enum aarch64_type_qualifiers):
- Moved to header file.
- (ENTRY): Likewise.
- (enum aarch64_simd_type): Likewise.
- (struct aarch64_simd_type_info): Remove static.
- (GTY): Likewise.
- * config/aarch64/aarch64-c.cc (aarch64_pragma_aarch64):
- Defines pragma for arm_neon_sve_bridge.h.
- * config/aarch64/aarch64-protos.h:
- Add handle_arm_neon_sve_bridge_h
- * config/aarch64/aarch64-sve-builtins-base.h: New intrinsics.
- * config/aarch64/aarch64-sve-builtins-base.cc
- (class svget_neonq_impl): New intrinsic implementation.
- (class svset_neonq_impl): Likewise.
- (class svdup_neonq_impl): Likewise.
- (NEON_SVE_BRIDGE_FUNCTION): New intrinsics.
- * config/aarch64/aarch64-sve-builtins-functions.h
- (NEON_SVE_BRIDGE_FUNCTION): Defines macro for NEON_SVE_BRIDGE
- functions.
- * config/aarch64/aarch64-sve-builtins-shapes.h: New shapes.
- * config/aarch64/aarch64-sve-builtins-shapes.cc
- (parse_element_type): Add NEON element types.
- (parse_type): Likewise.
- (struct get_neonq_def): Defines function shape for get_neonq.
- (struct set_neonq_def): Defines function shape for set_neonq.
- (struct dup_neonq_def): Defines function shape for dup_neonq.
- * config/aarch64/aarch64-sve-builtins.cc
- (DEF_SVE_TYPE_SUFFIX): Changed to be called through
- SVE_NEON macro.
- (DEF_SVE_NEON_TYPE_SUFFIX): Defines
- macro for NEON_SVE_BRIDGE type suffixes.
- (DEF_NEON_SVE_FUNCTION): Defines
- macro for NEON_SVE_BRIDGE functions.
- (function_resolver::infer_neon128_vector_type): Infers type suffix
- for overloaded functions.
- (handle_arm_neon_sve_bridge_h): Handles #pragma arm_neon_sve_bridge.h.
- * config/aarch64/aarch64-sve-builtins.def
- (DEF_SVE_NEON_TYPE_SUFFIX): Macro for handling neon_sve type suffixes.
- (bf16): Replace entry with neon-sve entry.
- (f16): Likewise.
- (f32): Likewise.
- (f64): Likewise.
- (s8): Likewise.
- (s16): Likewise.
- (s32): Likewise.
- (s64): Likewise.
- (u8): Likewise.
- (u16): Likewise.
- (u32): Likewise.
- (u64): Likewise.
- * config/aarch64/aarch64-sve-builtins.h
- (GCC_AARCH64_SVE_BUILTINS_H): Include aarch64-builtins.h.
- (ENTRY): Add aarch64_simd_type definiton.
- (enum aarch64_simd_type): Add neon information to type_suffix_info.
- (struct type_suffix_info): New function.
- * config/aarch64/aarch64-sve.md
- (@aarch64_sve_get_neonq_<mode>): New intrinsic insn for big endian.
- (@aarch64_sve_set_neonq_<mode>): Likewise.
- * config/aarch64/iterators.md: Add UNSPEC_SET_NEONQ.
- * config/aarch64/aarch64-builtins.h: New file.
- * config/aarch64/aarch64-neon-sve-bridge-builtins.def: New file.
- * config/aarch64/arm_neon_sve_bridge.h: New file.
-
-2023-12-13 Patrick Palka <ppalka@redhat.com>
-
- * doc/invoke.texi (C++ Dialect Options): Document
- -fdiagnostics-all-candidates.
-
-2023-12-13 Julian Brown <julian@codesourcery.com>
-
- * gimplify.cc (omp_map_clause_descriptor_p): New function.
- (build_omp_struct_comp_nodes, omp_get_attachment, omp_group_base): Use
- above function.
- (omp_tsort_mapping_groups): Process nodes that have
- OMP_CLAUSE_MAP_RUNTIME_IMPLICIT_P set after those that don't. Add
- enter_exit_data parameter.
- (omp_resolve_clause_dependencies): Remove GOMP_MAP_TO_PSET mappings if
- we're mapping the whole containing derived-type variable.
- (omp_accumulate_sibling_list): Adjust GOMP_MAP_TO_PSET handling.
- Remove GOMP_MAP_ALWAYS_POINTER handling.
- (gimplify_scan_omp_clauses): Pass enter_exit argument to
- omp_tsort_mapping_groups. Don't adjust/remove GOMP_MAP_TO_PSET
- mappings for derived-type components here.
- * tree.h (OMP_CLAUSE_RELEASE_DESCRIPTOR): New macro.
- * tree-pretty-print.cc (dump_omp_clause): Show
- OMP_CLAUSE_RELEASE_DESCRIPTOR in dump output (with
- GOMP_MAP_TO_PSET-like syntax).
-
-2023-12-13 Julian Brown <julian@codesourcery.com>
-
- * gimplify.cc (build_struct_comp_nodes): Don't process
- GOMP_MAP_ATTACH_DETACH "middle" nodes here.
- (omp_mapping_group): Add REPROCESS_STRUCT and FRAGILE booleans for
- nested struct handling.
- (omp_strip_components_and_deref, omp_strip_indirections): Remove
- functions.
- (omp_get_attachment): Handle GOMP_MAP_DETACH here.
- (omp_group_last): Handle GOMP_MAP_*, GOMP_MAP_DETACH,
- GOMP_MAP_ATTACH_DETACH groups for "exit data" of reference-to-pointer
- component array sections.
- (omp_gather_mapping_groups_1): Initialise reprocess_struct and fragile
- fields.
- (omp_group_base): Handle GOMP_MAP_ATTACH_DETACH after GOMP_MAP_STRUCT.
- (omp_index_mapping_groups_1): Skip reprocess_struct groups.
- (omp_get_nonfirstprivate_group, omp_directive_maps_explicitly,
- omp_resolve_clause_dependencies, omp_first_chained_access_token): New
- functions.
- (omp_check_mapping_compatibility): Adjust accepted node combinations
- for "from" clauses using release instead of alloc.
- (omp_accumulate_sibling_list): Add GROUP_MAP, ADDR_TOKENS, FRAGILE_P,
- REPROCESSING_STRUCT, ADDED_TAIL parameters. Use OMP address tokenizer
- to analyze addresses. Reimplement nested struct handling, and
- implement "fragile groups".
- (omp_build_struct_sibling_lists): Adjust for changes to
- omp_accumulate_sibling_list. Recalculate bias for ATTACH_DETACH nodes
- after GOMP_MAP_STRUCT nodes.
- (gimplify_scan_omp_clauses): Call omp_resolve_clause_dependencies. Use
- OMP address tokenizer.
- (gimplify_adjust_omp_clauses_1): Use build_fold_indirect_ref_loc
- instead of build_simple_mem_ref_loc.
- * omp-general.cc (omp-general.h, tree-pretty-print.h): Include.
- (omp_addr_tokenizer): New namespace.
- (omp_addr_tokenizer::omp_addr_token): New.
- (omp_addr_tokenizer::omp_parse_component_selector,
- omp_addr_tokenizer::omp_parse_ref,
- omp_addr_tokenizer::omp_parse_pointer,
- omp_addr_tokenizer::omp_parse_access_method,
- omp_addr_tokenizer::omp_parse_access_methods,
- omp_addr_tokenizer::omp_parse_structure_base,
- omp_addr_tokenizer::omp_parse_structured_expr,
- omp_addr_tokenizer::omp_parse_array_expr,
- omp_addr_tokenizer::omp_access_chain_p,
- omp_addr_tokenizer::omp_accessed_addr): New functions.
- (omp_parse_expr, debug_omp_tokenized_addr): New functions.
- * omp-general.h (omp_addr_tokenizer::access_method_kinds,
- omp_addr_tokenizer::structure_base_kinds,
- omp_addr_tokenizer::token_type,
- omp_addr_tokenizer::omp_addr_token,
- omp_addr_tokenizer::omp_access_chain_p,
- omp_addr_tokenizer::omp_accessed_addr): New.
- (omp_addr_token, omp_parse_expr): New.
- * omp-low.cc (scan_sharing_clauses): Skip error check for references
- to pointers.
- * tree.h (OMP_CLAUSE_ATTACHMENT_MAPPING_ERASED): New macro.
-
-2023-12-13 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-hsa.h (NO_XNACK): Change the defaults.
- * config/gcn/gcn-opts.h (enum hsaco_attr_type): Add HSACO_ATTR_DEFAULT.
- * config/gcn/gcn.cc (gcn_option_override): Set the default flag_xnack.
- * config/gcn/gcn.opt: Add -mxnack=default.
- * doc/invoke.texi: Document the -mxnack default.
-
-2023-12-13 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-hsa.h (NO_XNACK): Ignore missing -march.
- (XNACKOPT): Match on/off; ignore any.
- * config/gcn/gcn-valu.md (gather<mode>_insn_1offset<exec>):
- Add xnack compatible alternatives.
- (gather<mode>_insn_2offsets<exec>): Likewise.
- * config/gcn/gcn.cc (gcn_option_override): Permit -mxnack for devices
- other than Fiji and gfx1030.
- (gcn_expand_epilogue): Remove early-clobber problems.
- (gcn_hsa_declare_function_name): Obey -mxnack setting.
- * config/gcn/gcn.md (xnack): New attribute.
- (enabled): Rework to include "xnack" attribute.
- (*movbi): Add xnack compatible alternatives.
- (*mov<mode>_insn): Likewise.
- (*mov<mode>_insn): Likewise.
- (*mov<mode>_insn): Likewise.
- (*movti_insn): Likewise.
- * config/gcn/gcn.opt (-mxnack): Change the default to "any".
- * doc/invoke.texi: Remove placeholder notice for -mxnack.
-
-2023-12-13 Andrew Carlotti <andrew.carlotti@arm.com>
-
- * config/aarch64/x-aarch64: Add missing dependencies.
-
-2023-12-13 Roger Sayle <roger@nextmovesoftware.com>
- Jeff Law <jlaw@ventanamicro.com>
-
- * config/arc/arc.md (*extvsi_n_0): New define_insn_and_split to
- implement SImode sign extract using a AND, XOR and MINUS sequence.
-
-2023-12-13 Feng Wang <wangfeng@eswincomputing.com>
-
- * common/config/riscv/riscv-common.cc: Modify implied ISA info.
- * config/riscv/arch-canonicalize: Add crypto vector implied info.
-
-2023-12-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112929
- PR target/112988
- * config/riscv/riscv-vsetvl.cc
- (pre_vsetvl::compute_lcm_local_properties): Remove full available.
- (pre_vsetvl::pre_global_vsetvl_info): Add full available optimization.
-
-2023-12-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111317
- * tree-vect-loop.cc (vect_estimate_min_profitable_iters): Adjust for COST for decrement IV.
-
-2023-12-13 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112940
- * gimple-lower-bitint.cc (struct bitint_large_huge): Add another
- argument to prepare_data_in_out method defaulted to NULL_TREE.
- (bitint_large_huge::handle_operand): Pass another argument to
- prepare_data_in_out instead of emitting an assignment to set it.
- (bitint_large_huge::prepare_data_in_out): Add VAL_OUT argument.
- If non-NULL, use it as PHI argument instead of creating a new
- SSA_NAME.
- (bitint_large_huge::handle_cast): Pass rext as another argument
- to 2 prepare_data_in_out calls instead of emitting assignments
- to set them.
-
-2023-12-13 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112953
- * attribs.cc (free_attr_data): Use delete x rather than delete[] x.
-
-2023-12-13 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112962
- * config/i386/i386.cc (ix86_gimple_fold_builtin): For shifts
- and abs without lhs replace with nop.
-
-2023-12-13 Richard Biener <rguenther@suse.de>
-
- * emit-rtl.cc (set_mem_attributes_minus_bitpos): Preserve
- the offset when rewriting an exising MEM_REF base for
- stack slot sharing.
-
-2023-12-13 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112991
- PR tree-optimization/112961
- * tree-ssa-sccvn.h (do_rpo_vn): Add skip_entry_phis argument.
- * tree-ssa-sccvn.cc (do_rpo_vn): Likewise.
- (do_rpo_vn_1): Likewise, merge with auto-processing.
- (run_rpo_vn): Adjust.
- (pass_fre::execute): Likewise.
- * tree-if-conv.cc (tree_if_conversion): Revert last change.
- Value-number latch block but disable value-numbering of
- entry PHIs.
- * tree-ssa-uninit.cc (execute_early_warn_uninitialized): Adjust.
-
-2023-12-13 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112990
- * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..):
- Restrict to vector modes after lowering.
-
-2023-12-13 Richard Biener <rguenther@suse.de>
-
- PR middle-end/111591
- * cfgexpand.cc (update_alias_info_with_stack_vars): Document
- why not adjusting TBAA info on accesses is OK.
-
-2023-12-13 Alexandre Oliva <oliva@adacore.com>
-
- * doc/invoke.texi (multiflags): Drop extraneous period, use
- @pxref instead.
-
-2023-12-13 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-builtins.cc:
- (AARCH64_PLD): New enum aarch64_builtins entry.
- (AARCH64_PLDX): Likewise.
- (AARCH64_PLI): Likewise.
- (AARCH64_PLIX): Likewise.
- (aarch64_init_prefetch_builtin): New.
- (aarch64_general_init_builtins): Call prefetch init function.
- (aarch64_expand_prefetch_builtin): New.
- (aarch64_general_expand_builtin): Add prefetch expansion.
- (require_const_argument): New.
- * config/aarch64/aarch64.md (UNSPEC_PLDX): New.
- (aarch64_pldx): Likewise.
- * config/aarch64/arm_acle.h (__pld): Likewise.
- (__pli): Likewise.
- (__plix): Likewise.
- (__pldx): Likewise.
-
-2023-12-13 Kewen Lin <linkw@linux.ibm.com>
-
- PR tree-optimization/112788
- * value-range.h (range_compatible_p): Workaround same type mode but
- different type precision issue for rs6000 scalar float types
- _Float128 and long double.
-
-2023-12-13 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Add code to use
- pli for 34bit constant.
-
-2023-12-13 Jiufu Guo <guojiufu@linux.ibm.com>
-
- * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Add new
- parameter to record number of instructions to build the constant.
- (num_insns_constant_gpr): Call rs6000_emit_set_long_const to compute
- num_insn.
-
-2023-12-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo): New function.
- (costs::record_potential_vls_unrolling): Ditto.
- (costs::prefer_unrolled_loop): Ditto.
- (costs::better_main_loop_than_p): Ditto.
- (costs::add_stmt_cost): Ditto.
- * config/riscv/riscv-vector-costs.h (enum cost_type_enum): New enum.
- * config/riscv/t-riscv: Add new include files.
-
-2023-12-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (get_current_lmul): Remove it.
- (compute_estimated_lmul): New function.
- (costs::costs): Refactor.
- (costs::preferred_new_lmul_p): Ditto.
- (preferred_new_lmul_p): Ditto.
- (costs::better_main_loop_than_p): Ditto.
- * config/riscv/riscv-vector-costs.h (struct autovec_info): Remove it.
-
-2023-12-12 Martin Jambor <mjambor@suse.cz>
-
- PR tree-optimization/112822
- * tree-sra.cc (load_assign_lhs_subreplacements): Invoke
- force_gimple_operand_gsi also when LHS has partial stores and RHS is a
- VIEW_CONVERT_EXPR.
-
-2023-12-12 Jason Merrill <jason@redhat.com>
- Nathaniel Shead <nathanieloshead@gmail.com>
-
- * tree-core.h (enum clobber_kind): Rename CLOBBER_EOL to
- CLOBBER_STORAGE_END. Add CLOBBER_STORAGE_BEGIN,
- CLOBBER_OBJECT_BEGIN, CLOBBER_OBJECT_END.
- * gimple-lower-bitint.cc
- * gimple-ssa-warn-access.cc
- * gimplify.cc
- * tree-inline.cc
- * tree-ssa-ccp.cc: Adjust for rename.
- * tree-pretty-print.cc: And handle new values.
-
-2023-12-12 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_override_options): Update.
- (aarch64_handle_attr_branch_protection): Update.
- * config/arm/aarch-common-protos.h (aarch_parse_branch_protection):
- Remove.
- (aarch_validate_mbranch_protection): Add new argument.
- * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
- Update.
- (aarch_handle_standard_branch_protection): Update.
- (aarch_handle_pac_ret_protection): Update.
- (aarch_handle_pac_ret_leaf): Update.
- (aarch_handle_pac_ret_b_key): Update.
- (aarch_handle_bti_protection): Update.
- (aarch_parse_branch_protection): Remove.
- (next_tok): New.
- (aarch_validate_mbranch_protection): Rewrite.
- * config/arm/aarch-common.h (struct aarch_branch_protect_type):
- Add field "alone".
- * config/arm/arm.cc (arm_configure_build_target): Update.
-
-2023-12-12 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_override_options_after_change_1):
- Do not override branch_protection options.
- (aarch64_override_options): Remove accepted_branch_protection_string.
- * config/arm/aarch-common.cc (BRANCH_PROTECT_STR_MAX): Remove.
- (aarch_parse_branch_protection): Remove
- accepted_branch_protection_string.
- * config/arm/arm.cc: Likewise.
-
-2023-12-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112736
- * tree-vect-stmts.cc (vectorizable_load): Extend optimization
- to avoid peeling for gaps to handle single-element non-groups
- we now allow with SLP.
-
-2023-12-12 Richard Biener <rguenther@suse.de>
-
- PR ipa/92606
- * ipa-icf.cc (sem_item_optimizer::merge_classes): Check
- both source and alias for the no_icf attribute.
- * doc/extend.texi (no_icf): Document variable attribute.
-
-2023-12-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112961
- * tree-if-conv.cc (tree_if_conversion): Instead of excluding
- the latch block from VN, add a fake entry edge.
-
-2023-12-12 Xi Ruoyao <xry111@xry111.site>
-
- PR middle-end/107723
- * convert.cc (convert_to_integer_1) [case BUILT_IN_TRUNC]: Break
- early if !flag_fp_int_builtin_inexact and flag_trapping_math.
-
-2023-12-12 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p):
- Disable the avl propogation for the vcompress.
-
-2023-12-12 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-opts.h (la_target): Move into #if
- for loongarch-def.h.
- (loongarch_init_target): Likewise.
- (loongarch_config_target): Likewise.
- (loongarch_update_gcc_opt_status): Likewise.
-
-2023-12-12 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
- Return true for SYMBOL_PCREL64. Return true for SYMBOL_GOT_DISP
- if TARGET_CMODEL_EXTREME.
- (loongarch_split_symbol): Check for la_opt_explicit_relocs !=
- EXPLICIT_RELOCS_NONE instead of TARGET_EXPLICIT_RELOCS.
- (loongarch_print_operand_reloc): Likewise.
- (loongarch_option_override_internal): Likewise.
- (loongarch_handle_model_attribute): Likewise.
- * doc/invoke.texi (-mcmodel=extreme): Update the compatibility
- between it and -mexplicit-relocs=.
-
-2023-12-12 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112939
- * tree-ssa-sccvn.cc (visit_phi): When all args are undefined
- make sure we end up with a value that was visited, otherwise
- fall back to .VN_TOP.
-
-2023-12-12 liuhongt <hongtao.liu@intel.com>
-
- PR target/112891
- * config/i386/i386.cc (ix86_avx_u128_mode_after): Return
- AVX_U128_ANY if callee_abi doesn't clobber all_sse_regs to
- align with ix86_avx_u128_mode_needed.
- (ix86_avx_u128_mode_needed): Return AVX_U128_ClEAN for
- sibling_call.
-
-2023-12-12 Alexandre Oliva <oliva@adacore.com>
-
- PR target/112334
- * builtins.h (target_builtins): Add fields for apply_args_size
- and apply_result_size.
- * builtins.cc (apply_args_size, apply_result_size): Cache
- results in fields rather than in static variables.
- (get_apply_args_size, set_apply_args_size): New.
- (get_apply_result_size, set_apply_result_size): New.
-
-2023-12-12 Hongyu Wang <hongyu.wang@intel.com>
-
- PR target/112943
- * config/i386/i386.md (ashl<mode>3): Add TARGET_APX_NDD to
- ix86_expand_binary_operator call.
- (<insn><mode>3): Likewise for rshift.
- (<insn>di3): Likewise for DImode rotate.
- (<insn><mode>3): Likewise for SWI124 rotate.
-
-2023-12-12 Feng Wang <wangfeng@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION):
- Add AVAIL argument.
- (read_vl): Using AVAIL argument default value.
- (vlenb): Ditto.
- (vsetvl): Ditto.
- (vsetvlmax): Ditto.
- (vle): Ditto.
- (vse): Ditto.
- (vlm): Ditto.
- (vsm): Ditto.
- (vlse): Ditto.
- (vsse): Ditto.
- (vluxei8): Ditto.
- (vluxei16): Ditto.
- (vluxei32): Ditto.
- (vluxei64): Ditto.
- (vloxei8): Ditto.
- (vloxei16): Ditto.
- (vloxei32): Ditto.
- (vloxei64): Ditto.
- (vsuxei8): Ditto.
- (vsuxei16): Ditto.
- (vsuxei32): Ditto.
- (vsuxei64): Ditto.
- (vsoxei8): Ditto.
- (vsoxei16): Ditto.
- (vsoxei32): Ditto.
- (vsoxei64): Ditto.
- (vleff): Ditto.
- (vadd): Ditto.
- (vsub): Ditto.
- (vrsub): Ditto.
- (vneg): Ditto.
- (vwaddu): Ditto.
- (vwsubu): Ditto.
- (vwadd): Ditto.
- (vwsub): Ditto.
- (vwcvt_x): Ditto.
- (vwcvtu_x): Ditto.
- (vzext): Ditto.
- (vsext): Ditto.
- (vadc): Ditto.
- (vmadc): Ditto.
- (vsbc): Ditto.
- (vmsbc): Ditto.
- (vand): Ditto.
- (vor): Ditto.
- (vxor): Ditto.
- (vnot): Ditto.
- (vsll): Ditto.
- (vsra): Ditto.
- (vsrl): Ditto.
- (vnsrl): Ditto.
- (vnsra): Ditto.
- (vncvt_x): Ditto.
- (vmseq): Ditto.
- (vmsne): Ditto.
- (vmsltu): Ditto.
- (vmslt): Ditto.
- (vmsleu): Ditto.
- (vmsle): Ditto.
- (vmsgtu): Ditto.
- (vmsgt): Ditto.
- (vmsgeu): Ditto.
- (vmsge): Ditto.
- (vminu): Ditto.
- (vmin): Ditto.
- (vmaxu): Ditto.
- (vmax): Ditto.
- (vmul): Ditto.
- (vmulh): Ditto.
- (vmulhu): Ditto.
- (vmulhsu): Ditto.
- (vdivu): Ditto.
- (vdiv): Ditto.
- (vremu): Ditto.
- (vrem): Ditto.
- (vwmul): Ditto.
- (vwmulu): Ditto.
- (vwmulsu): Ditto.
- (vmacc): Ditto.
- (vnmsac): Ditto.
- (vmadd): Ditto.
- (vnmsub): Ditto.
- (vwmaccu): Ditto.
- (vwmacc): Ditto.
- (vwmaccsu): Ditto.
- (vwmaccus): Ditto.
- (vmerge): Ditto.
- (vmv_v): Ditto.
- (vsaddu): Ditto.
- (vsadd): Ditto.
- (vssubu): Ditto.
- (vssub): Ditto.
- (vaaddu): Ditto.
- (vaadd): Ditto.
- (vasubu): Ditto.
- (vasub): Ditto.
- (vsmul): Ditto.
- (vssrl): Ditto.
- (vssra): Ditto.
- (vnclipu): Ditto.
- (vnclip): Ditto.
- (vfadd): Ditto.
- (vfsub): Ditto.
- (vfrsub): Ditto.
- (vfadd_frm): Ditto.
- (vfsub_frm): Ditto.
- (vfrsub_frm): Ditto.
- (vfwadd): Ditto.
- (vfwsub): Ditto.
- (vfwadd_frm): Ditto.
- (vfwsub_frm): Ditto.
- (vfmul): Ditto.
- (vfdiv): Ditto.
- (vfrdiv): Ditto.
- (vfmul_frm): Ditto.
- (vfdiv_frm): Ditto.
- (vfrdiv_frm): Ditto.
- (vfwmul): Ditto.
- (vfwmul_frm): Ditto.
- (vfmacc): Ditto.
- (vfnmsac): Ditto.
- (vfmadd): Ditto.
- (vfnmsub): Ditto.
- (vfnmacc): Ditto.
- (vfmsac): Ditto.
- (vfnmadd): Ditto.
- (vfmsub): Ditto.
- (vfmacc_frm): Ditto.
- (vfnmacc_frm): Ditto.
- (vfmsac_frm): Ditto.
- (vfnmsac_frm): Ditto.
- (vfmadd_frm): Ditto.
- (vfnmadd_frm): Ditto.
- (vfmsub_frm): Ditto.
- (vfnmsub_frm): Ditto.
- (vfwmacc): Ditto.
- (vfwnmacc): Ditto.
- (vfwmsac): Ditto.
- (vfwnmsac): Ditto.
- (vfwmacc_frm): Ditto.
- (vfwnmacc_frm): Ditto.
- (vfwmsac_frm): Ditto.
- (vfwnmsac_frm): Ditto.
- (vfsqrt): Ditto.
- (vfsqrt_frm): Ditto.
- (vfrsqrt7): Ditto.
- (vfrec7): Ditto.
- (vfrec7_frm): Ditto.
- (vfmin): Ditto.
- (vfmax): Ditto.
- (vfsgnj): Ditto.
- (vfsgnjn): Ditto.
- (vfsgnjx): Ditto.
- (vfneg): Ditto.
- (vfabs): Ditto.
- (vmfeq): Ditto.
- (vmfne): Ditto.
- (vmflt): Ditto.
- (vmfle): Ditto.
- (vmfgt): Ditto.
- (vmfge): Ditto.
- (vfclass): Ditto.
- (vfmerge): Ditto.
- (vfmv_v): Ditto.
- (vfcvt_x): Ditto.
- (vfcvt_xu): Ditto.
- (vfcvt_rtz_x): Ditto.
- (vfcvt_rtz_xu): Ditto.
- (vfcvt_f): Ditto.
- (vfcvt_x_frm): Ditto.
- (vfcvt_xu_frm): Ditto.
- (vfcvt_f_frm): Ditto.
- (vfwcvt_x): Ditto.
- (vfwcvt_xu): Ditto.
- (vfwcvt_rtz_x): Ditto.
- (vfwcvt_rtz_xu) Ditto.:
- (vfwcvt_f): Ditto.
- (vfwcvt_x_frm): Ditto.
- (vfwcvt_xu_frm) Ditto.:
- (vfncvt_x): Ditto.
- (vfncvt_xu): Ditto.
- (vfncvt_rtz_x): Ditto.
- (vfncvt_rtz_xu): Ditto.
- (vfncvt_f): Ditto.
- (vfncvt_rod_f): Ditto.
- (vfncvt_x_frm): Ditto.
- (vfncvt_xu_frm): Ditto.
- (vfncvt_f_frm): Ditto.
- (vredsum): Ditto.
- (vredmaxu): Ditto.
- (vredmax): Ditto.
- (vredminu): Ditto.
- (vredmin): Ditto.
- (vredand): Ditto.
- (vredor): Ditto.
- (vredxor): Ditto.
- (vwredsum): Ditto.
- (vwredsumu): Ditto.
- (vfredusum): Ditto.
- (vfredosum): Ditto.
- (vfredmax): Ditto.
- (vfredmin): Ditto.
- (vfredusum_frm): Ditto.
- (vfredosum_frm): Ditto.
- (vfwredosum): Ditto.
- (vfwredusum): Ditto.
- (vfwredosum_frm): Ditto.
- (vfwredusum_frm): Ditto.
- (vmand): Ditto.
- (vmnand): Ditto.
- (vmandn): Ditto.
- (vmxor): Ditto.
- (vmor): Ditto.
- (vmnor): Ditto.
- (vmorn): Ditto.
- (vmxnor): Ditto.
- (vmmv): Ditto.
- (vmclr): Ditto.
- (vmset): Ditto.
- (vmnot): Ditto.
- (vcpop): Ditto.
- (vfirst): Ditto.
- (vmsbf): Ditto.
- (vmsif): Ditto.
- (vmsof): Ditto.
- (viota): Ditto.
- (vid): Ditto.
- (vmv_x): Ditto.
- (vmv_s): Ditto.
- (vfmv_f): Ditto.
- (vfmv_s): Ditto.
- (vslideup): Ditto.
- (vslidedown): Ditto.
- (vslide1up): Ditto.
- (vslide1down): Ditto.
- (vfslide1up): Ditto.
- (vfslide1down): Ditto.
- (vrgather): Ditto.
- (vrgatherei16): Ditto.
- (vcompress): Ditto.
- (vundefined): Ditto.
- (vreinterpret): Ditto.
- (vlmul_ext): Ditto.
- (vlmul_trunc): Ditto.
- (vset): Ditto.
- (vget): Ditto.
- (vcreate): Ditto.
- (vlseg): Ditto.
- (vsseg): Ditto.
- (vlsseg): Ditto.
- (vssseg): Ditto.
- (vluxseg): Ditto.
- (vloxseg): Ditto.
- (vsuxseg): Ditto.
- (vsoxseg): Ditto.
- (vlsegff): Ditto.
- * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION): Using variadic macro.
- * config/riscv/riscv-vector-builtins.h (struct function_group_info):
- Add avail function interface into struct.
- * config/riscv/t-riscv: Add dependency
- * config/riscv/riscv-vector-builtins-avail.h: New file.The definition of AVAIL marco.
-
-2023-12-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (estimated_poly_value): New function.
- * config/riscv/riscv-v.cc (estimated_poly_value): Ditto.
- * config/riscv/riscv.cc (riscv_estimated_poly_value): Move RVV POLY
- VALUE estimation to riscv-v.cc
-
-2023-12-12 Yang Yujie <yangyujie@loongson.cn>
-
- * config/loongarch/loongarch.cc: Do not restore the saved eh_return
- data registers ($r4-$r7) for a normal return of a function that calls
- __builtin_eh_return elsewhere.
- * config/loongarch/loongarch-protos.h: Same.
- * config/loongarch/loongarch.md: Same.
-
-2023-12-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * recog.cc (constrain_operands): Pass VOIDmode to
- strict_memory_address_p for 'p' constraints in asms.
- * rtl-ssa/changes.cc (recog_level2): Skip redundant constrain_operands
- for asms.
-
-2023-12-11 Jason Merrill <jason@redhat.com>
-
- * common.opt: Add comment.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- PR middle-end/112784
- * expr.cc (emit_block_move_via_loop): Call int_mode_for_size
- for maybe-too-wide sizes.
- (emit_block_cmp_via_loop): Likewise.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- PR target/112778
- * builtins.cc (can_store_by_multiple_pieces): New.
- (try_store_by_multiple_pieces): Call it.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- PR target/112804
- * builtins.cc (try_store_by_multiple_pieces): Use ptr's mode
- for the increment.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- * doc/invoke.texi (multiflags): Add period after @xref to
- silence warning.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- * config/rl78/rl78.cc (TARGET_HAVE_STRUB_SUPPORT_FOR): Disable.
-
-2023-12-11 Alexandre Oliva <oliva@adacore.com>
-
- * ipa-strub.cc (pass_ipa_strub::execute): Check that we don't
- add indirection to pointer parameters, and document attribute
- access non-interactions.
-
-2023-12-11 Roger Sayle <roger@nextmovesoftware.com>
-
- PR rtl-optimization/112380
- * combine.cc (expand_field_assignment): Check if gen_lowpart
- returned a CLOBBER, and avoid calling gen_simplify_binary with
- it if so.
-
-2023-12-11 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR target/111867
- * config/aarch64/aarch64.cc (aarch64_float_const_representable_p): For BFmode,
- only accept +0.0.
-
-2023-12-11 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR tree-optimization/111972
- PR tree-optimization/110637
- * match.pd (`(convert)(zeroone !=/== CST)`): Match
- and simplify to ((convert)zeroone){,^1}.
- * fold-const.cc (fold_binary_loc): Remove
- transformation of `(~a) & 1` and `(a ^ 1) & 1`
- into `(convert)(a == 0)`.
-
-2023-12-11 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR middle-end/112935
- * expr.cc (expand_expr_real_2): Use
- gimple_zero_one_valued_p instead of tree_nonzero_bits
- to find boolean defined expressions.
-
-2023-12-11 Mikael Pettersson <mikpelinux@gmail.com>
-
- PR target/112413
- * config/m68k/linux.h (ASM_RETURN_CASE_JUMP): For
- TARGET_LONG_JUMP_TABLE_OFFSETS, reference the jump table
- via its label.
- * config/m68k/m68kelf.h (ASM_RETURN_CASE_JUMP): Likewise.
- * config/m68k/netbsd-elf.h (ASM_RETURN_CASE_JUMP): Likewise.
-
-2023-12-11 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * config/aarch64/aarch64.cc (lane_size): New function.
- (aarch64_simd_clone_compute_vecsize_and_simdlen): Determine simdlen according to NDS rule
- and reject combination of simdlen and types that lead to vectors larger than 128bits.
-
-2023-12-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * rtl-ssa/insns.cc (function_info::record_use): Add !ordered_p case.
-
-2023-12-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (get_gather_index_mode): New function.
- (shuffle_series_patterns): Robostify shuffle index.
- (shuffle_generic_patterns): Ditto.
-
-2023-12-11 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/arm_neon.h (vldap1_lane_u64): Add
- `const' to `__builtin_aarch64_simd_di *' cast.
- (vldap1q_lane_u64): Likewise.
- (vldap1_lane_s64): Cast __src to `const __builtin_aarch64_simd_di *'.
- (vldap1q_lane_s64): Likewise.
- (vldap1_lane_f64): Cast __src to `const __builtin_aarch64_simd_df *'.
- (vldap1q_lane_f64): Cast __src to `const __builtin_aarch64_simd_df *'.
- (vldap1_lane_p64): Add `const' to `__builtin_aarch64_simd_di *' cast.
- (vldap1q_lane_p64): Add `const' to `__builtin_aarch64_simd_di *' cast.
- (vstl1_lane_u64): remove stray `const'.
- (vstl1_lane_s64): Cast __src to `__builtin_aarch64_simd_di *'.
- (vstl1q_lane_s64): Likewise.
- (vstl1_lane_f64): Cast __src to `const __builtin_aarch64_simd_df *'.
- (vstl1q_lane_f64): Likewise.
-
-2023-12-11 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112853
- * config/riscv/riscv-v.cc (expand_const_vector): Fix step
- calculation.
- (modulo_sel_indices): Also perform modulo for variable-length
- constants.
- (shuffle_series): Recognize series permutations.
- (expand_vec_perm_const_1): Add shuffle_series.
-
-2023-12-11 liuhongt <hongtao.liu@intel.com>
-
- * match.pd (VCE (a cmp b ? -1 : 0) < 0) ? c : d ---> (VCE ((a
- cmp b) ? (VCE:c) : (VCE:d))): New gimple simplication.
-
-2023-12-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Support highest overlap for wv instructions.
-
-2023-12-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (extract_single_source): Fix ICE.
-
-2023-12-11 Jakub Jelinek <jakub@redhat.com>
-
- * doc/extend.texi (__sync_fetch_and_add, __sync_fetch_and_sub,
- __sync_fetch_and_or, __sync_fetch_and_and, __sync_fetch_and_xor,
- __sync_fetch_and_nand, __sync_add_and_fetch, __sync_sub_and_fetch,
- __sync_or_and_fetch, __sync_and_and_fetch, __sync_xor_and_fetch,
- __sync_nand_and_fetch, __sync_bool_compare_and_swap,
- __sync_val_compare_and_swap, __sync_lock_test_and_set,
- __sync_lock_release, __atomic_load_n, __atomic_load, __atomic_store_n,
- __atomic_store, __atomic_exchange_n, __atomic_exchange,
- __atomic_compare_exchange_n, __atomic_compare_exchange,
- __atomic_add_fetch, __atomic_sub_fetch, __atomic_and_fetch,
- __atomic_xor_fetch, __atomic_or_fetch, __atomic_nand_fetch,
- __atomic_fetch_add, __atomic_fetch_sub, __atomic_fetch_and,
- __atomic_fetch_xor, __atomic_fetch_or, __atomic_fetch_nand,
- __atomic_test_and_set, __atomic_clear, __atomic_thread_fence,
- __atomic_signal_fence, __atomic_always_lock_free,
- __atomic_is_lock_free, __builtin_add_overflow,
- __builtin_sadd_overflow, __builtin_saddl_overflow,
- __builtin_saddll_overflow, __builtin_uadd_overflow,
- __builtin_uaddl_overflow, __builtin_uaddll_overflow,
- __builtin_sub_overflow, __builtin_ssub_overflow,
- __builtin_ssubl_overflow, __builtin_ssubll_overflow,
- __builtin_usub_overflow, __builtin_usubl_overflow,
- __builtin_usubll_overflow, __builtin_mul_overflow,
- __builtin_smul_overflow, __builtin_smull_overflow,
- __builtin_smulll_overflow, __builtin_umul_overflow,
- __builtin_umull_overflow, __builtin_umulll_overflow,
- __builtin_add_overflow_p, __builtin_sub_overflow_p,
- __builtin_mul_overflow_p, __builtin_addc, __builtin_addcl,
- __builtin_addcll, __builtin_subc, __builtin_subcl, __builtin_subcll,
- __builtin_alloca, __builtin_alloca_with_align,
- __builtin_alloca_with_align_and_max, __builtin_speculation_safe_value,
- __builtin_nan, __builtin_nand32, __builtin_nand64, __builtin_nand128,
- __builtin_nanf, __builtin_nanl, __builtin_nanf@var{n},
- __builtin_nanf@var{n}x, __builtin_nans, __builtin_nansd32,
- __builtin_nansd64, __builtin_nansd128, __builtin_nansf,
- __builtin_nansl, __builtin_nansf@var{n}, __builtin_nansf@var{n}x,
- __builtin_ffs, __builtin_clz, __builtin_ctz, __builtin_clrsb,
- __builtin_popcount, __builtin_parity, __builtin_bswap16,
- __builtin_bswap32, __builtin_bswap64, __builtin_bswap128,
- __builtin_extend_pointer, __builtin_goacc_parlevel_id,
- __builtin_goacc_parlevel_size, vec_clrl, vec_clrr, vec_mulh, vec_mul,
- vec_div, vec_dive, vec_mod, __builtin_rx_mvtc): Use @var{...} around
- parameter names.
- (vec_rl, vec_sl, vec_sr, vec_sra): Likewise. Use @var{...} also
- around A, B and R in description.
-
-2023-12-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-selftests.cc (riscv_run_selftests):
- Remove poly self test when FIXED-VLMAX.
-
-2023-12-11 Fei Gao <gaofei@eswincomputing.com>
- Xiao Zeng <zengxiao@eswincomputing.com>
-
- * ifcvt.cc (noce_cond_zero_binary_op_supported): Add support for AND.
- (noce_bbs_ok_for_cond_zero_arith): Likewise.
- (noce_try_cond_zero_arith): Likewise.
-
-2023-12-11 liuhongt <hongtao.liu@intel.com>
-
- PR target/112904
- * config/i386/mmx.md (*xop_pcmov_<mode>): New define_insn.
-
-2023-12-11 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/112707
- * config/rs6000/rs6000.h (TARGET_FCTID): Define.
- * config/rs6000/rs6000.md (lrint<mode>di2): Add guard TARGET_FCTID.
- * (lround<mode>di2): Replace TARGET_FPRND with TARGET_FCTID.
-
-2023-12-11 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/112707
- * config/rs6000/rs6000.md (expand lrint<mode>si2): New.
- (insn lrint<mode>si2): Rename to...
- (*lrint<mode>si): ...this.
- (lrint<mode>si_di): New.
-
-2023-12-10 Fei Gao <gaofei@eswincomputing.com>
- Xiao Zeng <zengxiao@eswincomputing.com>
-
- * ifcvt.cc (noce_cond_zero_binary_op_supported): Add support for shift
- like op.
-
-2023-12-10 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/112931
- PR target/112933
- * config/aarch64/aarch64-protos.h (aarch64_sve_reinterpret): Declare.
- * config/aarch64/aarch64.cc (aarch64_sve_reinterpret): New function.
- * config/aarch64/aarch64-sve-builtins-sme.cc (svread_za_impl::expand)
- (svwrite_za_impl::expand): Use it to cast the SVE register to the
- right mode.
-
-2023-12-10 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/112930
- * config/aarch64/aarch64.cc (aarch64_sme_mode_switch_regs::add_reg):
- Force specific SVE modes for single registers as well as structures.
-
-2023-12-10 Jason Merrill <jason@redhat.com>
-
- * doc/invoke.texi (-fpermissive): Mention ObjC++ for -Wnarrowing.
-
-2023-12-10 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/addsub.md (uaddv<mode>4, usubv<mode>4): New expanders.
- (uaddv): New define_insn_and_split plus post-reload pattern.
-
-2023-12-10 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/h8300-protos.h (use_extvsi): Prototype.
- * config/h8300/combiner.md: Two new define_insn_and_split patterns
- to implement signed bitfield extractions.
- * config/h8300/h8300.cc (use_extvsi): New function.
-
-2023-12-10 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/combiner.md (single bit signed bitfield extraction): Fix
- length computation when the bit we want is in the low half word.
-
-2023-12-10 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/h8300.cc (compute_a_shift_length): Fix computation
- of logical shifts on the H8/SX.
-
-2023-12-09 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112887
- * tree-ssa-phiopt.cc (hoist_adjacent_loads): Change type of
- param_align, param_align_bits, offset1, offset2, size2 and align1
- variables from int or unsigned int to unsigned HOST_WIDE_INT.
-
-2023-12-09 Costas Argyris <costas.argyris@gmail.com>
- Jakub Jelinek <jakub@redhat.com>
-
- PR driver/93019
- * gcc.cc (driver::finalize): Call XDELETEVEC on mdswitches before
- clearing it.
-
-2023-12-09 Jakub Jelinek <jakub@redhat.com>
-
- * attribs.h (any_nonignored_attribute_p): Declare.
- * attribs.cc (any_nonignored_attribute_p): New function.
-
-2023-12-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112932
- * config/riscv/vector.md (movmisalign<mode>): Fix VLSmode bugs.
-
-2023-12-09 Alexandre Oliva <oliva@adacore.com>
-
- * tree-emutls.cc: Include diagnostic-core.h.
- (pass_ipa_lower_emutls::gate): Skip if errors were seen.
-
-2023-12-08 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/112875
- * lra-eliminations.cc (lra_eliminate_regs_1): Change an assert.
- Add ASM_OPERANDS case.
-
-2023-12-08 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112109
- * config/riscv/riscv-protos.h (expand_strcmp): Declare.
- * config/riscv/riscv-string.cc (riscv_expand_strcmp): Add
- strategy handling and delegation to scalar and vector expanders.
- (expand_strcmp): Vectorized implementation.
- * config/riscv/riscv.md: Add TARGET_VECTOR to strcmp and strncmp
- expander.
-
-2023-12-08 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112109
- * config/riscv/riscv-protos.h (expand_rawmemchr): Add strlen
- parameter.
- * config/riscv/riscv-string.cc (riscv_expand_strlen): Call
- rawmemchr.
- (expand_rawmemchr): Add strlen handling.
- * config/riscv/riscv.md: Add TARGET_VECTOR to strlen expander.
-
-2023-12-08 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-early-ra.cc (allocno_info::chain_next):
- Put into an enum with...
- (allocno_info::last_def_point): ...new member variable.
- (allocno_info::m_current_bb_point): New member variable.
- (likely_operand_match_p): Switch based on get_constraint_type,
- rather than based on rtx code. Handle relaxed and special memory
- constraints.
- (early_ra::record_copy): Allow the source of an equivalence to be
- assigned to more than once.
- (early_ra::record_allocno_use): Invalidate any previous equivalence.
- Initialize last_def_point.
- (early_ra::record_allocno_def): Set last_def_point.
- (early_ra::valid_equivalence_p): New function, split out from...
- (early_ra::record_copy): ...here. Use last_def_point to handle
- source registers that have a later definition.
- (make_pass_aarch64_early_ra): Fix comment.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
- (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
- (vld1q_f16_x2, vld1q_f32_x2): New.
- (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
- (vld1q_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
- * config/arm/neon.md (vld1_x2<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
- (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
- (vld1q_f16_x3, vld1q_f32_x3): New.
- (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
- (vld1q_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
- * config/arm/neon.md (vld1_x3<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
- (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
- (vld1q_f16_x4, vld1q_f32_x4): New.
- (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
- (vld1q_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
- * config/arm/neon.md (vld1_x4<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
- (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
- (vst1_f16_x2, vst1_f32_x2): New.
- (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
- (vst1_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
- * config/arm/neon.md (vst1_x2<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
- (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
- (vst1_f16_x3, vst1_f32_x3): New.
- (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
- (vst1_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
- * config/arm/neon.md (vst1_x3<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
- (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
- (vst1_f16_x4, vst1_f32_x4): New.
- (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
- (vst1_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
- * config/arm/neon.md (vst1_x4<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
- (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
- (vst1q_f16_x2, vst1q_f32_x2): New.
- (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
- (vst1q_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vst1q_x2): New entries.
- * config/arm/neon.md
- (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
- neon_vst1_x2<mode>.
- * config/arm/iterators.md (VMEMX2): New mode iterator.
- (VMEMX2_q): New mode attribute.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
- (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
- (vst1q_f16_x3, vst1q_f32_x3): New.
- (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
- (vst1q_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
- * config/arm/neon.md (neon_vst1q_x3<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
- (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
- (vst1q_f16_x4, vst1q_f32_x4): New.
- (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
- (vst1q_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
- * config/arm/neon.md (neon_vst1q_x4<mode>): New.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New
- (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
- (vld1_f16_x2, vld1_f32_x2): New.
- (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
- (vld1_bf16_x2): New.
- (vld1q_types_x2): Updated to use vld1q_x2 from
- arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x2): Updated entries.
- (vld1q_x2): New entries, but comes from the old vld1_x2
- * config/arm/neon.md
- (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated
- from neon_vld1_x2<mode>.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New
- (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
- (vld1_f16_x3, vld1_f32_x3): New.
- (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
- (vld1_bf16_x3): New.
- (vld1q_types_x3): Updated to use vld1q_x3 from
- arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x3): Updated entries.
- (vld1q_x3): New entries, but comes from the old vld1_x2
- * config/arm/neon.md (neon_vld1q_x3<mode>): Updated from
- neon_vld1_x3<mode>.
-
-2023-12-08 Richard Earnshaw <rearnsha@arm.com>
-
- Revert:
- 2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New
- (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
- (vld1_f16_x4, vld1_f32_x4): New.
- (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
- (vld1_bf16_x4): New.
- (vld1q_types_x4): Updated to use vld1q_x4
- from arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x4): Updated entries.
- (vld1q_x4): New entries, but comes from the old vld1_x2
- * config/arm/neon.md (neon_vld1q_x4<mode>):
- Updated from neon_vld1_x4<mode>.
-
-2023-12-08 Tobias Burnus <tobias@codesourcery.com>
-
- * builtin-types.def (BT_FN_PTR_PTR_SIZE_PTRMODE_PTRMODE): New.
- * omp-builtins.def (BUILT_IN_GOMP_REALLOC): New.
- * builtins.cc (builtin_fnspec): Handle it.
- * gimple-ssa-warn-access.cc (fndecl_alloc_p,
- matching_alloc_calls_p): Likewise.
- * gimple.cc (nonfreeing_call_p): Likewise.
- * predict.cc (expr_expected_value_1): Likewise.
- * tree-ssa-ccp.cc (evaluate_stmt): Likewise.
- * tree.cc (fndecl_dealloc_argno): Likewise.
-
-2023-12-08 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112909
- * tree-ssa-uninit.cc (find_uninit_use): Look through a
- single level of SSA name copies with single use.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_try_expand_lsx_vshuf_const): Use
- simplify_gen_subreg instead of gen_rtx_SUBREG.
- (loongarch_expand_vec_perm_const_2): Ditto.
- (loongarch_expand_vec_cond_expr): Ditto.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_vector_costs::determine_suggested_unroll_factor):
- If m_has_recip is true, uf return 1.
- (loongarch_vector_costs::add_stmt_cost): Detect the use of approximate instruction sequence.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/genopts/loongarch.opt.in (recip_mask): New variable.
- (-mrecip, -mrecip): New options.
- * config/loongarch/lasx.md (div<mode>3): New expander.
- (*div<mode>3): Rename.
- (sqrt<mode>2): New expander.
- (*sqrt<mode>2): Rename.
- (rsqrt<mode>2): New expander.
- * config/loongarch/loongarch-protos.h (loongarch_emit_swrsqrtsf): New prototype.
- (loongarch_emit_swdivsf): Ditto.
- * config/loongarch/loongarch.cc (loongarch_option_override_internal): Set
- recip_mask for -mrecip and -mrecip= options.
- (loongarch_emit_swrsqrtsf): New function.
- (loongarch_emit_swdivsf): Ditto.
- * config/loongarch/loongarch.h (RECIP_MASK_NONE, RECIP_MASK_DIV, RECIP_MASK_SQRT
- RECIP_MASK_RSQRT, RECIP_MASK_VEC_DIV, RECIP_MASK_VEC_SQRT, RECIP_MASK_VEC_RSQRT
- RECIP_MASK_ALL): New bitmasks.
- (TARGET_RECIP_DIV, TARGET_RECIP_SQRT, TARGET_RECIP_RSQRT, TARGET_RECIP_VEC_DIV
- TARGET_RECIP_VEC_SQRT, TARGET_RECIP_VEC_RSQRT): New tests.
- * config/loongarch/loongarch.md (sqrt<mode>2): New expander.
- (*sqrt<mode>2): Rename.
- (rsqrt<mode>2): New expander.
- * config/loongarch/loongarch.opt (recip_mask): New variable.
- (-mrecip, -mrecip): New options.
- * config/loongarch/lsx.md (div<mode>3): New expander.
- (*div<mode>3): Rename.
- (sqrt<mode>2): New expander.
- (*sqrt<mode>2): Rename.
- (rsqrt<mode>2): New expander.
- * config/loongarch/predicates.md (reg_or_vecotr_1_operand): New predicate.
- * doc/invoke.texi (LoongArch Options): Document new options.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/lasx.md (lasx_xvfrecip_<flasxfmt>): Renamed to ..
- (recip<mode>3): .. this.
- * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vfrecip_d): Redefine
- to new pattern name.
- (CODE_FOR_lsx_vfrecip_s): Ditto.
- (CODE_FOR_lasx_xvfrecip_d): Ditto.
- (CODE_FOR_lasx_xvfrecip_s): Ditto.
- (loongarch_expand_builtin_direct): For the vector recip instructions, construct a
- temporary parameter const1_vector.
- * config/loongarch/lsx.md (lsx_vfrecip_<flsxfmt>): Renamed to ..
- (recip<mode>3): .. this.
- * config/loongarch/predicates.md (const_vector_1_operand): New predicate.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/lasx.md (lasx_xvfrsqrt_<flasxfmt>): Renamed to ..
- (rsqrt<mode>2): .. this.
- * config/loongarch/loongarch-builtins.cc
- (CODE_FOR_lsx_vfrsqrt_d): Redefine to standard pattern name.
- (CODE_FOR_lsx_vfrsqrt_s): Ditto.
- (CODE_FOR_lasx_xvfrsqrt_d): Ditto.
- (CODE_FOR_lasx_xvfrsqrt_s): Ditto.
- * config/loongarch/loongarch.cc (use_rsqrt_p): New function.
- (loongarch_optab_supported_p): Ditto.
- (TARGET_OPTAB_SUPPORTED_P): New hook.
- * config/loongarch/loongarch.md (*rsqrt<mode>a): Remove.
- (*rsqrt<mode>2): New insn pattern.
- (*rsqrt<mode>b): Remove.
- * config/loongarch/lsx.md (lsx_vfrsqrt_<flsxfmt>): Renamed to ..
- (rsqrt<mode>2): .. this.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/genopts/isa-evolution.in (fecipe): Add.
- * config/loongarch/larchintrin.h (__frecipe_s): New intrinsic.
- (__frecipe_d): Ditto.
- (__frsqrte_s): Ditto.
- (__frsqrte_d): Ditto.
- * config/loongarch/lasx.md (lasx_xvfrecipe_<flasxfmt>): New insn pattern.
- (lasx_xvfrsqrte_<flasxfmt>): Ditto.
- * config/loongarch/lasxintrin.h (__lasx_xvfrecipe_s): New intrinsic.
- (__lasx_xvfrecipe_d): Ditto.
- (__lasx_xvfrsqrte_s): Ditto.
- (__lasx_xvfrsqrte_d): Ditto.
- * config/loongarch/loongarch-builtins.cc (AVAIL_ALL): Add predicates.
- (LSX_EXT_BUILTIN): New macro.
- (LASX_EXT_BUILTIN): Ditto.
- * config/loongarch/loongarch-cpucfg-map.h: Regenerate.
- * config/loongarch/loongarch-c.cc: Add builtin macro "__loongarch_frecipe".
- * config/loongarch/loongarch-def.cc: Regenerate.
- * config/loongarch/loongarch-str.h (OPTSTR_FRECIPE): Regenerate.
- * config/loongarch/loongarch.cc (loongarch_asm_code_end): Dump status for TARGET_FRECIPE.
- * config/loongarch/loongarch.md (loongarch_frecipe_<fmt>): New insn pattern.
- (loongarch_frsqrte_<fmt>): Ditto.
- * config/loongarch/loongarch.opt: Regenerate.
- * config/loongarch/lsx.md (lsx_vfrecipe_<flsxfmt>): New insn pattern.
- (lsx_vfrsqrte_<flsxfmt>): Ditto.
- * config/loongarch/lsxintrin.h (__lsx_vfrecipe_s): New intrinsic.
- (__lsx_vfrecipe_d): Ditto.
- (__lsx_vfrsqrte_s): Ditto.
- (__lsx_vfrsqrte_d): Ditto.
- * doc/extend.texi: Add documentation for LoongArch new builtins and intrinsics.
-
-2023-12-08 Richard Biener <rguenther@suse.de>
-
- * tree-outof-ssa.cc (rewrite_out_of_ssa): Dump GIMPLE once only,
- after final IL adjustments.
-
-2023-12-08 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector-iterators.md: Replace RVVM2SI to RVVM2SF
- for mode attr V_F2DI_CONVERT_BRIDGE.
-
-2023-12-08 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/lasx.md (xorsign<mode>3): New expander.
- * config/loongarch/loongarch.cc (loongarch_can_change_mode_class): Allow
- conversion between LSX vector mode and scalar fp mode.
- * config/loongarch/loongarch.md (@xorsign<mode>3): New expander.
- * config/loongarch/lsx.md (@xorsign<mode>3): Ditto.
-
-2023-12-08 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112902
- * gimple-lower-bitint.cc (gimple_lower_bitint): For a narrowing
- or same precision cast don't set SSA_NAME_VERSION in m_names only
- if use_stmt is mergeable_op or fall through into the check that
- use is a store or rhs1 is not mergeable or other reasons prevent
- merging.
-
-2023-12-08 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112901
- * vr-values.cc
- (simplify_using_ranges::simplify_float_conversion_using_ranges):
- Return false if rhs1 has BITINT_TYPE type with BLKmode TYPE_MODE.
-
-2023-12-08 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112411
- * haifa-sched.cc (extend_h_i_d): Use 3U instead of 3 in
- 3 * get_max_uid () / 2 calculation.
-
-2023-12-08 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/genopts/loongarch-strings: Delete STR_ISA_BASE_LA64V110.
- * config/loongarch/genopts/loongarch.opt.in: Likewise.
- * config/loongarch/loongarch-cpu.cc (ISA_BASE_LA64V110_FEATURES): Delete macro.
- (fill_native_cpu_config): Define a new variable hw_isa_evolution record the
- extended instruction set support read from cpucfg.
- * config/loongarch/loongarch-def.cc: Set evolution at initialization.
- * config/loongarch/loongarch-def.h (ISA_BASE_LA64V100): Delete.
- (ISA_BASE_LA64V110): Likewise.
- (N_ISA_BASE_TYPES): Likewise.
- (defined): Likewise.
- * config/loongarch/loongarch-opts.cc: Likewise.
- * config/loongarch/loongarch-opts.h (TARGET_64BIT): Likewise.
- (ISA_BASE_IS_LA64V110): Likewise.
- * config/loongarch/loongarch-str.h (STR_ISA_BASE_LA64V110): Likewise.
- * config/loongarch/loongarch.opt: Regenerate.
-
-2023-12-08 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-def.h: Remove extern "C".
- (loongarch_isa_base_strings): Declare as loongarch_def_array
- instead of plain array.
- (loongarch_isa_ext_strings): Likewise.
- (loongarch_abi_base_strings): Likewise.
- (loongarch_abi_ext_strings): Likewise.
- (loongarch_cmodel_strings): Likewise.
- (loongarch_cpu_strings): Likewise.
- (loongarch_cpu_default_isa): Likewise.
- (loongarch_cpu_issue_rate): Likewise.
- (loongarch_cpu_multipass_dfa_lookahead): Likewise.
- (loongarch_cpu_cache): Likewise.
- (loongarch_cpu_align): Likewise.
- (loongarch_cpu_rtx_cost_data): Likewise.
- (loongarch_isa): Add a constructor and field setter functions.
- * config/loongarch/loongarch-opts.h (loongarch-defs.h): Do not
- include for target libraries.
- * config/loongarch/loongarch-opts.cc: Comment code that doesn't
- run and causes compilation errors.
- * config/loongarch/loongarch-tune.h (LOONGARCH_TUNE_H): Likewise.
- (struct loongarch_rtx_cost_data): Likewise.
- (struct loongarch_cache): Likewise.
- (struct loongarch_align): Likewise.
- * config/loongarch/t-loongarch: Compile loongarch-def.cc with the
- C++ compiler.
- * config/loongarch/loongarch-def-array.h: New file for a
- std:array like data structure with position setter function.
- * config/loongarch/loongarch-def.c: Rename to ...
- * config/loongarch/loongarch-def.cc: ... here.
- (loongarch_cpu_strings): Define as loongarch_def_array instead
- of plain array.
- (loongarch_cpu_default_isa): Likewise.
- (loongarch_cpu_cache): Likewise.
- (loongarch_cpu_align): Likewise.
- (loongarch_cpu_rtx_cost_data): Likewise.
- (loongarch_cpu_issue_rate): Likewise.
- (loongarch_cpu_multipass_dfa_lookahead): Likewise.
- (loongarch_isa_base_strings): Likewise.
- (loongarch_isa_ext_strings): Likewise.
- (loongarch_abi_base_strings): Likewise.
- (loongarch_abi_ext_strings): Likewise.
- (loongarch_cmodel_strings): Likewise.
- (abi_minimal_isa): Likewise.
- (loongarch_rtx_cost_optimize_size): Use field setter functions
- instead of designated initializers.
- (loongarch_rtx_cost_data): Implement default constructor.
-
-2023-12-08 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112411
- * params.opt (-param=min-nondebug-insn-uid=): Add
- IntegerRange(0, 1073741824).
- * lra.cc (check_and_expand_insn_recog_data): Use 3U rather than 3
- in * 3 / 2 computation and if the result is smaller or equal to
- index, use index + 1.
-
-2023-12-08 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/driver-i386.cc (host_detect_local_cpu):
- Do not append "-mno-" for Xeon Phi ISAs.
- * config/i386/i386-options.cc (ix86_option_override_internal):
- Emit a warning for KNL/KNM targets.
- * config/i386/i386.opt: Emit a warning for Xeon Phi ISAs.
-
-2023-12-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p):
- Remove redundant check.
-
-2023-12-08 Hao Liu <hliu@os.amperecomputing.com>
-
- PR tree-optimization/112774
- * tree-pretty-print.cc: if nonwrapping flag is set, chrec will be
- printed with additional <nw> info.
- * tree-scalar-evolution.cc: add record_nonwrapping_chrec and
- nonwrapping_chrec_p to set and check the new flag respectively.
- * tree-scalar-evolution.h: Likewise.
- * tree-ssa-loop-niter.cc (idx_infer_loop_bounds,
- infer_loop_bounds_from_pointer_arith, infer_loop_bounds_from_signedness,
- scev_probably_wraps_p): call record_nonwrapping_chrec before
- record_nonwrapping_iv, call nonwrapping_chrec_p to check the flag is
- set and return false from scev_probably_wraps_p.
- * tree-vect-loop.cc (vect_analyze_loop): call
- free_numbers_of_iterations_estimates explicitly.
- * tree-core.h: document the nothrow_flag usage in CHREC_NOWRAP
- * tree.h: add CHREC_NOWRAP(NODE), base.nothrow_flag is used to
- represent the nonwrapping info.
-
-2023-12-08 Fei Gao <gaofei@eswincomputing.com>
-
- * ifcvt.cc (noce_try_cond_zero_arith): New function.
- (noce_emit_czero, get_base_reg): Likewise.
- (noce_cond_zero_binary_op_supported): Likewise.
- (noce_bbs_ok_for_cond_zero_arith): Likewise.
- (noce_process_if_block): Use noce_try_cond_zero_arith.
- Co-authored-by: Xiao Zeng<zengxiao@eswincomputing.com>
-
-2023-12-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (expand_vec_series): Adapt function.
- * config/riscv/riscv-v.cc (rvv_builder::double_steps_npatterns_p): New function.
- (expand_vec_series): Adapt function.
- (expand_const_vector): Support new interleave vector with different step.
-
-2023-12-07 Richard Sandiford <richard.sandiford@arm.com>
-
- PR rtl-optimization/106694
- PR rtl-optimization/109078
- PR rtl-optimization/109391
- * config.gcc: Add aarch64-early-ra.o for AArch64 targets.
- * config/aarch64/t-aarch64 (aarch64-early-ra.o): New rule.
- * config/aarch64/aarch64-opts.h (aarch64_early_ra_scope): New enum.
- * config/aarch64/aarch64.opt (mearly_ra): New option.
- * doc/invoke.texi: Document it.
- * common/config/aarch64/aarch64-common.cc
- (aarch_option_optimization_table): Use -mearly-ra=strided by
- default for -O2 and above.
- * config/aarch64/aarch64-passes.def (pass_aarch64_early_ra): New pass.
- * config/aarch64/aarch64-protos.h (aarch64_strided_registers_p)
- (make_pass_aarch64_early_ra): Declare.
- * config/aarch64/aarch64-sme.md (@aarch64_sme_lut<LUTI_BITS><mode>):
- Add a stride_type attribute.
- (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): New pattern.
- (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
- * config/aarch64/aarch64-sve-builtins-base.cc (svld1_impl::expand)
- (svldnt1_impl::expand, svst1_impl::expand, svstn1_impl::expand): Handle
- new way of defining multi-register loads and stores.
- * config/aarch64/aarch64-sve.md (@aarch64_ld1<SVE_FULLx24:mode>)
- (@aarch64_ldnt1<SVE_FULLx24:mode>, @aarch64_st1<SVE_FULLx24:mode>)
- (@aarch64_stnt1<SVE_FULLx24:mode>): Delete.
- * config/aarch64/aarch64-sve2.md (@aarch64_<LD1_COUNT:optab><mode>)
- (@aarch64_<LD1_COUNT:optab><mode>_strided2): New patterns.
- (@aarch64_<LD1_COUNT:optab><mode>_strided4): Likewise.
- (@aarch64_<ST1_COUNT:optab><mode>): Likewise.
- (@aarch64_<ST1_COUNT:optab><mode>_strided2): Likewise.
- (@aarch64_<ST1_COUNT:optab><mode>_strided4): Likewise.
- * config/aarch64/aarch64.cc (aarch64_strided_registers_p): New
- function.
- * config/aarch64/aarch64.md (UNSPEC_LD1_SVE_COUNT): Delete.
- (UNSPEC_ST1_SVE_COUNT, UNSPEC_LDNT1_SVE_COUNT): Likewise.
- (UNSPEC_STNT1_SVE_COUNT): Likewise.
- (stride_type): New attribute.
- * config/aarch64/constraints.md (Uwd, Uwt): New constraints.
- * config/aarch64/iterators.md (UNSPEC_LD1_COUNT, UNSPEC_LDNT1_COUNT)
- (UNSPEC_ST1_COUNT, UNSPEC_STNT1_COUNT): New unspecs.
- (optab): Handle them.
- (LD1_COUNT, ST1_COUNT): New iterators.
- * config/aarch64/aarch64-early-ra.cc: New file.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New
- (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
- (vld1_f16_x4, vld1_f32_x4): New.
- (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
- (vld1_bf16_x4): New.
- (vld1q_types_x4): Updated to use vld1q_x4
- from arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x4): Updated entries.
- (vld1q_x4): New entries, but comes from the old vld1_x2
- * config/arm/neon.md (neon_vld1q_x4<mode>):
- Updated from neon_vld1_x4<mode>.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New
- (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
- (vld1_f16_x3, vld1_f32_x3): New.
- (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
- (vld1_bf16_x3): New.
- (vld1q_types_x3): Updated to use vld1q_x3 from
- arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x3): Updated entries.
- (vld1q_x3): New entries, but comes from the old vld1_x2
- * config/arm/neon.md (neon_vld1q_x3<mode>): Updated from
- neon_vld1_x3<mode>.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New
- (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
- (vld1_f16_x2, vld1_f32_x2): New.
- (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
- (vld1_bf16_x2): New.
- (vld1q_types_x2): Updated to use vld1q_x2 from
- arm_neon_builtins.def
- * config/arm/arm_neon_builtins.def
- (vld1_x2): Updated entries.
- (vld1q_x2): New entries, but comes from the old vld1_x2
- * config/arm/neon.md
- (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated
- from neon_vld1_x2<mode>.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
- (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
- (vst1q_f16_x4, vst1q_f32_x4): New.
- (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
- (vst1q_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
- * config/arm/neon.md (neon_vst1q_x4<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
- (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
- (vst1q_f16_x3, vst1q_f32_x3): New.
- (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
- (vst1q_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
- * config/arm/neon.md (neon_vst1q_x3<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
- (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
- (vst1q_f16_x2, vst1q_f32_x2): New.
- (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
- (vst1q_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vst1q_x2): New entries.
- * config/arm/neon.md
- (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
- neon_vst1_x2<mode>.
- * config/arm/iterators.md (VMEMX2): New mode iterator.
- (VMEMX2_q): New mode attribute.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
- (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
- (vst1_f16_x4, vst1_f32_x4): New.
- (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
- (vst1_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
- * config/arm/neon.md (vst1_x4<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
- (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
- (vst1_f16_x3, vst1_f32_x3): New.
- (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
- (vst1_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
- * config/arm/neon.md (vst1_x3<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
- (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
- (vst1_f16_x2, vst1_f32_x2): New.
- (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
- (vst1_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
- * config/arm/neon.md (vst1_x2<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
- (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
- (vld1q_f16_x4, vld1q_f32_x4): New.
- (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
- (vld1q_bf16_x4): New.
- * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
- * config/arm/neon.md (vld1_x4<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
- (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
- (vld1q_f16_x3, vld1q_f32_x3): New.
- (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
- (vld1q_bf16_x3): New.
- * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
- * config/arm/neon.md (vld1_x3<mode>): New.
-
-2023-12-07 Ezra Sitorus <ezra.sitorus@arm.com>
-
- * config/arm/arm_neon.h
- (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
- (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
- (vld1q_f16_x2, vld1q_f32_x2): New.
- (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
- (vld1q_bf16_x2): New.
- * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
- * config/arm/neon.md (vld1_x2<mode>): New.
-
-2023-12-07 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/vecintrin.h (vec_step): Expand vec_step to
- __builtin_s390_vec_step.
-
-2023-12-07 Alexandre Oliva <oliva@adacore.com>
-
- * target.def (have_strub_support_for): New hook.
- * doc/tm.texi.in: Document it.
- * doc/tm.texi: Rebuild.
- * ipa-strub.cc: Include target.h.
- (strub_target_support_p): New.
- (can_strub_p): Call it. Test for no flag_split_stack.
- (pass_ipa_strub::adjust_at_calls_call): Check for target
- support.
- * config/nvptx/nvptx.cc (TARGET_HAVE_STRUB_SUPPORT_FOR):
- Disable.
- * doc/sourcebuild.texi (strub): Document new effective
- target.
-
-2023-12-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-avlprop.cc (simplify_replace_avl): New function.
- (simplify_replace_vlmax_avl): Fix bug.
- * config/riscv/t-riscv: Add a new include file.
-
-2023-12-07 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/thead.cc (th_memidx_classify_address_index):
- Require TARGET_XTHEADMEMIDX for FP modes.
- * config/riscv/thead.md: Require TARGET_XTHEADMEMIDX for all
- XTheadFMemIdx pattern.
-
-2023-12-07 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112881
- * expr.cc (count_type_elements): Handle BITINT_TYPE like INTEGER_TYPE.
-
-2023-12-07 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112880
- * tree-ssa-dce.cc (maybe_optimize_arith_overflow): Use
- unsigned_type_for instead of conditionally calling
- build_nonstandard_integer_type.
-
-2023-12-07 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/arm_neon.h (vldap1_lane_u64): New.
- (vldap1q_lane_u64): Likewise.
- (vldap1_lane_s64): Likewise.
- (vldap1q_lane_s64): Likewise.
- (vldap1_lane_f64): Likewise.
- (vldap1q_lane_f64): Likewise.
- (vldap1_lane_p64): Likewise.
- (vldap1q_lane_p64): Likewise.
- (vstl1_lane_u64): Likewise.
- (vstl1q_lane_u64): Likewise.
- (vstl1_lane_s64): Likewise.
- (vstl1q_lane_s64): Likewise.
- (vstl1_lane_f64): Likewise.
- (vstl1q_lane_f64): Likewise.
- (vstl1_lane_p64): Likewise.
- (vstl1q_lane_p64): Likewise.
-
-2023-12-07 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-simd-builtins.def
- (vec_ldap1_lane): New.
- (vec_stl1_lane): Likewise.
- * config/aarch64/aarch64-simd.md
- (aarch64_vec_stl1_lanes<mode>_lane<Vel>): New.
- (aarch64_vec_stl1_lane<mode>): Likewise.
- (aarch64_vec_ldap1_lanes<mode>_lane<Vel>): Likewise.
- (aarch64_vec_ldap1_lane<mode>): Likewise.
- * config/aarch64/aarch64.md (UNSPEC_LDAP1_LANE): New.
- (UNSPEC_STL1_LANE): Likewise.
-
-2023-12-07 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/iterators.md (V12DIF): New.
- (V12DUP): Likewise.
- (VEL): Add support for all V12DIF-associated modes.
- (Vetype): Add support for V1DI and V1DF.
- (Vel): Likewise.
-
-2023-12-07 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-option-extensions.def (rcpc3): New.
- * config/aarch64/aarch64.h (AARCH64_ISA_RCPC3): Likewise.
- (TARGET_RCPC3): Likewise.
- * doc/invoke.texi (rcpc3): Document feature in AArch64 Options.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386-expand.cc (ix86_split_ashl_ndd): New
- function to split NDD form lshift.
- (ix86_split_rshift_ndd): Likewise for l/ashiftrt.
- * config/i386/i386-protos.h (ix86_split_ashl_ndd): New
- prototype.
- (ix86_split_rshift_ndd): Likewise.
- * config/i386/i386.md (ashl<mode>3_doubleword): Add NDD
- alternative, call ndd split function when operands[0]
- not equal to operands[1].
- (define_split for doubleword lshift): Likewise.
- (define_peephole for doubleword lshift): Likewise.
- (<insn><mode>3_doubleword): Likewise for l/ashiftrt.
- (define_split for doubleword l/ashiftrt): Likewise.
- (define_peephole for doubleword l/ashiftrt): Likewise.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (*mov<mode>cc_noc): Extend with new constraints
- to support NDD.
- (*movsicc_noc_zext): Likewise.
- (*movsicc_noc_zext_1): Likewise.
- (*movqicc_noc): Likewise.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (x86_64_shld_ndd): New define_insn.
- (x86_64_shld_ndd_1): Likewise.
- (*x86_64_shld_ndd_2): Likewise.
- (x86_shld_ndd): Likewise.
- (x86_shld_ndd_1): Likewise.
- (*x86_shld_ndd_2): Likewise.
- (x86_64_shrd_ndd): Likewise.
- (x86_64_shrd_ndd_1): Likewise.
- (*x86_64_shrd_ndd_2): Likewise.
- (x86_shrd_ndd): Likewise.
- (x86_shrd_ndd_1): Likewise.
- (*x86_shrd_ndd_2): Likewise.
- (*x86_64_shld_shrd_1_nozext): Adjust codegen under TARGET_APX_NDD.
- (*x86_shld_shrd_1_nozext): Likewise.
- (*x86_64_shrd_shld_1_nozext): Likewise.
- (*x86_shrd_shld_1_nozext): Likewise.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (*<insn><mode>3_1): Extend with a new
- alternative to support NDD for SI/DI rotate, and adjust output
- template.
- (*<insn>si3_1_zext): Likewise.
- (*<insn><mode>3_1): Likewise for QI/HI modes.
- (rcrsi2): Likewise, and use nonimmediate_operand for operands[1]
- to accept memory input for NDD alternative.
- (rcrdi2): Likewise.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (ashr<mode>3_cvt): Extend with new
- alternatives to support NDD, and adjust output templates.
- (*ashr<mode>3_1): Likewise for SI/DI mode.
- (*lshr<mode>3_1): Likewise.
- (*<insn>si3_1_zext): Likewise.
- (*ashr<mode>3_1): Likewise for QI/HI mode.
- (*lshrqi3_1): Likewise.
- (*lshrhi3_1): Likewise.
- (<insn><mode>3_cmp): Likewise.
- (*<insn><mode>3_cconly): Likewise.
- (*ashrsi3_cvt_zext): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
- (*highpartdisi2): Likewise.
- (*<insn>si3_cmp_zext): Likewise.
- (<insn><mode>3_carry): Likewise.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (*ashl<mode>3_1): Extend with new
- alternatives to support NDD, limit the new alternative to
- generate sal only, and adjust output template for NDD.
- (*ashlsi3_1_zext): Likewise.
- (*ashlhi3_1): Likewise.
- (*ashlqi3_1): Likewise.
- (*ashl<mode>3_cmp): Likewise.
- (*ashlsi3_cmp_zext): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
- (*ashl<mode>3_cconly): Likewise.
- (*ashl<dwi>3_doubleword_highpart): Adjust codegen for NDD.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md (<code><mode>3): Add new alternative for NDD
- and adjust output templates.
- (*<code><mode>_1): Likewise.
- (*<code>qi_1): Likewise.
- (*notxor<mode>_1): Likewise.
- (*<code>si_1_zext): Likewise.
- (*notxorqi_1): Likewise.
- (*<code><mode>_2): Likewise.
- (*<code>si_2_zext): Likewise.
- (*<code>si_2_zext_imm): Likewise.
- (*<code>si_1_zext_imm): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
- (*one_cmplsi2_2_zext): Likewise.
- (define_split for *one_cmplsi2_2_zext): Use nonimmediate_operand for
- operands[3].
- (*<code><dwi>3_doubleword): Add NDD constraints, adopt '&' to NDD dest
- and emit move for optimized case if operands[0] != operands[1] or
- operands[4] != operands[5].
- (define_split for QI highpart OR/XOR): Prohibit splitter to split NDD
- form OR/XOR insn to <any_logic:code>qi_ext<mode>_3.
- (define_split for QI strict_lowpart optimization): Prohibit splitter to
- split NDD form AND insn to *<code><mode>3_1_slp.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md (and<mode>3): Add NDD alternatives and adjust
- output template.
- (*anddi_1): Likewise.
- (*and<mode>_1): Likewise.
- (*andqi_1): Likewise.
- (*andsi_1_zext): Likewise.
- (*anddi_2): Likewise.
- (*andsi_2_zext): Likewise.
- (*andqi_2_maybe_si): Likewise.
- (*and<mode>_2): Likewise.
- (*and<dwi>3_doubleword): Add NDD alternative, adopt '&' to NDD dest and
- emit move for optimized case if operands[0] not equal to operands[1].
- (define_split for QI highpart AND): Prohibit splitter to split NDD
- form AND insn to <any_logic:code>qi_ext<mode>_3.
- (define_split for QI strict_lowpart optimization): Prohibit splitter to
- split NDD form AND insn to *<code><mode>3_1_slp.
- (define_split for zero_extend and optimization): Prohibit splitter to
- split NDD form AND insn to zero_extend insn.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md (one_cmpl<mode>2): Add new constraints for NDD
- and adjust output template.
- (*one_cmpl<mode>2_1): Likewise.
- (*one_cmplqi2_1): Likewise.
- (*one_cmpl<dwi>2_doubleword): Likewise, and adopt '&' to NDD dest.
- (*one_cmpl<mode>2_2): Likewise.
- (*one_cmplsi2_1_zext): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386-expand.cc (ix86_expand_unary_operator): Add use_ndd
- parameter and adjust for NDD.
- * config/i386/i386-protos.h: Add use_ndd parameter for
- ix86_unary_operator_ok and ix86_expand_unary_operator.
- * config/i386/i386.cc (ix86_unary_operator_ok): Add use_ndd parameter
- and adjust for NDD.
- * config/i386/i386.md (neg<mode>2): Add new constraint for NDD and
- adjust output template.
- (*neg<mode>_1): Likewise.
- (*neg<dwi>2_doubleword): Likewise and adopt '&' to NDD dest.
- (*neg<mode>_2): Likewise.
- (*neg<mode>_ccc_1): Likewise.
- (*neg<mode>_ccc_2): Likewise.
- (*negsi_1_zext): Likewise, and use nonimmediate_operand for operands[1]
- to accept memory input for NDD alternatives.
- (*negsi_2_zext): Likewise.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md (*sub<dwi>3_doubleword): Add new alternative for
- NDD, adopt '&' modifier to NDD dest and emit move when operands[0] not
- equal to operands[1].
- (*sub<dwi>3_doubleword_zext): Likewise.
- (*subv<dwi>4_doubleword): Likewise.
- (*subv<dwi>4_doubleword_1): Likewise.
- (*subv<mode>4_overflow_1): Add NDD alternatives and adjust output
- templates.
- (*subv<mode>4_overflow_2): Likewise.
- (@sub<mode>3_carry): Likewise.
- (*addsi3_carry_zext_0r): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
- (*subsi3_carry_zext): Likewise.
- (subborrow<mode>): Parse TARGET_APX_NDD to ix86_binary_operator_ok.
- (subborrow<mode>_0): Likewise.
- (*sub<mode>3_eq): Likewise.
- (*sub<mode>3_ne): Likewise.
- (*sub<mode>3_eq_1): Likewise.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386-expand.cc (ix86_fixup_binary_operands_no_copy):
- Add use_ndd parameter and parse it.
- * config/i386/i386-protos.h (ix86_fixup_binary_operands_no_copy):
- Change define.
- * config/i386/i386.md (sub<mode>3): Add new alternatives for NDD
- and adjust output templates.
- (*sub<mode>_1): Likewise.
- (*sub<mode>_2): Likewise.
- (subv<mode>4): Likewise.
- (*subv<mode>4): Likewise.
- (subv<mode>4_1): Likewise.
- (usubv<mode>4): Likewise.
- (*sub<mode>_3): Likewise.
- (*subsi_1_zext): Likewise, and use nonimmediate_operand for operands[1]
- to accept memory input for NDD alternatives.
- (*subsi_2_zext): Likewise.
- (*subsi_3_zext): Likewise.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md (*add<dwi>3_doubleword): Add ndd alternatives,
- adopt '&' to ndd dest and move operands[1] to operands[0] when they are
- not equal.
- (*add<dwi>3_doubleword_cc_overflow_1): Likewise.
- (*addv<dwi>4_doubleword): Likewise.
- (*addv<dwi>4_doubleword_1): Likewise.
- (*add<dwi>3_doubleword_zext): Likewise.
- (addv<mode>4_overflow_1): Add ndd alternatives.
- (*addv<mode>4_overflow_2): Likewise.
- (@add<mode>3_carry): Likewise.
- (*add<mode>3_carry_0): Likewise.
- (*addsi3_carry_zext): Likewise.
- (addcarry<mode>): Likewise.
- (addcarry<mode>_0): Likewise.
- (*addcarry<mode>_1): Likewise.
- (*add<mode>3_eq): Likewise.
- (*add<mode>3_ne): Likewise.
- (*addsi3_carry_zext_0): Likewise, and use nonimmediate_operand for
- operands[1] to accept memory input for NDD alternative.
-
-2023-12-07 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/constraints.md (je): New constraint.
- * config/i386/i386-protos.h (x86_poff_operand_p): New function to
- check any *POFF constant in operand.
- * config/i386/i386.cc (x86_poff_operand_p): New prototype.
- * config/i386/i386.md (*add<mode>_1): Split out je alternative for add.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386.md: (addsi_1_zext): Add new alternatives for
- NDD and adjust output templates.
- (*add<mode>_2): Likewise.
- (*addsi_2_zext): Likewise.
- (*add<mode>_3): Likewise.
- (*addsi_3_zext): Likewise.
- (*adddi_4): Likewise.
- (*add<mode>_4): Likewise.
- (*add<mode>_5): Likewise.
- (*addv<mode>4): Likewise.
- (*addv<mode>4_1): Likewise.
- (*add<mode>3_cconly_overflow_1): Likewise.
- (*add<mode>3_cc_overflow_1): Likewise.
- (*addsi3_zext_cc_overflow_1): Likewise.
- (*add<mode>3_cconly_overflow_2): Likewise.
- (*add<mode>3_cc_overflow_2): Likewise.
- (*addsi3_zext_cc_overflow_2): Likewise.
-
-2023-12-07 Kong Lingling <lingling.kong@intel.com>
-
- * config/i386/i386-expand.cc (ix86_fixup_binary_operands): Add
- new use_ndd flag to check whether ndd can be used for this binop
- and adjust operand emit.
- (ix86_binary_operator_ok): Likewise.
- (ix86_expand_binary_operator): Likewise, and void postreload
- expand generate lea pattern when use_ndd is explicit parsed.
- * config/i386/i386-options.cc (ix86_option_override_internal):
- Prohibit apx subfeatures when not in 64bit mode.
- * config/i386/i386-protos.h (ix86_binary_operator_ok):
- Add use_ndd flag.
- (ix86_fixup_binary_operand): Likewise.
- (ix86_expand_binary_operand): Likewise.
- * config/i386/i386.md (*add<mode>_1): Extend with new alternatives
- to support NDD, and adjust output template.
- (*addhi_1): Likewise.
- (*addqi_1): Likewise.
-
-2023-12-07 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/103546
- PR analyzer/112850
- * doc/invoke.texi: Add -Wanalyzer-symbol-too-complex.
-
-2023-12-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (extract_single_source): new function.
- (pre_vsetvl::compute_lcm_local_properties): Fix ICE.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-builtins.cc (AARCH64_RSR128): New
- `enum aarch64_builtins' value.
- (AARCH64_WSR128): Likewise.
- (aarch64_init_rwsr_builtins): Init `__builtin_aarch64_rsr128'
- and `__builtin_aarch64_wsr128' builtins.
- (aarch64_expand_rwsr_builtin): Extend function to handle
- `__builtin_aarch64_{rsr|wsr}128'.
- * config/aarch64/aarch64-protos.h (aarch64_retrieve_sysreg):
- Update function signature.
- * config/aarch64/aarch64.cc (F_REG_128): New.
- (aarch64_retrieve_sysreg): Add 128-bit register mode check.
- * config/aarch64/aarch64.md (UNSPEC_SYSREG_RTI): New.
- (UNSPEC_SYSREG_WTI): Likewise.
- (aarch64_read_sysregti): Likewise.
- (aarch64_write_sysregti): Likewise.
- * config/aarch64/arm_acle.h (__arm_rsr128): New.
- (__arm_wsr128): Likewise.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-option-extensions.def (gcs): New.
- * config/aarch64/aarch64.h (AARCH64_ISA_GCS): New.
- (TARGET_THE): Likewise.
- * doc/invoke.texi (AArch64 Options): Describe GCS.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-c.cc (__ARM_FEATURE_SYSREG128): New.
- * config/aarch64/aarch64-arches.def (armv8.9-a): New.
- (armv9.4-a): Likewise.
- * config/aarch64/aarch64-option-extensions.def (d128): Likewise.
- (the): Likewise.
- * config/aarch64/aarch64.h (AARCH64_ISA_V9_4A): Likewise.
- (AARCH64_ISA_V8_9A): Likewise.
- (TARGET_ARMV9_4): Likewise.
- (AARCH64_ISA_D128): Likewise.
- (AARCH64_ISA_THE): Likewise.
- (TARGET_D128): Likewise.
- * doc/invoke.texi (AArch64 Options): Document new -march flags
- and extensions.
-
-2023-12-06 Eric Gallager <egallager@gcc.gnu.org>
-
- * Makefile.in: Remove qmtest-related targets.
-
-2023-12-06 David Malcolm <dmalcolm@redhat.com>
-
- * common.opt (fdiagnostics-json-formatting): New.
- * diagnostic-format-json.cc: Add "formatted" boolean
- to json_output_format and subclasses, and to the
- diagnostic_output_format_init_json_* functions. Use it when
- printing JSON.
- * diagnostic-format-sarif.cc: Likewise for sarif_builder,
- sarif_output_format, and the various
- diagnostic_output_format_init_sarif_* functions.
- * diagnostic.cc (diagnostic_output_format_init): Add
- "json_formatting" boolean and pass on to the various cases.
- * diagnostic.h (diagnostic_output_format_init): Add
- "json_formatted" param.
- (diagnostic_output_format_init_json_stderr): Add "formatted" param
- (diagnostic_output_format_init_json_file): Likewise.
- (diagnostic_output_format_init_sarif_stderr): Likewise.
- (diagnostic_output_format_init_sarif_file): Likewise.
- (diagnostic_output_format_init_sarif_stream): Likewise.
- * doc/invoke.texi (-fdiagnostics-format=json): Remove discussion
- about JSON output needing formatting.
- (-fno-diagnostics-json-formatting): Add.
- * gcc.cc (driver_handle_option): Use
- opts->x_flag_diagnostics_json_formatting.
- * gcov.cc (generate_results): Pass "false" for new formatting
- option when printing json.
- * json.cc (value::dump): Add new "formatted" param.
- (object::print): Likewise, using it to add whitespace to format
- the JSON output.
- (array::print): Likewise.
- (float_number::print): Add new "formatted" param.
- (integer_number::print): Likewise.
- (string::print): Likewise.
- (literal::print): Likewise.
- (selftest::assert_print_eq): Add "formatted" param.
- (ASSERT_PRINT_EQ): Add "FORMATTED" param.
- (selftest::test_writing_objects): Test both formatted and
- unformatted printing.
- (selftest::test_writing_arrays): Likewise.
- (selftest::test_writing_float_numbers): Update for new param of
- ASSERT_PRINT_EQ.
- (selftest::test_writing_integer_numbers): Likewise.
- (selftest::test_writing_strings): Likewise.
- (selftest::test_writing_literals): Likewise.
- (selftest::test_formatting): New.
- (selftest::json_cc_tests): Call it.
- * json.h (value::print): Add "formatted" param.
- (value::dump): Likewise.
- (object::print): Likewise.
- (array::print): Likewise.
- (float_number::print): Likewise.
- (integer_number::print): Likewise.
- (string::print): Likewise.
- (literal::print): Likewise.
- * optinfo-emit-json.cc (optrecord_json_writer::write): Pass
- "false" for new formatting option when printing json.
- (selftest::test_building_json_from_dump_calls): Likewise.
- * opts.cc (common_handle_option): Use
- opts->x_flag_diagnostics_json_formatting.
-
-2023-12-06 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-format-json.cc (on_begin_diagnostic): Convert param
- to const reference.
- (on_end_diagnostic): Likewise.
- (json_output_format::on_end_diagnostic): Likewise.
- * diagnostic-format-sarif.cc
- (sarif_invocation::add_notification_for_ice): Likewise.
- (sarif_result::on_nested_diagnostic): Likewise.
- (sarif_ice_notification::sarif_ice_notification): Likewise.
- (sarif_builder::end_diagnostic): Likewise.
- (sarif_builder::make_result_object): Likewise.
- (make_reporting_descriptor_object_for_warning): Likewise.
- (sarif_builder::make_locations_arr): Likewise.
- (sarif_output_format::on_begin_diagnostic): Likewise.
- (sarif_output_format::on_end_diagnostic): Likewise.
- * diagnostic.cc (default_diagnostic_starter): Make diagnostic_info
- param const.
- (default_diagnostic_finalizer): Likewise.
- (diagnostic_context::report_diagnostic): Pass diagnostic by
- reference to on_{begin,end}_diagnostic.
- (diagnostic_text_output_format::on_begin_diagnostic): Convert
- param to const reference.
- (diagnostic_text_output_format::on_end_diagnostic): Likewise.
- * diagnostic.h (diagnostic_starter_fn): Make diagnostic_info param
- const.
- (diagnostic_finalizer_fn): Likeewise.
- (diagnostic_output_format::on_begin_diagnostic): Convert param to
- const reference.
- (diagnostic_output_format::on_end_diagnostic): Likewise.
- (diagnostic_text_output_format::on_begin_diagnostic): Likewise.
- (diagnostic_text_output_format::on_end_diagnostic): Likewise.
- (default_diagnostic_starter): Make diagnostic_info param const.
- (default_diagnostic_finalizer): Likewise.
- * langhooks-def.h (lhd_print_error_function): Make diagnostic_info
- param const.
- * langhooks.cc (lhd_print_error_function): Likewise.
- * langhooks.h (lang_hooks::print_error_function): Likewise.
- * tree-diagnostic.cc (diagnostic_report_current_function):
- Likewise.
- (default_tree_diagnostic_starter): Likewise.
- (virt_loc_aware_diagnostic_finalizer): Likewise.
- * tree-diagnostic.h (diagnostic_report_current_function):
- Likewise.
- (virt_loc_aware_diagnostic_finalizer): Likewise.
-
-2023-12-06 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-builtins.def (DISPATCH_PTR): New built-in.
- * config/gcn/gcn.cc (gcn_init_machine_status): Disable global
- addressing.
- (gcn_expand_builtin_1): Implement GCN_BUILTIN_DISPATCH_PTR.
-
-2023-12-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112855
- * config/riscv/riscv-vsetvl.cc
- (pre_vsetvl::compute_lcm_local_properties): Fix transparant LCM data.
- (pre_vsetvl::earliest_fuse_vsetvl_info): Disable earliest fusion for unrelated edge.
-
-2023-12-06 Marek Polacek <polacek@redhat.com>
-
- PR target/112762
- * config/linux.h: Redefine TARGET_FORTIFY_SOURCE_DEFAULT_LEVEL for
- glibc only.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64.cc
- (aarch64_test_sysreg_encoding_clashes): New.
- (aarch64_run_selftests): add call to
- aarch64_test_sysreg_encoding_clashes selftest.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-builtins.cc (aarch64_general_check_builtin_call):
- New.
- * config/aarch64/aarch64-c.cc (aarch64_check_builtin_call):
- Add `aarch64_general_check_builtin_call' call.
- * config/aarch64/aarch64-protos.h (aarch64_general_check_builtin_call):
- New.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-builtins.cc (enum aarch64_builtins):
- Add enums for new builtins.
- (aarch64_init_rwsr_builtins): New.
- (aarch64_general_init_builtins): Call aarch64_init_rwsr_builtins.
- (aarch64_expand_rwsr_builtin): New.
- (aarch64_general_expand_builtin): Call aarch64_general_expand_builtin.
- * config/aarch64/aarch64.md (read_sysregdi): New insn_and_split.
- (write_sysregdi): Likewise.
- * config/aarch64/arm_acle.h (__arm_rsr): New.
- (__arm_rsrp): Likewise.
- (__arm_rsr64): Likewise.
- (__arm_rsrf): Likewise.
- (__arm_rsrf64): Likewise.
- (__arm_wsr): Likewise.
- (__arm_wsrp): Likewise.
- (__arm_wsr64): Likewise.
- (__arm_wsrf): Likewise.
- (__arm_wsrf64): Likewise.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_valid_sysreg_name_p): New.
- (aarch64_retrieve_sysreg): Likewise.
- * config/aarch64/aarch64.cc (is_implem_def_reg): Likewise.
- (aarch64_valid_sysreg_name_p): Likewise.
- (aarch64_retrieve_sysreg): Likewise.
- (aarch64_register_sysreg): Likewise.
- (aarch64_init_sysregs): Likewise.
- (aarch64_lookup_sysreg_map): Likewise.
- * config/aarch64/predicates.md (aarch64_sysreg_string): New.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64.cc (sysreg_t): New.
- (aarch64_sysregs): Likewise.
- (AARCH64_FEATURE): Likewise.
- (AARCH64_FEATURES): Likewise.
- (AARCH64_NO_FEATURES): Likewise.
- * config/aarch64/aarch64.h (AARCH64_ISA_V8A): Add missing
- ISA flag.
- (AARCH64_ISA_V8_1A): Likewise.
- (AARCH64_ISA_V8_7A): Likewise.
- (AARCH64_ISA_V8_8A): Likewise.
- (AARCH64_NO_FEATURES): Likewise.
- (AARCH64_FL_RAS): New ISA flag alias.
- (AARCH64_FL_LOR): Likewise.
- (AARCH64_FL_PAN): Likewise.
- (AARCH64_FL_AMU): Likewise.
- (AARCH64_FL_SCXTNUM): Likewise.
- (AARCH64_FL_ID_PFR2): Likewise.
- (F_DEPRECATED): New.
- (F_REG_READ): Likewise.
- (F_REG_WRITE): Likewise.
- (F_ARCHEXT): Likewise.
- (F_REG_ALIAS): Likewise.
-
-2023-12-06 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64-sys-regs.def: New.
-
-2023-12-06 Robin Dapp <rdapp@ventanamicro.com>
-
- PR target/112854
- PR target/112872
- * config/riscv/autovec.md (vec_init<mode>qi): New expander.
-
-2023-12-06 Jakub Jelinek <jakub@redhat.com>
-
- PR rtl-optimization/112760
- * config/i386/i386-passes.def (pass_insert_vzeroupper): Insert
- after pass_postreload_cse rather than pass_reload.
- * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
- Adjust comment for it.
-
-2023-12-06 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112809
- * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt): For
- separate_ext in kind == bitint_prec_huge mode if rem == 0, create for
- i == cnt - 1 the loop rather than using size_int (end).
-
-2023-12-06 Jakub Jelinek <jakub@redhat.com>
-
- * gcc.cc (driver_handle_option): Add /* FALLTHROUGH */ comment
- between OPT_pie and OPT_r cases.
-
-2023-12-06 Tobias Burnus <tobias@codesourcery.com>
-
- * tsystem.h (calloc, realloc): Declare when inhibit_libc.
-
-2023-12-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112843
- * tree-ssa-operands.cc (update_stmt_operands): Do not call
- update_stmt from ranger.
- * value-query.h (range_query::update_stmt): Remove.
- * gimple-range.h (gimple_ranger::update_stmt): Likewise.
- * gimple-range.cc (gimple_ranger::update_stmt): Likewise.
-
-2023-12-06 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv.md: Remove.
-
-2023-12-06 Alexandre Oliva <oliva@adacore.com>
-
- * Makefile.in (OBJS): Add ipa-strub.o.
- (GTFILES): Add ipa-strub.cc.
- * builtins.def (BUILT_IN_STACK_ADDRESS): New.
- (BUILT_IN___STRUB_ENTER): New.
- (BUILT_IN___STRUB_UPDATE): New.
- (BUILT_IN___STRUB_LEAVE): New.
- * builtins.cc: Include ipa-strub.h.
- (STACK_STOPS, STACK_UNSIGNED): Define.
- (expand_builtin_stack_address): New.
- (expand_builtin_strub_enter): New.
- (expand_builtin_strub_update): New.
- (expand_builtin_strub_leave): New.
- (expand_builtin): Call them.
- * common.opt (fstrub=*): New options.
- * doc/extend.texi (strub): New type attribute.
- (__builtin_stack_address): New function.
- (Stack Scrubbing): New section.
- * doc/invoke.texi (-fstrub=*): New options.
- (-fdump-ipa-*): New passes.
- * gengtype-lex.l: Ignore multi-line pp-directives.
- * ipa-inline.cc: Include ipa-strub.h.
- (can_inline_edge_p): Test strub_inlinable_to_p.
- * ipa-split.cc: Include ipa-strub.h.
- (execute_split_functions): Test strub_splittable_p.
- * ipa-strub.cc, ipa-strub.h: New.
- * passes.def: Add strub_mode and strub passes.
- * tree-cfg.cc (gimple_verify_flow_info): Note on debug stmts.
- * tree-pass.h (make_pass_ipa_strub_mode): Declare.
- (make_pass_ipa_strub): Declare.
- (make_pass_ipa_function_and_variable_visibility): Fix
- formatting.
- * tree-ssa-ccp.cc (optimize_stack_restore): Keep restores
- before strub leave.
- * attribs.cc: Include ipa-strub.h.
- (decl_attributes): Support applying attributes to function
- type, rather than pointer type, at handler's request.
- (comp_type_attributes): Combine strub_comptypes and target
- comp_type results.
- * doc/tm.texi.in (TARGET_STRUB_USE_DYNAMIC_ARRAY): New.
- (TARGET_STRUB_MAY_USE_MEMSET): New.
- * doc/tm.texi: Rebuilt.
- * cgraph.h (symtab_node::reset): Add preserve_comdat_group
- param, with a default.
- * cgraphunit.cc (symtab_node::reset): Use it.
-
-2023-12-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112851
- PR target/112852
- * config/riscv/riscv-v.cc (vls_mode_valid_p): Block VLSmodes according
- TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR.
-
-2023-12-05 David Faust <david.faust@oracle.com>
-
- PR debug/112849
- * btfout.cc (btf_collect_datasec): Avoid incorrectly creating an
- entry in a BTF_KIND_DATASEC record for extern variable decls without
- a known section.
-
-2023-12-05 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112606
- * config/rs6000/rs6000.md (copysign<mode>3): Change predicate
- of the last argument from gpc_reg_operand to any_operand. If
- operands[2] is CONST_DOUBLE, emit abs or neg abs depending on
- its sign, otherwise if it doesn't satisfy gpc_reg_operand,
- force it to REG using copy_to_mode_reg.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * attribs.cc (handle_ignored_attributes_option): Add extra
- braces to work around PR 16333 in older compilers.
- * config/aarch64/aarch64.cc (aarch64_gnu_attribute_table): Likewise.
- (aarch64_arm_attribute_table): Likewise.
- * config/arm/arm.cc (arm_gnu_attribute_table): Likewise.
- * config/i386/i386-options.cc (ix86_gnu_attribute_table): Likewise.
- * config/ia64/ia64.cc (ia64_gnu_attribute_table): Likewise.
- * config/rs6000/rs6000.cc (rs6000_gnu_attribute_table): Likewise.
- * target-def.h (TARGET_GNU_ATTRIBUTES): Likewise.
- * genhooks.cc (emit_init_macros): Likewise, when emitting the
- instantiation of TARGET_ATTRIBUTE_TABLE.
- * langhooks-def.h (LANG_HOOKS_INITIALIZER): Likewise, when
- instantiating LANG_HOOKS_ATTRIBUTE_TABLE.
- (LANG_HOOKS_ATTRIBUTE_TABLE): Define to be empty by default.
- * target.def (attribute_table): Likewise.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112860
- * passes.cc (should_skip_pass_p): Do not skip ISEL.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR sanitizer/111736
- * asan.cc (asan_protect_global): Do not protect globals
- in non-generic address-space.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR ipa/92606
- * ipa-icf.cc (sem_variable::equals_wpa): Compare address-spaces.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112830
- * gimplify.cc (gimplify_modify_expr): Avoid turning aggregate
- copy of non-generic address-spaces to memcpy.
- (gimplify_modify_expr_to_memcpy): Assert we are dealing with
- a copy inside the generic address-space.
- (gimplify_modify_expr_to_memset): Likewise.
- * tree-cfg.cc (verify_gimple_assign_single): Allow
- WITH_SIZE_EXPR as part of the RHS of an assignment.
- * builtins.cc (get_memory_address): Assert we are dealing
- with the generic address-space.
- * tree-ssa-dce.cc (ref_may_be_aliased): Handle WITH_SIZE_EXPR.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/109689
- PR tree-optimization/112856
- * cfgloopmanip.h (unloop_loops): Adjust API.
- * tree-ssa-loop-ivcanon.cc (unloop_loops): Take edges_to_remove
- as parameter.
- (canonicalize_induction_variables): Adjust.
- (tree_unroll_loops_completely): Likewise.
- * tree-ssa-loop-ch.cc (ch_base::copy_headers): Rewrite into
- LC SSA if we unlooped some loops and we are in LC SSA.
-
-2023-12-05 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112845
- * config/i386/i386.md (movabsq $(i32 << shift), r64 peephole2): FAIL
- if the new immediate is ix86_endbr_immediate_operand.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (TARGET_STREAMING_SME2): New macro.
- (P_ALIASES): Likewise.
- (REGISTER_NAMES): Add pn aliases of the predicate registers.
- (W8_W11_REGNUM_P): New macro.
- (W8_W11_REGS): New register class.
- (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly.
- * config/aarch64/aarch64.cc (aarch64_print_operand): Add support
- for %K, which prints a predicate as a counter. Handle tuples of
- predicates.
- (aarch64_regno_regclass): Handle W8_W11_REGS.
- (aarch64_class_max_nregs): Likewise.
- * config/aarch64/constraints.md (Uci, Uw2, Uw4): New constraints.
- (x, y): Move further up file.
- (Uph): Redefine as the high predicate registers, renaming the old
- constraint to...
- (Uih): ...this.
- * config/aarch64/predicates.md (const_0_to_7_operand): New predicate.
- (const_0_to_4_step_4_operand, const_0_to_6_step_2_operand): Likewise.
- (const_0_to_12_step_4_operand, const_0_to_14_step_2_operand): Likewise.
- (aarch64_simd_shift_imm_qi): Use const_0_to_7_operand.
- * config/aarch64/iterators.md (VNx16SI_ONLY, VNx8SI_ONLY)
- (VNx8DI_ONLY, SVE_FULL_BHSIx2, SVE_FULL_HF, SVE_FULL_SIx2_SDIx4)
- (SVE_FULL_BHS, SVE_FULLx24, SVE_DIx24, SVE_BHSx24, SVE_Ix24)
- (SVE_Fx24, SVE_SFx24, SME_ZA_BIx24, SME_ZA_BHIx124, SME_ZA_BHIx24)
- (SME_ZA_HFx124, SME_ZA_HFx24, SME_ZA_HIx124, SME_ZA_HIx24)
- (SME_ZA_SDIx24, SME_ZA_SDFx24): New mode iterators.
- (UNSPEC_REVD, UNSPEC_CNTP_C, UNSPEC_PEXT, UNSPEC_PEXTx2): New unspecs.
- (UNSPEC_PSEL, UNSPEC_PTRUE_C, UNSPEC_SQRSHR, UNSPEC_SQRSHRN)
- (UNSPEC_SQRSHRU, UNSPEC_SQRSHRUN, UNSPEC_UQRSHR, UNSPEC_UQRSHRN)
- (UNSPEC_UZP, UNSPEC_UZPQ, UNSPEC_ZIP, UNSPEC_ZIPQ, UNSPEC_BFMLSLB)
- (UNSPEC_BFMLSLT, UNSPEC_FCVTN, UNSPEC_FDOT, UNSPEC_SQCVT): Likewise.
- (UNSPEC_SQCVTN, UNSPEC_SQCVTU, UNSPEC_SQCVTUN, UNSPEC_UQCVT): Likewise.
- (UNSPEC_SME_ADD, UNSPEC_SME_ADD_WRITE, UNSPEC_SME_BMOPA): Likewise.
- (UNSPEC_SME_BMOPS, UNSPEC_SME_FADD, UNSPEC_SME_FDOT, UNSPEC_SME_FVDOT)
- (UNSPEC_SME_FMLA, UNSPEC_SME_FMLS, UNSPEC_SME_FSUB, UNSPEC_SME_READ)
- (UNSPEC_SME_SDOT, UNSPEC_SME_SVDOT, UNSPEC_SME_SMLA, UNSPEC_SME_SMLS)
- (UNSPEC_SME_SUB, UNSPEC_SME_SUB_WRITE, UNSPEC_SME_SUDOT): Likewise.
- (UNSPEC_SME_SUVDOT, UNSPEC_SME_UDOT, UNSPEC_SME_UVDOT): Likewise.
- (UNSPEC_SME_UMLA, UNSPEC_SME_UMLS, UNSPEC_SME_USDOT): Likewise.
- (UNSPEC_SME_USVDOT, UNSPEC_SME_WRITE): Likewise.
- (Vetype, VNARROW, V2XWIDE, Ventype, V_INT_EQUIV, v_int_equiv)
- (VSINGLE, vsingle, b): Add tuple modes.
- (v2xwide, za32_offset_range, za64_offset_range, za32_long)
- (za32_last_offset, vg_modifier, z_suffix, aligned_operand)
- (aligned_fpr): New mode attributes.
- (SVE_INT_BINARY_MULTI, SVE_INT_BINARY_SINGLE, SVE_INT_BINARY_MULTI)
- (SVE_FP_BINARY_MULTI): New int iterators.
- (SVE_BFLOAT_TERNARY_LONG): Add UNSPEC_BFMLSLB and UNSPEC_BFMLSLT.
- (SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
- (SVE_WHILE_ORDER, SVE2_INT_SHIFT_IMM_NARROWxN, SVE_QCVTxN)
- (SVE2_SFx24_UNARY, SVE2_x24_PERMUTE, SVE2_x24_PERMUTEQ)
- (UNSPEC_REVD_ONLY, SME2_INT_MOP, SME2_BMOP, SME_BINARY_SLICE_SDI)
- (SME_BINARY_SLICE_SDF, SME_BINARY_WRITE_SLICE_SDI, SME_INT_DOTPROD)
- (SME_INT_DOTPROD_LANE, SME_FP_DOTPROD, SME_FP_DOTPROD_LANE)
- (SME_INT_TERNARY_SLICE, SME_FP_TERNARY_SLICE, BHSD_BITS)
- (LUTI_BITS): New int iterators.
- (optab, sve_int_op): Handle the new unspecs.
- (sme_int_op, has_16bit_form): New int attributes.
- (bits_etype): Handle 64.
- * config/aarch64/aarch64.md (UNSPEC_LD1_SVE_COUNT): New unspec.
- (UNSPEC_ST1_SVE_COUNT, UNSPEC_LDNT1_SVE_COUNT): Likewise.
- (UNSPEC_STNT1_SVE_COUNT): Likewise.
- * config/aarch64/atomics.md (cas_short_expected_imm): Use Uhi
- rather than Uph for HImode immediates.
- * config/aarch64/aarch64-sve.md (@aarch64_ld1<SVE_FULLx24:mode>)
- (@aarch64_ldnt1<SVE_FULLx24:mode>, @aarch64_st1<SVE_FULLx24:mode>)
- (@aarch64_stnt1<SVE_FULLx24:mode>): New patterns.
- (@aarch64_<sur>dot_prod_lane<vsi2qi>): Extend to...
- (@aarch64_<sur>dot_prod_lane<SVE_FULL_SDI:mode><SVE_FULL_BHI:mode>)
- (@aarch64_<sur>dot_prod_lane<VNx4SI_ONLY:mode><VNx16QI_ONLY:mode>):
- ...these new patterns.
- (SVE_WHILE_B, SVE_WHILE_B_X2, SVE_WHILE_C): New constants. Add
- SVE_WHILE_B to existing while patterns.
- * config/aarch64/aarch64-sve2.md (@aarch64_sve_ptrue_c<BHSD_BITS>)
- (@aarch64_sve_pext<BHSD_BITS>, @aarch64_sve_pext<BHSD_BITS>x2)
- (@aarch64_sve_psel<BHSD_BITS>, *aarch64_sve_psel<BHSD_BITS>_plus)
- (@aarch64_sve_cntp_c<BHSD_BITS>, <frint_pattern><mode>2)
- (<optab><mode>3, *<optab><mode>3, @aarch64_sve_single_<optab><mode>)
- (@aarch64_sve_<sve_int_op><mode>): New patterns.
- (@aarch64_sve_single_<sve_int_op><mode>, @aarch64_sve_<su>clamp<mode>)
- (*aarch64_sve_<su>clamp<mode>_x, @aarch64_sve_<su>clamp_single<mode>)
- (@aarch64_sve_fclamp<mode>, *aarch64_sve_fclamp<mode>_x)
- (@aarch64_sve_fclamp_single<mode>, <optab><mode><v2xwide>2)
- (@aarch64_sve_<sur>dotvnx4sivnx8hi): New patterns.
- (@aarch64_sve_<maxmin_uns_op><mode>): Likewise.
- (*aarch64_sve_<maxmin_uns_op><mode>): Likewise.
- (@aarch64_sve_single_<maxmin_uns_op><mode>): Likewise.
- (aarch64_sve_fdotvnx4sfvnx8hf): Likewise.
- (aarch64_fdot_prod_lanevnx4sfvnx8hf): Likewise.
- (@aarch64_sve_<optab><VNx16QI_ONLY:mode><VNx16SI_ONLY:mode>): Likewise.
- (@aarch64_sve_<optab><VNx8HI_ONLY:mode><VNx8SI_ONLY:mode>): Likewise.
- (@aarch64_sve_<optab><VNx8HI_ONLY:mode><VNx8DI_ONLY:mode>): Likewise.
- (truncvnx8sf<mode>2, @aarch64_sve_cvtn<mode>): Likewise.
- (<optab><v_int_equiv><mode>2, <optab><mode><v_int_equiv>2): Likewise.
- (@aarch64_sve_sel<mode>): Likewise.
- (@aarch64_sve_while<while_optab_cmp>_b<BHSD_BITS>_x2): Likewise.
- (@aarch64_sve_while<while_optab_cmp>_c<BHSD_BITS>): Likewise.
- (@aarch64_pred_<optab><mode>, @cond_<optab><mode>): Likewise.
- (@aarch64_sve_<optab><mode>): Likewise.
- * config/aarch64/aarch64-sme.md (@aarch64_sme_<optab><mode><mode>)
- (*aarch64_sme_<optab><mode><mode>_plus, @aarch64_sme_read<mode>)
- (*aarch64_sme_read<mode>_plus, @aarch64_sme_write<mode>): New patterns.
- (*aarch64_sme_write<mode>_plus aarch64_sme_zero_zt0): Likewise.
- (@aarch64_sme_<optab><mode>, *aarch64_sme_<optab><mode>_plus)
- (@aarch64_sme_single_<optab><mode>): Likewise.
- (*aarch64_sme_single_<optab><mode>_plus): Likewise.
- (@aarch64_sme_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>)
- (*aarch64_sme_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>_plus)
- (@aarch64_sme_single_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>)
- (*aarch64_sme_single_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>_plus)
- (@aarch64_sme_single_sudot<VNx4SI_ONLY:mode><SME_ZA_BIx24:mode>)
- (*aarch64_sme_single_sudot<VNx4SI_ONLY:mode><SME_ZA_BIx24:mode>_plus)
- (@aarch64_sme_lane_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>)
- (*aarch64_sme_lane_<optab><SME_ZA_SDI:mode><SME_ZA_BHIx24:mode>_plus)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_BHI:mode>)
- (*aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_BHI:mode>_plus)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx24:mode>)
- (*aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx24:mode>_plus)
- (@aarch64_sme_single_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx24:mode>)
- (*aarch64_sme_single_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx24:mode>_plus)
- (@aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx124:mode>)
- (*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_BHIx124:mode>)
- (@aarch64_sme_<optab><VNx2DI_ONLY:mode><VNx8HI_ONLY:mode>)
- (*aarch64_sme_<optab><VNx2DI_ONLY:mode><VNx8HI_ONLY:mode>_plus)
- (@aarch64_sme_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx24:mode>)
- (*aarch64_sme_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx24:mode>_plus)
- (@aarch64_sme_single_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx24:mode>)
- (*aarch64_sme_single_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx24:mode>_plus)
- (@aarch64_sme_lane_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx124:mode>)
- (*aarch64_sme_lane_<optab><VNx2DI_ONLY:mode><SME_ZA_HIx124:mode>)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><VNx8HI_ONLY:mode>)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><VNx4SI_ONLY:mode>)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>)
- (*aarch64_sme_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>_plus)
- (@aarch64_sme_single_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>)
- (*aarch64_sme_single_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>_plus)
- (@aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>)
- (*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx24:mode>_plus)
- (@aarch64_sme_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>)
- (*aarch64_sme_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>_plus)
- (@aarch64_sme_single_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>)
- (*aarch64_sme_single_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>_plus)
- (@aarch64_sme_lane_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>)
- (*aarch64_sme_lane_<optab><SME_ZA_SDF_I:mode><SME_ZA_SDFx24:mode>)
- (@aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>)
- (*aarch64_sme_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>_plus)
- (@aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx124:mode>)
- (*aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SME_ZA_HFx124:mode>)
- (@aarch64_sme_lut<LUTI_BITS><mode>): Likewise.
- (UNSPEC_SME_LUTI): New unspec.
- * config/aarch64/aarch64-sve-builtins.def (single): New mode suffix.
- (c8, c16, c32, c64): New type suffixes.
- (vg1x2, vg1x4, vg2, vg2x1, vg2x2, vg2x4, vg4, vg4x1, vg4x2)
- (vg4x4): New group suffixes.
- * config/aarch64/aarch64-sve-builtins.h (CP_READ_ZT0)
- (CP_WRITE_ZT0): New constants.
- (get_svbool_t): Delete.
- (function_resolver::report_mismatched_num_vectors): New member
- function.
- (function_resolver::resolve_conversion): Likewise.
- (function_resolver::infer_predicate_type): Likewise.
- (function_resolver::infer_64bit_scalar_integer_pair): Likewise.
- (function_resolver::require_matching_predicate_type): Likewise.
- (function_resolver::require_nonscalar_type): Likewise.
- (function_resolver::finish_opt_single_resolution): Likewise.
- (function_resolver::require_derived_vector_type): Add an
- expected_num_vectors parameter.
- (function_expander::map_to_rtx_codes): Add an extra parameter
- for unconditional FP unspecs.
- (function_instance::gp_type_index): New member function.
- (function_instance::gp_type): Likewise.
- (function_instance::gp_mode): Handle multi-vector operations.
- * config/aarch64/aarch64-sve-builtins.cc (TYPES_all_count)
- (TYPES_all_pred_count, TYPES_c, TYPES_bhs_data, TYPES_bhs_widen)
- (TYPES_hs_data, TYPES_cvt_h_s_float, TYPES_cvt_s_s, TYPES_qcvt_x2)
- (TYPES_qcvt_x4, TYPES_qrshr_x2, TYPES_qrshru_x2, TYPES_qrshr_x4)
- (TYPES_qrshru_x4, TYPES_while_x, TYPES_while_x_c, TYPES_s_narrow_fsu)
- (TYPES_za_s_b_signed, TYPES_za_s_b_unsigned, TYPES_za_s_b_integer)
- (TYPES_za_s_h_integer, TYPES_za_s_h_data, TYPES_za_s_unsigned)
- (TYPES_za_s_float, TYPES_za_s_data, TYPES_za_d_h_integer): New type
- macros.
- (groups_x2, groups_x12, groups_x4, groups_x24, groups_x124)
- (groups_vg1x2, groups_vg1x4, groups_vg1x24, groups_vg2, groups_vg4)
- (groups_vg24): New group arrays.
- (function_instance::reads_global_state_p): Handle CP_READ_ZT0.
- (function_instance::modifies_global_state_p): Handle CP_WRITE_ZT0.
- (add_shared_state_attribute): Handle zt0 state.
- (function_builder::add_overloaded_functions): Skip MODE_single
- for non-tuple groups.
- (function_resolver::report_mismatched_num_vectors): New function.
- (function_resolver::resolve_to): Add a fallback error message for
- the general two-type case.
- (function_resolver::resolve_conversion): New function.
- (function_resolver::infer_predicate_type): Likewise.
- (function_resolver::infer_64bit_scalar_integer_pair): Likewise.
- (function_resolver::require_matching_predicate_type): Likewise.
- (function_resolver::require_matching_vector_type): Specifically
- diagnose mismatched vector counts.
- (function_resolver::require_derived_vector_type): Add an
- expected_num_vectors parameter. Extend to handle cases where
- tuples are expected.
- (function_resolver::require_nonscalar_type): New function.
- (function_resolver::check_gp_argument): Use gp_type_index rather
- than hard-coding VECTOR_TYPE_svbool_t.
- (function_resolver::finish_opt_single_resolution): New function.
- (function_checker::require_immediate_either_or): Remove hard-coded
- constants.
- (function_expander::direct_optab_handler): New function.
- (function_expander::use_pred_x_insn): Only add a strictness flag
- is the insn has an operand for it.
- (function_expander::map_to_rtx_codes): Take an unconditional
- FP unspec as an extra parameter. Handle tuples and MODE_single.
- (function_expander::map_to_unspecs): Handle tuples and MODE_single.
- * config/aarch64/aarch64-sve-builtins-functions.h (read_zt0)
- (write_zt0): New typedefs.
- (full_width_access::memory_vector): Use the function's
- vectors_per_tuple.
- (rtx_code_function_base): Add an optional unconditional FP unspec.
- (rtx_code_function::expand): Update accordingly.
- (rtx_code_function_rotated::expand): Likewise.
- (unspec_based_function_exact_insn::expand): Use tuple_mode instead
- of vector_mode.
- (unspec_based_uncond_function): New typedef.
- (cond_or_uncond_unspec_function): New class.
- (sme_1mode_function::expand): Handle single forms.
- (sme_2mode_function_t): Likewise, adding a template parameter for them.
- (sme_2mode_function): Update accordingly.
- (sme_2mode_lane_function): New typedef.
- (multireg_permute): New class.
- (class integer_conversion): Likewise.
- (while_comparison::expand): Handle svcount_t and svboolx2_t results.
- * config/aarch64/aarch64-sve-builtins-shapes.h
- (binary_int_opt_single_n, binary_opt_single_n, binary_single)
- (binary_za_slice_lane, binary_za_slice_int_opt_single)
- (binary_za_slice_opt_single, binary_za_slice_uint_opt_single)
- (binaryx, clamp, compare_scalar_count, count_pred_c)
- (dot_za_slice_int_lane, dot_za_slice_lane, dot_za_slice_uint_lane)
- (extract_pred, inherent_zt, ldr_zt, read_za, read_za_slice)
- (select_pred, shift_right_imm_narrowxn, storexn, str_zt)
- (unary_convertxn, unary_za_slice, unaryxn, write_za)
- (write_za_slice): Declare.
- * config/aarch64/aarch64-sve-builtins-shapes.cc
- (za_group_is_pure_overload): New function.
- (apply_predication): Use the function's gp_type for the predicate,
- instead of hard-coding the use of svbool_t.
- (parse_element_type): Add support for "c" (svcount_t).
- (parse_type): Add support for "c0" and "c1" (conversion destination
- and source types).
- (binary_za_slice_lane_base): New class.
- (binary_za_slice_opt_single_base): Likewise.
- (load_contiguous_base::resolve): Pass the group suffix to r.resolve.
- (luti_lane_zt_base): New class.
- (binary_int_opt_single_n, binary_opt_single_n, binary_single)
- (binary_za_slice_lane, binary_za_slice_int_opt_single)
- (binary_za_slice_opt_single, binary_za_slice_uint_opt_single)
- (binaryx, clamp): New shapes.
- (compare_scalar_def::build): Allow the return type to be a tuple.
- (compare_scalar_def::expand): Pass the group suffix to r.resolve.
- (compare_scalar_count, count_pred_c, dot_za_slice_int_lane)
- (dot_za_slice_lane, dot_za_slice_uint_lane, extract_pred, inherent_zt)
- (ldr_zt, read_za, read_za_slice, select_pred, shift_right_imm_narrowxn)
- (storexn, str_zt): New shapes.
- (ternary_qq_lane_def, ternary_qq_opt_n_def): Replace with...
- (ternary_qq_or_011_lane_def, ternary_qq_opt_n_or_011_def): ...these
- new classes. Allow a second suffix that specifies the type of the
- second vector argument, and that is used to derive the third.
- (unary_def::build): Extend to handle tuple types.
- (unary_convert_def::build): Use the new c0 and c1 format specifiers.
- (unary_convertxn, unary_za_slice, unaryxn, write_za): New shapes.
- (write_za_slice): Likewise.
- * config/aarch64/aarch64-sve-builtins-base.cc (svbic_impl::expand)
- (svext_bhw_impl::expand): Update call to map_to_rtx_costs.
- (svcntp_impl::expand): Handle svcount_t variants.
- (svcvt_impl::expand): Handle unpredicated conversions separately,
- dealing with tuples.
- (svdot_impl::expand): Handle 2-way dot products.
- (svdotprod_lane_impl::expand): Likewise.
- (svld1_impl::fold): Punt on tuple loads.
- (svld1_impl::expand): Handle tuple loads.
- (svldnt1_impl::expand): Likewise.
- (svpfalse_impl::fold): Punt on svcount_t forms.
- (svptrue_impl::fold): Likewise.
- (svptrue_impl::expand): Handle svcount_t forms.
- (svrint_impl): New class.
- (svsel_impl::fold): Punt on tuple forms.
- (svsel_impl::expand): Handle tuple forms.
- (svst1_impl::fold): Punt on tuple loads.
- (svst1_impl::expand): Handle tuple loads.
- (svstnt1_impl::expand): Likewise.
- (svwhilelx_impl::fold): Punt on tuple forms.
- (svdot_lane): Use UNSPEC_FDOT.
- (svmax, svmaxnm, svmin, svminmm): Add unconditional FP unspecs.
- (rinta, rinti, rintm, rintn, rintp, rintx, rintz): Use svrint_impl.
- * config/aarch64/aarch64-sve-builtins-base.def (svcreate2, svget2)
- (svset2, svundef2): Add _b variants.
- (svcvt): Use unary_convertxn.
- (svdot): Use ternary_qq_opt_n_or_011.
- (svdot_lane): Use ternary_qq_or_011_lane.
- (svmax, svmaxnm, svmin, svminnm): Use binary_opt_single_n.
- (svpfalse): Add a form that returns svcount_t results.
- (svrinta, svrintm, svrintn, svrintp): Use unaryxn.
- (svsel): Use binaryxn.
- (svst1, svstnt1): Use storexn.
- * config/aarch64/aarch64-sve-builtins-sme.h
- (svadd_za, svadd_write_za, svbmopa_za, svbmops_za, svdot_za)
- (svdot_lane_za, svldr_zt, svluti2_lane_zt, svluti4_lane_zt)
- (svmla_za, svmla_lane_za, svmls_za, svmls_lane_za, svread_za)
- (svstr_zt, svsub_za, svsub_write_za, svsudot_za, svsudot_lane_za)
- (svsuvdot_lane_za, svusdot_za, svusdot_lane_za, svusvdot_lane_za)
- (svvdot_lane_za, svwrite_za, svzero_zt): Declare.
- * config/aarch64/aarch64-sve-builtins-sme.cc (load_store_za_base):
- Rename to...
- (load_store_za_zt0_base): ...this and extend to tuples.
- (load_za_base, store_za_base): Update accordingly.
- (expand_ldr_str_zt0): New function.
- (svldr_zt_impl, svluti_lane_zt_impl, svread_za_impl, svstr_zt_impl)
- (svsudot_za_impl, svwrite_za_impl, svzero_zt_impl): New classes.
- (svadd_za, svadd_write_za, svbmopa_za, svbmops_za, svdot_za)
- (svdot_lane_za, svldr_zt, svluti2_lane_zt, svluti4_lane_zt)
- (svmla_za, svmla_lane_za, svmls_za, svmls_lane_za, svread_za)
- (svstr_zt, svsub_za, svsub_write_za, svsudot_za, svsudot_lane_za)
- (svsuvdot_lane_za, svusdot_za, svusdot_lane_za, svusvdot_lane_za)
- (svvdot_lane_za, svwrite_za, svzero_zt): New functions.
- * config/aarch64/aarch64-sve-builtins-sme.def: Add SME2 intrinsics.
- * config/aarch64/aarch64-sve-builtins-sve2.h
- (svbfmlslb, svbfmlslb_lane, svbfmlslt, svbfmlslt_lane, svclamp)
- (svcvtn, svpext, svpsel, svqcvt, svqcvtn, svqrshr, svqrshrn)
- (svqrshru, svqrshrun, svrevd, svunpk, svuzp, svuzpq, svzip)
- (svzipq): Declare.
- * config/aarch64/aarch64-sve-builtins-sve2.cc (svclamp_impl)
- (svcvtn_impl, svpext_impl, svpsel_impl): New classes.
- (svqrshl_impl::fold): Update for change to svrshl shape.
- (svrshl_impl::fold): Punt on tuple forms.
- (svsqadd_impl::expand): Update call to map_to_rtx_codes.
- (svunpk_impl): New class.
- (svbfmlslb, svbfmlslb_lane, svbfmlslt, svbfmlslt_lane, svclamp)
- (svcvtn, svpext, svpsel, svqcvt, svqcvtn, svqrshr, svqrshrn)
- (svqrshru, svqrshrun, svrevd, svunpk, svuzp, svuzpq, svzip)
- (svzipq): New functions.
- * config/aarch64/aarch64-sve-builtins-sve2.def: Add SME2 intrinsics.
- * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
- or undefine __ARM_FEATURE_SME2.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.md (ZT0_REGNUM): New constant.
- (LAST_FAKE_REGNUM): Bump to include it.
- * config/aarch64/aarch64.h (FIXED_REGISTERS): Add an entry for ZT0.
- (CALL_REALLY_USED_REGISTERS, REGISTER_NAMES): Likewise.
- (REG_CLASS_CONTENTS): Likewise.
- (machine_function): Add zt0_save_buffer.
- (CUMULATIVE_ARGS): Add shared_zt0_flags;
- * config/aarch64/aarch64.cc (aarch64_check_state_string): Handle zt0.
- (aarch64_fntype_pstate_za, aarch64_fndecl_pstate_za): Likewise.
- (aarch64_function_arg): Add the shared ZT0 flags as an extra
- limb of the parallel.
- (aarch64_init_cumulative_args): Initialize shared_zt0_flags.
- (aarch64_extra_live_on_entry): Handle ZT0_REGNUM.
- (aarch64_epilogue_uses): Likewise.
- (aarch64_get_zt0_save_buffer, aarch64_save_zt0): New functions.
- (aarch64_restore_zt0): Likewise.
- (aarch64_start_call_args): Reject calls to functions that share
- ZT0 from functions that have no ZT0 state. Save ZT0 around shared-ZA
- calls that do not share ZT0.
- (aarch64_expand_call): Handle ZT0. Reject calls to functions that
- share ZT0 but not ZA from functions with ZA state.
- (aarch64_end_call_args): Restore ZT0 after calls to shared-ZA functions
- that do not share ZT0.
- (aarch64_set_current_function): Require +sme2 for functions that
- have ZT0 state.
- (aarch64_function_attribute_inlinable_p): Don't allow functions to
- be inlined if they have local zt0 state.
- (AARCH64_IPA_CLOBBERS_ZT0): New constant.
- (aarch64_update_ipa_fn_target_info): Record asms that clobber ZT0.
- (aarch64_can_inline_p): Don't inline callees that clobber ZT0
- into functions that have ZT0 state.
- (aarch64_comp_type_attributes): Check for compatible ZT0 sharing.
- (aarch64_optimize_mode_switching): Use mode switching if the
- function has ZT0 state.
- (aarch64_mode_emit_local_sme_state): Save and restore ZT0 around
- calls to private-ZA functions.
- (aarch64_mode_needed_local_sme_state): Require ZA to be active
- for instructions that access ZT0.
- (aarch64_mode_entry): Mark ZA as dead on entry if the function
- only shares state other than "za" itself.
- (aarch64_mode_exit): Likewise mark ZA as dead on return.
- (aarch64_md_asm_adjust): Extend handling of ZA clobbers to ZT0.
- * config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros):
- Define __ARM_STATE_ZT0.
- * config/aarch64/aarch64-sme.md (UNSPECV_ASM_UPDATE_ZT0): New unspecv.
- (aarch64_asm_update_zt0): New insn.
- (UNSPEC_RESTORE_ZT0): New unspec.
- (aarch64_sme_ldr_zt0, aarch64_restore_zt0): New insns.
- (aarch64_sme_str_zt0): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-modes.def (VNx32BI): New mode.
- * config/aarch64/aarch64-protos.h (aarch64_split_double_move): Declare.
- * config/aarch64/aarch64-sve-builtins.cc
- (register_tuple_type): Handle tuples of predicates.
- (handle_arm_sve_h): Define svboolx2_t as a pair of two svbool_ts.
- * config/aarch64/aarch64-sve.md (movvnx32bi): New insn.
- * config/aarch64/aarch64.cc
- (pure_scalable_type_info::piece::get_rtx): Use VNx32BI for pairs
- of predicates.
- (pure_scalable_type_info::add_piece): Don't try to form pairs of
- predicates.
- (VEC_STRUCT): Generalize comment.
- (aarch64_classify_vector_mode): Handle VNx32BI.
- (aarch64_array_mode): Likewise. Return BLKmode for arrays of
- predicates that have no associated mode, rather than allowing
- an integer mode to be chosen.
- (aarch64_hard_regno_nregs): Handle VNx32BI.
- (aarch64_hard_regno_mode_ok): Likewise.
- (aarch64_split_double_move): New function, split out from...
- (aarch64_split_128bit_move): ...here.
- (aarch64_ptrue_reg): Tighten assert to aarch64_sve_pred_mode_p.
- (aarch64_pfalse_reg): Likewise.
- (aarch64_sve_same_pred_for_ptest_p): Likewise.
- (aarch64_sme_mode_switch_regs::add_reg): Handle VNx32BI.
- (aarch64_expand_mov_immediate): Restrict handling of boolean vector
- constants to single-predicate modes.
- (aarch64_classify_address): Handle VNx32BI, ensuring that both halves
- can be addressed.
- (aarch64_class_max_nregs): Handle VNx32BI.
- (aarch64_member_type_forces_blk): Don't for BLKmode for svboolx2_t.
- (aarch64_simd_valid_immediate): Allow all-zeros and all-ones for
- VNx32BI.
- (aarch64_mov_operand_p): Restrict predicate constant canonicalization
- to single-predicate modes.
- (aarch64_evpc_ext): Generalize exclusion to all predicate modes.
- (aarch64_evpc_rev_local, aarch64_evpc_dup): Likewise.
- * config/aarch64/constraints.md (PR_REGS): New predicate.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins-base.cc
- (svreinterpret_impl::fold): Handle reinterprets between svbool_t
- and svcount_t.
- (svreinterpret_impl::expand): Likewise.
- * config/aarch64/aarch64-sve-builtins-base.def (svreinterpret): Add
- b<->c forms.
- * config/aarch64/aarch64-sve-builtins.cc (TYPES_reinterpret_b): New
- type suffix list.
- (wrap_type_in_struct, register_type_decl): New functions, split out
- from...
- (register_tuple_type): ...here.
- (register_builtin_types): Handle svcount_t.
- (handle_arm_sve_h): Don't create tuples of svcount_t.
- * config/aarch64/aarch64-sve-builtins.def (svcount_t): New type.
- (c): New type suffix.
- * config/aarch64/aarch64-sve-builtins.h (TYPE_count): New type class.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/invoke.texi: Document +sme2.
- * doc/sourcebuild.texi: Document aarch64_sme2.
- * config/aarch64/aarch64-option-extensions.def (AARCH64_OPT_EXTENSION):
- Add sme2.
- * config/aarch64/aarch64.h (AARCH64_ISA_SME2, TARGET_SME2): New macros.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
- Enforce PSTATE.SM and PSTATE.ZA restrictions.
- (aarch64_expand_epilogue): Save and restore the arguments
- to a sibcall around any change to PSTATE.SM.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc: Include symbol-summary.h, ipa-prop.h,
- and ipa-fnsummary.h
- (aarch64_function_attribute_inlinable_p): New function.
- (AARCH64_IPA_SM_FIXED, AARCH64_IPA_CLOBBERS_ZA): New constants.
- (aarch64_need_ipa_fn_target_info): New function.
- (aarch64_update_ipa_fn_target_info): Likewise.
- (aarch64_can_inline_p): Restrict the previous ISA flag checks
- to non-modal features. Prevent callees that require a particular
- PSTATE.SM state from being inlined into callers that can't guarantee
- that state. Also prevent callees that have ZA state from being
- inlined into callers that don't. Finally, prevent callees that
- clobber ZA from being inlined into callers that have ZA state.
- (TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P): Define.
- (TARGET_NEED_IPA_FN_TARGET_INFO): Likewise.
- (TARGET_UPDATE_IPA_FN_TARGET_INFO): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc: Include except.h
- (aarch64_sme_mode_switch_regs::add_call_preserved_reg): New function.
- (aarch64_sme_mode_switch_regs::add_call_preserved_regs): Likewise.
- (aarch64_need_old_pstate_sm): Return true if the function has
- a nonlocal-goto or exception receiver.
- (aarch64_switch_pstate_sm_for_landing_pad): New function.
- (aarch64_switch_pstate_sm_for_jump): Likewise.
- (pass_switch_pstate_sm::gate): Enable the pass for all
- streaming and streaming-compatible functions.
- (pass_switch_pstate_sm::execute): Handle non-local gotos and their
- receivers. Handle exception handler entry points.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_arm_attribute_table): Add
- arm::locally_streaming.
- (aarch64_fndecl_is_locally_streaming): New function.
- (aarch64_fndecl_sm_state): Handle locally-streaming functions.
- (aarch64_cfun_enables_pstate_sm): New function.
- (aarch64_add_offset): Add an argument that specifies whether
- the streaming vector length should be used instead of the
- prevailing one.
- (aarch64_split_add_offset, aarch64_add_sp, aarch64_sub_sp): Likewise.
- (aarch64_allocate_and_probe_stack_space): Likewise.
- (aarch64_expand_mov_immediate): Update calls accordingly.
- (aarch64_need_old_pstate_sm): Return true for locally-streaming
- streaming-compatible functions.
- (aarch64_layout_frame): Force all call-preserved Z and P registers
- to be saved and restored if the function switches PSTATE.SM in the
- prologue.
- (aarch64_get_separate_components): Disable shrink-wrapping of
- such Z and P saves and restores.
- (aarch64_use_late_prologue_epilogue): New function.
- (aarch64_expand_prologue): Measure SVE lengths in the streaming
- vector length for locally-streaming functions, then emit code
- to enable streaming mode.
- (aarch64_expand_epilogue): Likewise in reverse.
- (TARGET_USE_LATE_PROLOGUE_EPILOGUE): Define.
- * config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros):
- Define __arm_locally_streaming.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/invoke.texi: Document +sme-i16i64 and +sme-f64f64.
- * config.gcc (aarch64*-*-*): Add arm_sme.h to the list of headers
- to install and aarch64-sve-builtins-sme.o to the list of objects
- to build.
- * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
- or undefine TARGET_SME, TARGET_SME_I16I64 and TARGET_SME_F64F64.
- (aarch64_pragma_aarch64): Handle arm_sme.h.
- * config/aarch64/aarch64-option-extensions.def (sme-i16i64)
- (sme-f64f64): New extensions.
- * config/aarch64/aarch64-protos.h (aarch64_sme_vq_immediate)
- (aarch64_addsvl_addspl_immediate_p, aarch64_output_addsvl_addspl)
- (aarch64_output_sme_zero_za): Declare.
- (aarch64_output_move_struct): Delete.
- (aarch64_sme_ldr_vnum_offset): Declare.
- (aarch64_sve::handle_arm_sme_h): Likewise.
- * config/aarch64/aarch64.h (AARCH64_ISA_SM_ON): New macro.
- (AARCH64_ISA_SME_I16I64, AARCH64_ISA_SME_F64F64): Likewise.
- (TARGET_STREAMING, TARGET_STREAMING_SME): Likewise.
- (TARGET_SME_I16I64, TARGET_SME_F64F64): Likewise.
- * config/aarch64/aarch64.cc (aarch64_sve_rdvl_factor_p): Rename to...
- (aarch64_sve_rdvl_addvl_factor_p): ...this.
- (aarch64_sve_rdvl_immediate_p): Update accordingly.
- (aarch64_rdsvl_immediate_p, aarch64_add_offset): Likewise.
- (aarch64_sme_vq_immediate): Likewise. Make public.
- (aarch64_sve_addpl_factor_p): New function.
- (aarch64_sve_addvl_addpl_immediate_p): Use
- aarch64_sve_rdvl_addvl_factor_p and aarch64_sve_addpl_factor_p.
- (aarch64_addsvl_addspl_immediate_p): New function.
- (aarch64_output_addsvl_addspl): Likewise.
- (aarch64_cannot_force_const_mem): Return true for RDSVL immediates.
- (aarch64_classify_index): Handle .Q scaling for VNx1TImode.
- (aarch64_classify_address): Likewise for vnum offsets.
- (aarch64_output_sme_zero_za): New function.
- (aarch64_sme_ldr_vnum_offset_p): Likewise.
- * config/aarch64/predicates.md (aarch64_addsvl_addspl_immediate):
- New predicate.
- (aarch64_pluslong_operand): Include it for SME.
- * config/aarch64/constraints.md (Ucj, Uav): New constraints.
- * config/aarch64/iterators.md (VNx1TI_ONLY): New mode iterator.
- (SME_ZA_I, SME_ZA_SDI, SME_ZA_SDF_I, SME_MOP_BHI): Likewise.
- (SME_MOP_HSDF): Likewise.
- (UNSPEC_SME_ADDHA, UNSPEC_SME_ADDVA, UNSPEC_SME_FMOPA)
- (UNSPEC_SME_FMOPS, UNSPEC_SME_LD1_HOR, UNSPEC_SME_LD1_VER)
- (UNSPEC_SME_READ_HOR, UNSPEC_SME_READ_VER, UNSPEC_SME_SMOPA)
- (UNSPEC_SME_SMOPS, UNSPEC_SME_ST1_HOR, UNSPEC_SME_ST1_VER)
- (UNSPEC_SME_SUMOPA, UNSPEC_SME_SUMOPS, UNSPEC_SME_UMOPA)
- (UNSPEC_SME_UMOPS, UNSPEC_SME_USMOPA, UNSPEC_SME_USMOPS)
- (UNSPEC_SME_WRITE_HOR, UNSPEC_SME_WRITE_VER): New unspecs.
- (elem_bits): Handle x2 and x4 structure modes, plus VNx1TI.
- (Vetype, Vesize, VPRED): Handle VNx1TI.
- (b): New mode attribute.
- (SME_LD1, SME_READ, SME_ST1, SME_WRITE, SME_BINARY_SDI, SME_INT_MOP)
- (SME_FP_MOP): New int iterators.
- (optab): Handle SME unspecs.
- (hv): New int attribute.
- * config/aarch64/aarch64.md (*add<mode>3_aarch64): Handle ADDSVL
- and ADDSPL.
- * config/aarch64/aarch64-sme.md (UNSPEC_SME_LDR): New unspec.
- (@aarch64_sme_<optab><mode>, @aarch64_sme_<optab><mode>_plus)
- (aarch64_sme_ldr0, @aarch64_sme_ldrn<mode>): New patterns.
- (UNSPEC_SME_STR): New unspec.
- (@aarch64_sme_<optab><mode>, @aarch64_sme_<optab><mode>_plus)
- (aarch64_sme_str0, @aarch64_sme_strn<mode>): New patterns.
- (@aarch64_sme_<optab><v_int_container><mode>): Likewise.
- (*aarch64_sme_<optab><v_int_container><mode>_plus): Likewise.
- (@aarch64_sme_<optab><VNx1TI_ONLY:mode><SVE_FULL:mode>): Likewise.
- (@aarch64_sme_<optab><v_int_container><mode>): Likewise.
- (*aarch64_sme_<optab><v_int_container><mode>_plus): Likewise.
- (@aarch64_sme_<optab><VNx1TI_ONLY:mode><SVE_FULL:mode>): Likewise.
- (UNSPEC_SME_ZERO): New unspec.
- (aarch64_sme_zero): New pattern.
- (@aarch64_sme_<SME_BINARY_SDI:optab><mode>): Likewise.
- (@aarch64_sme_<SME_INT_MOP:optab><mode>): Likewise.
- (@aarch64_sme_<SME_FP_MOP:optab><mode>): Likewise.
- * config/aarch64/aarch64-sve-builtins.def: Add ZA type suffixes.
- Include aarch64-sve-builtins-sme.def.
- (DEF_SME_ZA_FUNCTION): New macro.
- * config/aarch64/aarch64-sve-builtins.h (CP_READ_ZA): New call
- property.
- (CP_WRITE_ZA): Likewise.
- (PRED_za_m): New predication type.
- (type_suffix_index): Handle DEF_SME_ZA_SUFFIX.
- (type_suffix_info): Add vector_p and za_p fields.
- (function_instance::num_za_tiles): New member function.
- (function_builder::get_attributes): Add an aarch64_feature_flags
- argument.
- (function_expander::get_contiguous_base): Take a base argument
- number, a vnum argument number, and an argument that indicates
- whether the vnum parameter is a factor of the SME vector length
- or the prevailing vector length.
- (function_expander::add_integer_operand): Take a poly_int64.
- (sve_switcher::sve_switcher): Take a base set of flags.
- (sme_switcher): New class.
- (scalar_types): Add a null entry for NUM_VECTOR_TYPES.
- * config/aarch64/aarch64-sve-builtins.cc: Include
- aarch64-sve-builtins-sme.h.
- (pred_suffixes): Add an entry for PRED_za_m.
- (type_suffixes): Initialize vector_p and za_p. Handle ZA suffixes.
- (TYPES_all_za, TYPES_d_za, TYPES_za_bhsd_data, TYPES_za_all_data)
- (TYPES_za_s_integer, TYPES_za_d_integer, TYPES_mop_base)
- (TYPES_mop_base_signed, TYPES_mop_base_unsigned, TYPES_mop_i16i64)
- (TYPES_mop_i16i64_signed, TYPES_mop_i16i64_unsigned, TYPES_za): New
- type suffix macros.
- (preds_m, preds_za_m): New predication lists.
- (function_groups): Handle DEF_SME_ZA_FUNCTION.
- (scalar_types): Add an entry for NUM_VECTOR_TYPES.
- (find_type_suffix_for_scalar_type): Check positively for vectors
- rather than negatively for predicates.
- (check_required_extensions): Handle PSTATE.SM and PSTATE.ZA
- requirements.
- (report_out_of_range): Handle the case where the minimum and
- maximum are the same.
- (function_instance::reads_global_state_p): Return true for functions
- that read ZA.
- (function_instance::modifies_global_state_p): Return true for functions
- that write to ZA.
- (sve_switcher::sve_switcher): Add a base flags argument.
- (function_builder::get_name): Handle "__arm_" prefixes.
- (add_attribute): Add an overload that takes a namespaces.
- (add_shared_state_attribute): New function.
- (function_builder::get_attributes): Take the required feature flags
- as argument. Add streaming and ZA attributes where appropriate.
- (function_builder::add_unique_function): Update calls accordingly.
- (function_resolver::check_gp_argument): Assert that the predication
- isn't ZA _m predication.
- (function_checker::function_checker): Don't bias the argument
- number for ZA _m predication.
- (function_expander::get_contiguous_base): Add arguments that
- specify the base argument number, the vnum argument number,
- and an argument that indicates whether the vnum parameter is
- a factor of the SME vector length or the prevailing vector length.
- Handle the SME case.
- (function_expander::add_input_operand): Handle pmode_register_operand.
- (function_expander::add_integer_operand): Take a poly_int64.
- (init_builtins): Call handle_arm_sme_h for LTO.
- (handle_arm_sve_h): Skip SME intrinsics.
- (handle_arm_sme_h): New function.
- * config/aarch64/aarch64-sve-builtins-functions.h
- (read_write_za, write_za): New classes.
- (unspec_based_sme_function, za_arith_function): New using aliases.
- (quiet_za_arith_function): Likewise.
- * config/aarch64/aarch64-sve-builtins-shapes.h
- (binary_za_int_m, binary_za_m, binary_za_uint_m, bool_inherent)
- (inherent_za, inherent_mask_za, ldr_za, load_za, read_za_m, store_za)
- (str_za, unary_za_m, write_za_m): Declare.
- * config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
- Expect za_m functions to have an existing governing predicate.
- (binary_za_m_base, binary_za_int_m_def, binary_za_m_def): New classes.
- (binary_za_uint_m_def, bool_inherent_def, inherent_za_def): Likewise.
- (inherent_mask_za_def, ldr_za_def, load_za_def, read_za_m_def)
- (store_za_def, str_za_def, unary_za_m_def, write_za_m_def): Likewise.
- * config/aarch64/arm_sme.h: New file.
- * config/aarch64/aarch64-sve-builtins-sme.h: Likewise.
- * config/aarch64/aarch64-sve-builtins-sme.cc: Likewise.
- * config/aarch64/aarch64-sve-builtins-sme.def: Likewise.
- * config/aarch64/t-aarch64 (aarch64-sve-builtins.o): Depend on
- aarch64-sve-builtins-sme.def and aarch64-sve-builtins-sme.h.
- (aarch64-sve-builtins-sme.o): New rule.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h
- (function_shape::has_merge_argument_p): New member function.
- * config/aarch64/aarch64-sve-builtins.cc:
- (function_resolver::check_gp_argument): Use it.
- (function_expander::get_fallback_value): Likewise.
- * config/aarch64/aarch64-sve-builtins-shapes.cc
- (apply_predication): Likewise.
- (unary_convert_narrowt_def::has_merge_argument_p): New function.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins-functions.h
- (unspec_based_function_base): Allow type suffix 1 to determine
- the mode of the operation.
- (unspec_based_function): Update accordingly.
- (unspec_based_fused_function): Likewise.
- (unspec_based_fused_lane_function): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-modes.def: Add VNx1TI.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (W12_W15_REGNUM_P): New macro.
- (W12_W15_REGS): New register class.
- (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add entries for it.
- * config/aarch64/aarch64.cc (aarch64_regno_regclass)
- (aarch64_class_max_nregs, aarch64_register_move_cost): Handle
- W12_W15_REGS.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-isa-modes.def (ZA_ON): New ISA mode.
- * config/aarch64/aarch64-protos.h (aarch64_rdsvl_immediate_p)
- (aarch64_output_rdsvl, aarch64_optimize_mode_switching)
- (aarch64_restore_za): Declare.
- * config/aarch64/constraints.md (UsR): New constraint.
- * config/aarch64/aarch64.md (LOWERING_REGNUM, TPIDR_BLOCK_REGNUM)
- (SME_STATE_REGNUM, TPIDR2_SETUP_REGNUM, ZA_FREE_REGNUM)
- (ZA_SAVED_REGNUM, ZA_REGNUM, FIRST_FAKE_REGNUM): New constants.
- (LAST_FAKE_REGNUM): Likewise.
- (UNSPEC_SAVE_NZCV, UNSPEC_RESTORE_NZCV, UNSPEC_SME_VQ): New unspecs.
- (arches): Add sme.
- (arch_enabled): Handle it.
- (*cb<optab><mode>1): Rename to...
- (aarch64_cb<optab><mode>1): ...this.
- (*movsi_aarch64): Add an alternative for RDSVL.
- (*movdi_aarch64): Likewise.
- (aarch64_save_nzcv, aarch64_restore_nzcv): New insns.
- * config/aarch64/aarch64-sme.md (UNSPEC_SMSTOP_ZA)
- (UNSPEC_INITIAL_ZERO_ZA, UNSPEC_TPIDR2_SAVE, UNSPEC_TPIDR2_RESTORE)
- (UNSPEC_READ_TPIDR2, UNSPEC_WRITE_TPIDR2, UNSPEC_SETUP_LOCAL_TPIDR2)
- (UNSPEC_RESTORE_ZA, UNSPEC_START_PRIVATE_ZA_CALL): New unspecs.
- (UNSPEC_END_PRIVATE_ZA_CALL, UNSPEC_COMMIT_LAZY_SAVE): Likewise.
- (UNSPECV_ASM_UPDATE_ZA): New unspecv.
- (aarch64_tpidr2_save, aarch64_smstart_za, aarch64_smstop_za)
- (aarch64_initial_zero_za, aarch64_setup_local_tpidr2)
- (aarch64_clear_tpidr2, aarch64_write_tpidr2, aarch64_read_tpidr2)
- (aarch64_tpidr2_restore, aarch64_restore_za, aarch64_asm_update_za)
- (aarch64_start_private_za_call, aarch64_end_private_za_call)
- (aarch64_commit_lazy_save): New patterns.
- * config/aarch64/aarch64.h (AARCH64_ISA_ZA_ON, TARGET_ZA): New macros.
- (FIXED_REGISTERS, REGISTER_NAMES): Add the new fake ZA registers.
- (CALL_USED_REGISTERS): Replace with...
- (CALL_REALLY_USED_REGISTERS): ...this and add the fake ZA registers.
- (FIRST_PSEUDO_REGISTER): Bump to include the fake ZA registers.
- (FAKE_REGS): New register class.
- (REG_CLASS_NAMES): Update accordingly.
- (REG_CLASS_CONTENTS): Likewise.
- (machine_function::tpidr2_block): New member variable.
- (machine_function::tpidr2_block_ptr): Likewise.
- (machine_function::za_save_buffer): Likewise.
- (machine_function::next_asm_update_za_id): Likewise.
- (CUMULATIVE_ARGS::shared_za_flags): Likewise.
- (aarch64_mode_entity, aarch64_local_sme_state): New enums.
- (aarch64_tristate_mode): Likewise.
- (OPTIMIZE_MODE_SWITCHING, NUM_MODES_FOR_MODE_SWITCHING): Define.
- * config/aarch64/aarch64.cc (AARCH64_STATE_SHARED, AARCH64_STATE_IN)
- (AARCH64_STATE_OUT): New constants.
- (aarch64_attribute_shared_state_flags): New function.
- (aarch64_lookup_shared_state_flags, aarch64_fndecl_has_new_state)
- (aarch64_check_state_string, cmp_string_csts): Likewise.
- (aarch64_merge_string_arguments, aarch64_check_arm_new_against_type)
- (handle_arm_new, handle_arm_shared): Likewise.
- (handle_arm_new_za_attribute): New
- (aarch64_arm_attribute_table): Add new, preserves, in, out, and inout.
- (aarch64_hard_regno_nregs): Handle FAKE_REGS.
- (aarch64_hard_regno_mode_ok): Likewise.
- (aarch64_fntype_shared_flags, aarch64_fntype_pstate_za): New functions.
- (aarch64_fntype_isa_mode): Include aarch64_fntype_pstate_za.
- (aarch64_fndecl_has_state, aarch64_fndecl_pstate_za): New functions.
- (aarch64_fndecl_isa_mode): Include aarch64_fndecl_pstate_za.
- (aarch64_cfun_incoming_pstate_za, aarch64_cfun_shared_flags)
- (aarch64_cfun_has_new_state, aarch64_cfun_has_state): New functions.
- (aarch64_sme_vq_immediate, aarch64_sme_vq_unspec_p): Likewise.
- (aarch64_rdsvl_immediate_p, aarch64_output_rdsvl): Likewise.
- (aarch64_expand_mov_immediate): Handle RDSVL immediates.
- (aarch64_function_arg): Add the ZA sharing flags as a third limb
- of the PARALLEL.
- (aarch64_init_cumulative_args): Record the ZA sharing flags.
- (aarch64_extra_live_on_entry): New function. Handle the new
- ZA-related fake registers.
- (aarch64_epilogue_uses): Handle the new ZA-related fake registers.
- (aarch64_cannot_force_const_mem): Handle UNSPEC_SME_VQ constants.
- (aarch64_get_tpidr2_block, aarch64_get_tpidr2_ptr): New functions.
- (aarch64_init_tpidr2_block, aarch64_restore_za): Likewise.
- (aarch64_layout_frame): Check whether the current function creates
- new ZA state. Record that it clobbers LR if so.
- (aarch64_expand_prologue): Handle functions that create new ZA state.
- (aarch64_expand_epilogue): Likewise.
- (aarch64_create_tpidr2_block): New function.
- (aarch64_restore_za): Likewise.
- (aarch64_start_call_args): Disallow calls to shared-ZA functions
- from functions that have no ZA state. Emit a marker instruction
- before calls to private-ZA functions from functions that have
- SME state.
- (aarch64_expand_call): Add return registers for state that is
- managed via attributes. Record the use and clobber information
- for the ZA registers.
- (aarch64_end_call_args): New function.
- (aarch64_regno_regclass): Handle FAKE_REGS.
- (aarch64_class_max_nregs): Likewise.
- (aarch64_override_options_internal): Require TARGET_SME for
- functions that have ZA state.
- (aarch64_conditional_register_usage): Handle FAKE_REGS.
- (aarch64_mov_operand_p): Handle RDSVL immediates.
- (aarch64_comp_type_attributes): Check that the ZA sharing flags
- are equal.
- (aarch64_merge_decl_attributes): New function.
- (aarch64_optimize_mode_switching, aarch64_mode_emit_za_save_buffer)
- (aarch64_mode_emit_local_sme_state, aarch64_mode_emit): Likewise.
- (aarch64_insn_references_sme_state_p): Likewise.
- (aarch64_mode_needed_local_sme_state): Likewise.
- (aarch64_mode_needed_za_save_buffer, aarch64_mode_needed): Likewise.
- (aarch64_mode_after_local_sme_state, aarch64_mode_after): Likewise.
- (aarch64_local_sme_confluence, aarch64_mode_confluence): Likewise.
- (aarch64_one_shot_backprop, aarch64_local_sme_backprop): Likewise.
- (aarch64_mode_backprop, aarch64_mode_entry): Likewise.
- (aarch64_mode_exit, aarch64_mode_eh_handler): Likewise.
- (aarch64_mode_priority, aarch64_md_asm_adjust): Likewise.
- (TARGET_END_CALL_ARGS, TARGET_MERGE_DECL_ATTRIBUTES): Define.
- (TARGET_MODE_EMIT, TARGET_MODE_NEEDED, TARGET_MODE_AFTER): Likewise.
- (TARGET_MODE_CONFLUENCE, TARGET_MODE_BACKPROP): Likewise.
- (TARGET_MODE_ENTRY, TARGET_MODE_EXIT): Likewise.
- (TARGET_MODE_EH_HANDLER, TARGET_MODE_PRIORITY): Likewise.
- (TARGET_EXTRA_LIVE_ON_ENTRY): Likewise.
- (TARGET_MD_ASM_ADJUST): Use aarch64_md_asm_adjust.
- * config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros):
- Define __arm_new, __arm_preserves,__arm_in, __arm_out, and __arm_inout.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-passes.def
- (pass_late_thread_prologue_and_epilogue): New pass.
- * config/aarch64/aarch64-sme.md: New file.
- * config/aarch64/aarch64.md: Include it.
- (*tb<optab><mode>1): Rename to...
- (@aarch64_tb<optab><mode>): ...this.
- (call, call_value, sibcall, sibcall_value): Don't require operand 2
- to be a CONST_INT.
- * config/aarch64/aarch64-protos.h (aarch64_emit_call_insn): Return
- the insn.
- (make_pass_switch_sm_state): Declare.
- * config/aarch64/aarch64.h (TARGET_STREAMING_COMPATIBLE): New macro.
- (CALL_USED_REGISTER): Mark VG as call-preserved.
- (aarch64_frame::old_svcr_offset): New member variable.
- (machine_function::call_switches_sm_state): Likewise.
- (CUMULATIVE_ARGS::num_sme_mode_switch_args): Likewise.
- (CUMULATIVE_ARGS::sme_mode_switch_args): Likewise.
- * config/aarch64/aarch64.cc: Include tree-pass.h and cfgbuild.h.
- (aarch64_cfun_incoming_pstate_sm): New function.
- (aarch64_call_switches_pstate_sm): Likewise.
- (aarch64_reg_save_mode): Return DImode for VG_REGNUM.
- (aarch64_callee_isa_mode): New function.
- (aarch64_insn_callee_isa_mode): Likewise.
- (aarch64_guard_switch_pstate_sm): Likewise.
- (aarch64_switch_pstate_sm): Likewise.
- (aarch64_sme_mode_switch_regs): New class.
- (aarch64_record_sme_mode_switch_args): New function.
- (aarch64_finish_sme_mode_switch_args): Likewise.
- (aarch64_function_arg): Handle the end marker by returning a
- PARALLEL that contains the ABI cookie that we used previously
- alongside the result of aarch64_finish_sme_mode_switch_args.
- (aarch64_init_cumulative_args): Initialize num_sme_mode_switch_args.
- (aarch64_function_arg_advance): If a call would switch SM state,
- record all argument registers that would need to be saved around
- the mode switch.
- (aarch64_need_old_pstate_sm): New function.
- (aarch64_layout_frame): Decide whether the frame needs to store the
- incoming value of PSTATE.SM and allocate a save slot for it if so.
- If a function switches SME state, arrange to save the old value
- of the DWARF VG register. Handle the case where this is the only
- register save slot above the FP.
- (aarch64_save_callee_saves): Handles saves of the DWARF VG register.
- (aarch64_get_separate_components): Prevent such saves from being
- shrink-wrapped.
- (aarch64_old_svcr_mem): New function.
- (aarch64_read_old_svcr): Likewise.
- (aarch64_guard_switch_pstate_sm): Likewise.
- (aarch64_expand_prologue): Handle saves of the DWARF VG register.
- Initialize any SVCR save slot.
- (aarch64_expand_call): Allow the cookie to be PARALLEL that contains
- both the UNSPEC_CALLEE_ABI value and a list of registers that need
- to be preserved across a change to PSTATE.SM. If the call does
- involve such a change to PSTATE.SM, record the registers that
- would be clobbered by this process. Also emit an instruction
- to mark the temporary change in VG. Update call_switches_pstate_sm.
- (aarch64_emit_call_insn): Return the emitted instruction.
- (aarch64_frame_pointer_required): New function.
- (aarch64_conditional_register_usage): Prevent VG_REGNUM from being
- treated as a register operand.
- (aarch64_switch_pstate_sm_for_call): New function.
- (pass_data_switch_pstate_sm): New pass variable.
- (pass_switch_pstate_sm): New pass class.
- (make_pass_switch_pstate_sm): New function.
- (TARGET_FRAME_POINTER_REQUIRED): Define.
- * config/aarch64/t-aarch64 (s-check-sve-md): Add aarch64-sme.md.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (TARGET_NON_STREAMING): New macro.
- (TARGET_SVE2_AES, TARGET_SVE2_BITPERM): Use it.
- (TARGET_SVE2_SHA3, TARGET_SVE2_SM4): Likewise.
- * config/aarch64/aarch64-sve-builtins-base.def: Separate out
- the functions that require PSTATE.SM to be 0 and guard them
- with AARCH64_FL_SM_OFF.
- * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
- * config/aarch64/aarch64-sve-builtins.cc (check_required_extensions):
- Enforce AARCH64_FL_SM_OFF requirements.
- * config/aarch64/aarch64-sve.md (aarch64_wrffr): Require
- TARGET_NON_STREAMING
- (aarch64_rdffr, aarch64_rdffr_z, *aarch64_rdffr_z_ptest): Likewise.
- (*aarch64_rdffr_ptest, *aarch64_rdffr_z_cc, *aarch64_rdffr_cc)
- (@aarch64_ld<fn>f1<mode>): Likewise.
- (@aarch64_ld<fn>f1_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>)
- (gather_load<mode><v_int_container>): Likewise
- (mask_gather_load<mode><v_int_container>): Likewise.
- (mask_gather_load<mode><v_int_container>): Likewise.
- (*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
- (*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
- (*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>)
- (@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked)
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_sxtw): Likewise.
- (*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
- <SVE_2BHSI:mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather<mode>, @aarch64_ldff1_gather<mode>): Likewise.
- (*aarch64_ldff1_gather<mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather<mode>_uxtw): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
- <VNx4_NARROW:mode>): Likewise.
- (@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_sxtw): Likewise.
- (*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
- <VNx2_NARROW:mode>_uxtw): Likewise.
- (@aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx4SI_ONLY:mode>)
- (@aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx2DI_ONLY:mode>)
- (*aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx2DI_ONLY:mode>_sxtw)
- (*aarch64_sve_gather_prefetch<SVE_FULL_I:mode><VNx2DI_ONLY:mode>_uxtw)
- (scatter_store<mode><v_int_container>): Likewise.
- (mask_scatter_store<mode><v_int_container>): Likewise.
- (*mask_scatter_store<mode><v_int_container>_<su>xtw_unpacked)
- (*mask_scatter_store<mode><v_int_container>_sxtw): Likewise.
- (*mask_scatter_store<mode><v_int_container>_uxtw): Likewise.
- (@aarch64_scatter_store_trunc<VNx4_NARROW:mode><VNx4_WIDE:mode>)
- (@aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>)
- (*aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>_sxtw)
- (*aarch64_scatter_store_trunc<VNx2_NARROW:mode><VNx2_WIDE:mode>_uxtw)
- (@aarch64_sve_ld1ro<mode>, @aarch64_adr<mode>): Likewise.
- (*aarch64_adr_sxtw, *aarch64_adr_uxtw_unspec): Likewise.
- (*aarch64_adr_uxtw_and, @aarch64_adr<mode>_shift): Likewise.
- (*aarch64_adr<mode>_shift, *aarch64_adr_shift_sxtw): Likewise.
- (*aarch64_adr_shift_uxtw, @aarch64_sve_add_<optab><vsi2qi>): Likewise.
- (@aarch64_sve_<sve_fp_op><mode>, fold_left_plus_<mode>): Likewise.
- (mask_fold_left_plus_<mode>, @aarch64_sve_compact<mode>): Likewise.
- * config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>)
- (@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
- <SVE_PARTIAL_I:mode>): Likewise.
- (@aarch64_sve2_histcnt<mode>, @aarch64_sve2_histseg<mode>): Likewise.
- (@aarch64_pred_<SVE2_MATCH:sve_int_op><mode>): Likewise.
- (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_cc): Likewise.
- (*aarch64_pred_<SVE2_MATCH:sve_int_op><mode>_ptest): Likewise.
- * config/aarch64/iterators.md (SVE_FP_UNARY_INT): Make FEXPA
- depend on TARGET_NON_STREAMING.
- (SVE_BFLOAT_TERNARY_LONG): Likewise BFMMLA.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.h (TARGET_BASE_SIMD): New macro.
- (TARGET_SIMD): Require PSTATE.SM to be 0.
- (AARCH64_ISA_SM_OFF): New macro.
- * config/aarch64/aarch64.cc (aarch64_array_mode_supported_p):
- Allow Advanced SIMD structure modes for TARGET_BASE_SIMD.
- (aarch64_print_operand): Support '%Z'.
- (aarch64_secondary_reload): Expect SVE moves to be used for
- Advanced SIMD modes if SVE is enabled and non-streaming
- Advanced SIMD isn't.
- (aarch64_register_move_cost): Likewise.
- (aarch64_simd_container_mode): Extend Advanced SIMD mode
- handling to TARGET_BASE_SIMD.
- (aarch64_expand_cpymem): Expand commentary.
- * config/aarch64/aarch64.md (arches): Add base_simd and nobase_simd.
- (arch_enabled): Handle it.
- (*mov<mode>_aarch64): Extend UMOV alternative to TARGET_BASE_SIMD.
- (*movti_aarch64): Use an SVE move instruction if non-streaming
- SIMD isn't available.
- (*mov<TFD:mode>_aarch64): Likewise.
- (load_pair_dw_tftf): Extend to TARGET_BASE_SIMD.
- (store_pair_dw_tftf): Likewise.
- (loadwb_pair<TX:mode>_<P:mode>): Likewise.
- (storewb_pair<TX:mode>_<P:mode>): Likewise.
- * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>):
- Allow UMOV in streaming mode.
- (*aarch64_simd_mov<VQMOV:mode>): Use an SVE move instruction
- if non-streaming SIMD isn't available.
- (aarch64_store_lane0<mode>): Depend on TARGET_FLOAT rather than
- TARGET_SIMD.
- (aarch64_simd_mov_from_<mode>low): Likewise. Use fmov if
- Advanced SIMD is completely disabled.
- (aarch64_simd_mov_from_<mode>high): Use SVE EXT instructions if
- non-streaming SIMD isn't available.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/invoke.texi: Document SME.
- * doc/sourcebuild.texi: Document aarch64_sve.
- * config/aarch64/aarch64-option-extensions.def (sme): Define.
- * config/aarch64/aarch64.h (AARCH64_ISA_SME): New macro.
- (TARGET_SME): Likewise.
- * config/aarch64/aarch64.cc (aarch64_override_options_internal):
- Ensure that SME is present when compiling streaming code.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-isa-modes.def: New file.
- * config/aarch64/aarch64.h: Include it in the feature enumerations.
- (AARCH64_FL_SM_STATE, AARCH64_FL_ISA_MODES): New constants.
- (AARCH64_FL_DEFAULT_ISA_MODE): Likewise.
- (AARCH64_ISA_MODE): New macro.
- (CUMULATIVE_ARGS): Add an isa_mode field.
- * config/aarch64/aarch64-protos.h (aarch64_gen_callee_cookie): Declare.
- (aarch64_tlsdesc_abi_id): Return an arm_pcs.
- * config/aarch64/aarch64.cc (attr_streaming_exclusions)
- (aarch64_gnu_attributes, aarch64_gnu_attribute_table)
- (aarch64_arm_attributes, aarch64_arm_attribute_table): New tables.
- (aarch64_attribute_table): Redefine to include the gnu and arm
- attributes.
- (aarch64_fntype_pstate_sm, aarch64_fntype_isa_mode): New functions.
- (aarch64_fndecl_pstate_sm, aarch64_fndecl_isa_mode): Likewise.
- (aarch64_gen_callee_cookie, aarch64_callee_abi): Likewise.
- (aarch64_insn_callee_cookie, aarch64_insn_callee_abi): Use them.
- (aarch64_function_arg, aarch64_output_mi_thunk): Likewise.
- (aarch64_init_cumulative_args): Initialize the isa_mode field.
- (aarch64_output_mi_thunk): Use aarch64_gen_callee_cookie to get
- the ABI cookie.
- (aarch64_override_options): Add the ISA mode to the feature set.
- (aarch64_temporary_target::copy_from_fndecl): Likewise.
- (aarch64_fndecl_options, aarch64_handle_attr_arch): Likewise.
- (aarch64_set_current_function): Maintain the correct ISA mode.
- (aarch64_tlsdesc_abi_id): Return an arm_pcs.
- (aarch64_comp_type_attributes): Handle arm::streaming and
- arm::streaming_compatible.
- * config/aarch64/aarch64-c.cc (aarch64_define_unconditional_macros):
- Define __arm_streaming and __arm_streaming_compatible.
- * config/aarch64/aarch64.md (tlsdesc_small_<mode>): Use
- aarch64_gen_callee_cookie to get the ABI cookie.
- * config/aarch64/t-aarch64 (TM_H): Add all feature-related .def files.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins-base.cc
- (svreinterpret_impl::fold): Punt on tuple forms.
- (svreinterpret_impl::expand): Use tuple_mode instead of vector_mode.
- * config/aarch64/aarch64-sve-builtins-base.def (svreinterpret):
- Extend to x1234 groups.
- * config/aarch64/aarch64-sve-builtins-functions.h
- (multi_vector_function::vectors_per_tuple): If the function has
- a group suffix, get the number of vectors from there.
- * config/aarch64/aarch64-sve-builtins-shapes.h (reinterpret): Declare.
- * config/aarch64/aarch64-sve-builtins-shapes.cc (reinterpret_def)
- (reinterpret): New function shape.
- * config/aarch64/aarch64-sve-builtins.cc (function_groups): Handle
- DEF_SVE_FUNCTION_GS.
- * config/aarch64/aarch64-sve-builtins.def (DEF_SVE_FUNCTION_GS): New
- macro.
- (DEF_SVE_FUNCTION): Forward to DEF_SVE_FUNCTION_GS by default.
- * config/aarch64/aarch64-sve-builtins.h
- (function_instance::tuple_mode): New member function.
- (function_base::vectors_per_tuple): Take the function instance
- as argument and get the number from the group suffix.
- (function_instance::vectors_per_tuple): Update accordingly.
- * config/aarch64/iterators.md (SVE_FULLx2, SVE_FULLx3, SVE_FULLx4)
- (SVE_ALL_STRUCT): New mode iterators.
- (SVE_STRUCT): Redefine in terms of SVE_FULL*.
- * config/aarch64/aarch64-sve.md (@aarch64_sve_reinterpret<mode>)
- (*aarch64_sve_reinterpret<mode>): Extend to SVE structure modes.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.cc
- (function_resolver::require_derived_vector_type): Add a specific
- error message for the case in which the caller wants a single
- vector whose element type matches a previous tuyple argument.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h
- (function_resolver::lookup_form): Add an overload that takes
- an sve_type rather than type and group suffixes.
- (function_resolver::resolve_to): Likewise.
- (function_resolver::infer_vector_or_tuple_type): Return an sve_type.
- (function_resolver::infer_tuple_type): Likewise.
- (function_resolver::require_matching_vector_type): Take an sve_type
- rather than a type_suffix_index.
- (function_resolver::require_derived_vector_type): Likewise.
- * config/aarch64/aarch64-sve-builtins.cc (num_vectors_to_group):
- New function.
- (function_resolver::lookup_form): Add an overload that takes
- an sve_type rather than type and group suffixes.
- (function_resolver::resolve_to): Likewise.
- (function_resolver::infer_vector_or_tuple_type): Return an sve_type.
- (function_resolver::infer_tuple_type): Likewise.
- (function_resolver::infer_vector_type): Update accordingly.
- (function_resolver::require_matching_vector_type): Take an sve_type
- rather than a type_suffix_index.
- (function_resolver::require_derived_vector_type): Likewise.
- * config/aarch64/aarch64-sve-builtins-shapes.cc (get_def::resolve)
- (set_def::resolve, store_def::resolve, tbl_tuple_def::resolve): Update
- calls accordingly.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h
- (function_resolver::require_matching_vector_type): Add a parameter
- that specifies the number of the earlier argument that is being
- matched against.
- * config/aarch64/aarch64-sve-builtins.cc
- (function_resolver::require_matching_vector_type): Likewise.
- (require_derived_vector_type): Update calls accordingly.
- (function_resolver::resolve_unary): Likewise.
- (function_resolver::resolve_uniform): Likewise.
- (function_resolver::resolve_uniform_opt_n): Likewise.
- * config/aarch64/aarch64-sve-builtins-shapes.cc
- (binary_long_lane_def::resolve): Likewise.
- (clast_def::resolve, ternary_uint_def::resolve): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h
- (function_resolver::infer_sve_type): New member function.
- (function_resolver::report_incorrect_num_vectors): Likewise.
- * config/aarch64/aarch64-sve-builtins.cc
- (function_resolver::infer_sve_type): New function,.
- (function_resolver::report_incorrect_num_vectors): New function,
- split out from...
- (function_resolver::infer_vector_or_tuple_type): ...here. Use
- infer_sve_type.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h (sve_type): New struct.
- (sve_type::operator==): New function.
- (function_resolver::get_vector_type): Delete.
- (function_resolver::report_no_such_form): Take an sve_type rather
- than a type_suffix_index.
- * config/aarch64/aarch64-sve-builtins.cc (get_vector_type): New
- function.
- (function_resolver::get_vector_type): Delete.
- (function_resolver::report_no_such_form): Take an sve_type rather
- than a type_suffix_index.
- (find_sve_type): New function, split out from...
- (function_resolver::infer_vector_or_tuple_type): ...here.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Take
- a group suffix index parameter.
- (build_32_64, build_all): Update accordingly. Iterate over all
- group suffixes.
- * config/aarch64/aarch64-sve-builtins-sve2.cc (svqrshl_impl::fold)
- (svqshl_impl::fold, svrshl_impl::fold): Update function_instance
- constructors.
- * config/aarch64/aarch64-sve-builtins.cc (group_suffixes): New array.
- (groups_none): New constant.
- (function_groups): Initialize the groups field.
- (function_instance::hash): Hash the group index.
- (function_builder::get_name): Add the group suffix.
- (function_builder::add_overloaded_functions): Iterate over all
- group suffixes.
- (function_resolver::lookup_form): Take a group suffix parameter.
- (function_resolver::resolve_to): Likewise.
- * config/aarch64/aarch64-sve-builtins.def (DEF_SVE_GROUP_SUFFIX): New
- macro.
- (x2, x3, x4): New group suffixes.
- * config/aarch64/aarch64-sve-builtins.h (group_suffix_index): New enum.
- (group_suffix_info): New structure.
- (function_group_info::groups): New member variable.
- (function_instance::group_suffix_id): Likewise.
- (group_suffixes): New array.
- (function_instance::operator==): Compare the group suffixes.
- (function_instance::group_suffix): New function.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.cc (function_groups): Remove
- implied requirement on SVE.
- * config/aarch64/aarch64-sve-builtins-base.def: Explicitly require SVE.
- * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_sve_rdvl_immediate_p)
- (aarch64_output_sve_rdvl): Declare.
- * config/aarch64/aarch64.cc (aarch64_sve_cnt_factor_p): New
- function, split out from...
- (aarch64_sve_cnt_immediate_p): ...here.
- (aarch64_sve_rdvl_factor_p): New function.
- (aarch64_sve_rdvl_immediate_p): Likewise.
- (aarch64_output_sve_rdvl): Likewise.
- (aarch64_offset_temporaries): Rewrite the SVE handling to use RDVL
- for some cases.
- (aarch64_expand_mov_immediate): Handle RDVL immediates.
- (aarch64_mov_operand_p): Likewise.
- * config/aarch64/constraints.md (Usr): New constraint.
- * config/aarch64/aarch64.md (*mov<SHORT:mode>_aarch64): Add an RDVL
- alternative.
- (*movsi_aarch64, *movdi_aarch64): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h:
- (function_checker::require_immediate_lane_index): Add an argument
- for the index of the indexed vector argument.
- * config/aarch64/aarch64-sve-builtins.cc
- (function_checker::require_immediate_lane_index): Likewise.
- * config/aarch64/aarch64-sve-builtins-shapes.cc
- (ternary_bfloat_lane_base::check): Update accordingly.
- (ternary_qq_lane_base::check): Likewise.
- (binary_lane_def::check): Likewise.
- (binary_long_lane_def::check): Likewise.
- (ternary_lane_def::check): Likewise.
- (ternary_lane_rotate_def::check): Likewise.
- (ternary_long_lane_def::check): Likewise.
- (ternary_qq_lane_rotate_def::check): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (md_asm_adjust): Add a uses parameter.
- * doc/tm.texi: Regenerate.
- * cfgexpand.cc (expand_asm_loc): Update call to md_asm_adjust.
- Handle any USEs created by the target.
- (expand_asm_stmt): Likewise.
- * recog.cc (asm_noperands): Handle asms with USEs.
- (decode_asm_operands): Likewise.
- * config/arm/aarch-common-protos.h (arm_md_asm_adjust): Add uses
- parameter.
- * config/arm/aarch-common.cc (arm_md_asm_adjust): Likewise.
- * config/arm/arm.cc (thumb1_md_asm_adjust): Likewise.
- * config/avr/avr.cc (avr_md_asm_adjust): Likewise.
- * config/cris/cris.cc (cris_md_asm_adjust): Likewise.
- * config/i386/i386.cc (ix86_md_asm_adjust): Likewise.
- * config/mn10300/mn10300.cc (mn10300_md_asm_adjust): Likewise.
- * config/nds32/nds32.cc (nds32_md_asm_adjust): Likewise.
- * config/pdp11/pdp11.cc (pdp11_md_asm_adjust): Likewise.
- * config/rs6000/rs6000.cc (rs6000_md_asm_adjust): Likewise.
- * config/s390/s390.cc (s390_md_asm_adjust): Likewise.
- * config/vax/vax.cc (vax_md_asm_adjust): Likewise.
- * config/visium/visium.cc (visium_md_asm_adjust): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/tm.texi.in: Add TARGET_START_CALL_ARGS.
- * doc/tm.texi: Regenerate.
- * target.def (start_call_args): New hook.
- (call_args, end_call_args): Add a parameter for the cumulative
- argument information.
- * hooks.h (hook_void_rtx_tree): Delete.
- * hooks.cc (hook_void_rtx_tree): Likewise.
- * targhooks.h (hook_void_CUMULATIVE_ARGS): Declare.
- (hook_void_CUMULATIVE_ARGS_rtx_tree): Likewise.
- * targhooks.cc (hook_void_CUMULATIVE_ARGS): New function.
- (hook_void_CUMULATIVE_ARGS_rtx_tree): Likewise.
- * calls.cc (expand_call): Call start_call_args before computing
- and storing stack parameters. Pass the cumulative argument
- information to call_args and end_call_args.
- (emit_library_call_value_1): Likewise.
- * config/nvptx/nvptx.cc (nvptx_call_args): Add a cumulative
- argument parameter.
- (nvptx_end_call_args): Likewise.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * doc/tm.texi.in: Add TARGET_EMIT_EPILOGUE_FOR_SIBCALL.
- * doc/tm.texi: Regenerate.
- * target.def (emit_epilogue_for_sibcall): New hook.
- * calls.cc (can_implement_as_sibling_call_p): Use it.
- * function.cc (thread_prologue_and_epilogue_insns): Likewise.
- (reposition_prologue_and_epilogue_notes): Likewise.
- * config/aarch64/aarch64-protos.h (aarch64_expand_epilogue): Take
- an rtx_call_insn * rather than a bool.
- * config/aarch64/aarch64.cc (aarch64_expand_epilogue): Likewise.
- (TARGET_EMIT_EPILOGUE_FOR_SIBCALL): Define.
- * config/aarch64/aarch64.md (epilogue): Update call.
- (sibcall_epilogue): Delete.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (use_late_prologue_epilogue): New hook.
- * doc/tm.texi.in: Add TARGET_USE_LATE_PROLOGUE_EPILOGUE.
- * doc/tm.texi: Regenerate.
- * passes.def (pass_late_thread_prologue_and_epilogue): New pass.
- * tree-pass.h (make_pass_late_thread_prologue_and_epilogue): Declare.
- * function.cc (pass_thread_prologue_and_epilogue::gate): New function.
- (pass_data_late_thread_prologue_and_epilogue): New pass variable.
- (pass_late_thread_prologue_and_epilogue): New pass class.
- (make_pass_late_thread_prologue_and_epilogue): New function.
-
-2023-12-05 Kito Cheng <kito.cheng@sifive.com>
-
- * common/config/riscv/riscv-common.cc
- (riscv_subset_list::check_conflict_ext): Check zcd conflicts
- with zcmt and zcmp.
-
-2023-12-05 Richard Sandiford <richard.sandiford@arm.com>
-
- PR rtl-optimization/112278
- * lra-int.h (lra_update_biggest_mode): New function.
- * lra-coalesce.cc (merge_pseudos): Use it.
- * lra-lives.cc (process_bb_lives): Likewise.
- * lra.cc (new_insn_reg): Likewise.
-
-2023-12-05 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112843
- * gimple-lower-bitint.cc (gimple_lower_bitint): Change lhs of stmt
- to lhs2 before building and inserting lhs = (cast) lhs2; assignment.
- Adjust stmt operands before adjusting lhs.
-
-2023-12-05 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-v.cc (sew64_scalar_helper): Bugfix.
-
-2023-12-05 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112816
- * config/i386/sse.md ((eq (eq (lshiftrt x elt_bits-1) 0) 0)): New
- splitter to turn psrld $31; pcmpeq; pcmpeq into psrad $31.
-
-2023-12-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md: Add blocker.
- * config/riscv/riscv-protos.h (gather_scatter_valid_offset_p): New function.
- * config/riscv/riscv-v.cc (gather_scatter_valid_offset_p): Ditto.
-
-2023-12-05 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112827
- PR tree-optimization/112848
- * tree-scalar-evolution.cc (final_value_replacement_loop):
- Compute the insert location for each insert.
-
-2023-12-05 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
- Count sse_reg/gpr_regs for components not loaded from memory.
- (ix86_vector_costs:ix86_vector_costs): New constructor.
- (ix86_vector_costs::m_num_gpr_needed[3]): New private memeber.
- (ix86_vector_costs::m_num_sse_needed[3]): Ditto.
- (ix86_vector_costs::finish_cost): Estimate overall register
- pressure cost.
- (ix86_vector_costs::ix86_vect_estimate_reg_pressure): New
- function.
-
-2023-12-05 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md (udot_prodv64qi): New expander.
- (udot_prod<mode>): Emulates with VEC_UNPACKU_EXPR +
- DOT_PROD (short, int).
-
-2023-12-05 Marek Polacek <polacek@redhat.com>
-
- PR c++/107687
- PR c++/110997
- * doc/invoke.texi: Document -fno-immediate-escalation.
-
-2023-12-04 Andrew Pinski <quic_apinski@quicinc.com>
-
- * match.pd (zero_one_valued_p): For convert
- make sure type is not a signed 1-bit integer.
-
-2023-12-04 Jeff Law <jlaw@ventanamicro.com>
-
- * config/microblaze/microblaze.md (movhi): Use %i for half-word
- loads to properly select between lhu/lhui.
-
-2023-12-04 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv-string.cc (expand_rawmemchr): Increment
- source address by vl * element_size.
-
-2023-12-04 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum):
- Rename...
- (enum stringop_strategy_enum): ... to this.
- * config/riscv/riscv-string.cc (riscv_expand_block_move): New
- wrapper expander handling the strategies and delegation.
- (riscv_expand_block_move_scalar): Rename function and make
- static.
- (expand_block_move): Remove strategy handling.
- * config/riscv/riscv.md: Call expander wrapper.
- * config/riscv/riscv.opt: Rename.
-
-2023-12-04 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112785
- * function.h (get_new_clique): New inline function handling
- last_clique overflow.
- * cfgrtl.cc (duplicate_insn_chain): Use it.
- * tree-cfg.cc (gimple_duplicate_bb): Likewise.
- * tree-inline.cc (remap_dependence_clique): Likewise.
-
-2023-12-04 Christoph Müllner <christoph.muellner@vrull.eu>
-
- PR target/112650
- * doc/invoke.texi: Document riscv-strcmp-inline-limit.
-
-2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Fix incorrect overlap in v0.
-
-2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Add highest-number overlap support.
-
-2023-12-04 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112818
- * tree-vect-stmts.cc (vectorizable_bswap): Check input and
- output vector types have the same size.
-
-2023-12-04 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112827
- * tree-scalar-evolution.cc (final_value_replacement_loop):
- Do not release SSA name but keep a dead initialization around.
-
-2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Remove earlyclobber from widen reduction.
-
-2023-12-04 Indu Bhagat <indu.bhagat@oracle.com>
-
- PR debug/112656
- * btfout.cc (btf_asm_type): Fixup ctti_name for all
- BTF types of kind BTF_KIND_FUNC_PROTO.
-
-2023-12-04 Indu Bhagat <indu.bhagat@oracle.com>
-
- PR debug/112768
- * btfout.cc (get_btf_type_name): New definition.
- (btf_collect_datasec): Update dtd_name to the original type name
- string.
- (btf_asm_type_ref): Use the new get_btf_type_name function
- instead.
- (btf_asm_type): Likewise.
- (btf_asm_func_type): Likewise.
-
-2023-12-04 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112837
- * config/i386/i386.cc (ix86_elim_entry_set_got): Before checking
- for UNSPEC_SET_GOT check that SET_SRC is UNSPEC. Use SET_SRC and
- SET_DEST macros instead of XEXP, rename vec variable to set.
-
-2023-12-04 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112816
- * config/i386/sse.md (signbit<mode>2): Force operands[1] into a REG.
-
-2023-12-04 Feng Wang <wangfeng@eswincomputing.com>
-
- * common/config/riscv/riscv-common.cc: Add zvkb ISA info.
- * config/riscv/riscv.opt: Add Mask(ZVKB)
-
-2023-12-04 Fei Gao <gaofei@eswincomputing.com>
- Xiao Zeng <zengxiao@eswincomputing.com>
-
- * config/riscv/riscv.md (*mov<GPR:mode><X:mode>cc):move to sfb.md
- * config/riscv/sfb.md: New file.
-
-2023-12-04 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-cores.def: Add sifive-x280.
- * doc/invoke.texi (RISC-V Options): Add sifive-x280
-
-2023-12-04 Kito Cheng <kito.cheng@sifive.com>
-
- * common/config/riscv/riscv-common.cc (riscv_implied_predicator_t): New.
- (riscv_implied_info_t::riscv_implied_info_t): New.
- (riscv_implied_info_t::match): New.
- (riscv_implied_info): New entry for zcf.
- (riscv_subset_list::handle_implied_ext): Use
- riscv_implied_info_t::match.
- (riscv_subset_list::check_implied_ext): Ditto.
- (riscv_subset_list::handle_combine_ext): Ditto.
- (riscv_subset_list::parse): Move zcf implication handling to
- riscv_implied_infos.
-
-2023-12-04 Kito Cheng <kito.cheng@sifive.com>
-
- * common/config/riscv/riscv-common.cc
- (riscv_subset_list::check_conflict_ext): New.
- (riscv_subset_list::parse): Move checking conflict ext. to
- check_conflict_ext.
- * config/riscv/riscv-subset.h:
- Add riscv_subset_list::check_conflict_ext.
-
-2023-12-04 Hu, Lin1 <lin1.hu@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features): Move USER_MSR
- to the correct location.
-
-2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv.md: Rostify the constraints.
-
-2023-12-04 chenxiaolong <chenxiaolong@loongson.cn>
-
- * doc/extend.texi: Add information about the intrinsic function of the vector
- instruction.
-
-2023-12-03 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112807
- * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
- When choosing type0 and type1 types, if prec3 has small/middle bitint
- kind, use maximum of type0 and type1's precision instead of prec3.
-
-2023-12-03 Jeff Law <jlaw@ventanamicro.com>
-
- * config/frv/frv.h (TRANSFER_FROM_TRAMPOLINE): Add prototype for exit.
-
-2023-12-02 Richard Sandiford <richard.sandiford@arm.com>
-
- * attribs.cc (comp_type_attributes): Pass the full TREE_PURPOSE
- to lookup_attribute_spec, rather than just the name.
- (remove_attributes_matching): Likewise.
-
-2023-12-02 Richard Sandiford <richard.sandiford@arm.com>
-
- * attribs.cc (find_same_attribute): New function.
- (decl_attributes, comp_type_attributes): Use it when looking
- up one list's attributes in another list.
-
-2023-12-02 Richard Sandiford <richard.sandiford@arm.com>
-
- * Makefile.in (GTFILES): Add attribs.cc.
- * attribs.cc (gnu_namespace_cache): New variable.
- (get_gnu_namespace): New function.
- (lookup_attribute_spec): Use it instead of get_identifier ("gnu").
- (get_attribute_namespace, attribs_cc_tests): Likewise.
-
-2023-12-02 Richard Sandiford <richard.sandiford@arm.com>
-
- * attribs.h (scoped_attribute_specs): New structure.
- (register_scoped_attributes): Take a reference to a
- scoped_attribute_specs instead of separate namespace and array
- parameters.
- * plugin.h (register_scoped_attributes): Likewise.
- * attribs.cc (register_scoped_attributes): Likewise.
- (attribute_tables): Change into an array of scoped_attribute_specs
- pointers. Reduce to 1 element for frontends and 1 element for targets.
- (empty_attribute_table): Delete.
- (check_attribute_tables): Update for changes to attribute_tables.
- Use a hash_set to identify duplicates.
- (handle_ignored_attributes_option): Update for above changes.
- (init_attributes): Likewise.
- (excl_pair): Delete.
- (test_attribute_exclusions): Update for above changes. Don't
- enforce symmetry for standard attributes in the top-level namespace.
- * langhooks-def.h (LANG_HOOKS_COMMON_ATTRIBUTE_TABLE): Delete.
- (LANG_HOOKS_FORMAT_ATTRIBUTE_TABLE): Likewise.
- (LANG_HOOKS_INITIALIZER): Update accordingly.
- (LANG_HOOKS_ATTRIBUTE_TABLE): Define to an empty constructor.
- * langhooks.h (lang_hooks::common_attribute_table): Delete.
- (lang_hooks::format_attribute_table): Likewise.
- (lang_hooks::attribute_table): Redefine to an array of
- scoped_attribute_specs pointers.
- * target-def.h (TARGET_GNU_ATTRIBUTES): New macro.
- * target.def (attribute_spec): Redefine to return an array of
- scoped_attribute_specs pointers.
- * tree-inline.cc (function_attribute_inlinable_p): Update accordingly.
- * doc/tm.texi: Regenerate.
- * config/aarch64/aarch64.cc (aarch64_attribute_table): Define using
- TARGET_GNU_ATTRIBUTES.
- * config/alpha/alpha.cc (vms_attribute_table): Likewise.
- * config/avr/avr.cc (avr_attribute_table): Likewise.
- * config/bfin/bfin.cc (bfin_attribute_table): Likewise.
- * config/bpf/bpf.cc (bpf_attribute_table): Likewise.
- * config/csky/csky.cc (csky_attribute_table): Likewise.
- * config/epiphany/epiphany.cc (epiphany_attribute_table): Likewise.
- * config/gcn/gcn.cc (gcn_attribute_table): Likewise.
- * config/h8300/h8300.cc (h8300_attribute_table): Likewise.
- * config/loongarch/loongarch.cc (loongarch_attribute_table): Likewise.
- * config/m32c/m32c.cc (m32c_attribute_table): Likewise.
- * config/m32r/m32r.cc (m32r_attribute_table): Likewise.
- * config/m68k/m68k.cc (m68k_attribute_table): Likewise.
- * config/mcore/mcore.cc (mcore_attribute_table): Likewise.
- * config/microblaze/microblaze.cc (microblaze_attribute_table):
- Likewise.
- * config/mips/mips.cc (mips_attribute_table): Likewise.
- * config/msp430/msp430.cc (msp430_attribute_table): Likewise.
- * config/nds32/nds32.cc (nds32_attribute_table): Likewise.
- * config/nvptx/nvptx.cc (nvptx_attribute_table): Likewise.
- * config/riscv/riscv.cc (riscv_attribute_table): Likewise.
- * config/rl78/rl78.cc (rl78_attribute_table): Likewise.
- * config/rx/rx.cc (rx_attribute_table): Likewise.
- * config/s390/s390.cc (s390_attribute_table): Likewise.
- * config/sh/sh.cc (sh_attribute_table): Likewise.
- * config/sparc/sparc.cc (sparc_attribute_table): Likewise.
- * config/stormy16/stormy16.cc (xstormy16_attribute_table): Likewise.
- * config/v850/v850.cc (v850_attribute_table): Likewise.
- * config/visium/visium.cc (visium_attribute_table): Likewise.
- * config/arc/arc.cc (arc_attribute_table): Likewise. Move further
- down file.
- * config/arm/arm.cc (arm_attribute_table): Update for above changes,
- using...
- (arm_gnu_attributes, arm_gnu_attribute_table): ...these new globals.
- * config/i386/i386-options.h (ix86_attribute_table): Delete.
- (ix86_gnu_attribute_table): Declare.
- * config/i386/i386-options.cc (ix86_attribute_table): Replace with...
- (ix86_gnu_attributes, ix86_gnu_attribute_table): ...these two globals.
- * config/i386/i386.cc (ix86_attribute_table): Define as an array of
- scoped_attribute_specs pointers.
- * config/ia64/ia64.cc (ia64_attribute_table): Update for above changes,
- using...
- (ia64_gnu_attributes, ia64_gnu_attribute_table): ...these new globals.
- * config/rs6000/rs6000.cc (rs6000_attribute_table): Update for above
- changes, using...
- (rs6000_gnu_attributes, rs6000_gnu_attribute_table): ...these new
- globals.
-
-2023-12-02 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/riscv/riscv-vsetvl.cc (csetvl_info::parse_insn): Rename
- local variable from demand_flags to dflags, to avoid conflicting
- with (enumeration) type of the same name.
-
-2023-12-02 Li Wei <liwei@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
- Supplementary function prototype.
- (loongarch_is_even_extraction): Adjust.
- (loongarch_try_expand_lsx_vshuf_const): Adjust.
- (loongarch_is_extraction_permutation): Adjust.
- (loongarch_expand_vec_perm_const_2): Adjust.
-
-2023-12-02 Li Wei <liwei@loongson.cn>
-
- * config/loongarch/loongarch.md (v2di): Used to simplify the
- following templates.
- (popcount<mode>2): New.
-
-2023-12-02 Li Wei <liwei@loongson.cn>
-
- * config/loongarch/loongarch.h (CTZ_DEFINED_VALUE_AT_ZERO): Add
- description.
- (CLZ_DEFINED_VALUE_AT_ZERO): Remove duplicate definition.
-
-2023-12-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112801
- * config/riscv/vector.md: Add !TARGET_64BIT.
-
-2023-12-02 Pan Li <pan2.li@intel.com>
-
- PR target/112743
- * config/riscv/riscv.cc (riscv_legitimize_move): Take the
- exist (U *mode) and handle DFmode like DImode when EEW is
- 32bits for ZVE32F.
-
-2023-12-01 Andrew MacLeod <amacleod@redhat.com>
-
- * gimple-range-fold.h (range_compatible_p): Relocate.
- * value-range.h (range_compatible_p): Here.
- * range-op-mixed.h (operand_equal::operand_check_p): Call
- range_compatible_p rather than comparing precision.
- (operand_not_equal::operand_check_p): Ditto.
- (operand_not_lt::operand_check_p): Ditto.
- (operand_not_le::operand_check_p): Ditto.
- (operand_not_gt::operand_check_p): Ditto.
- (operand_not_ge::operand_check_p): Ditto.
- (operand_plus::operand_check_p): Ditto.
- (operand_abs::operand_check_p): Ditto.
- (operand_minus::operand_check_p): Ditto.
- (operand_negate::operand_check_p): Ditto.
- (operand_mult::operand_check_p): Ditto.
- (operand_bitwise_not::operand_check_p): Ditto.
- (operand_bitwise_xor::operand_check_p): Ditto.
- (operand_bitwise_and::operand_check_p): Ditto.
- (operand_bitwise_or::operand_check_p): Ditto.
- (operand_min::operand_check_p): Ditto.
- (operand_max::operand_check_p): Ditto.
- * range-op.cc (operand_lshift::operand_check_p): Ditto.
- (operand_rshift::operand_check_p): Ditto.
- (operand_logical_and::operand_check_p): Ditto.
- (operand_logical_or::operand_check_p): Ditto.
- (operand_logical_not::operand_check_p): Ditto.
-
-2023-12-01 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR target/112445
- * lra.h (lra): Add one more arg.
- * lra-int.h (lra_verbose, lra_dump_insns): New externals.
- (lra_dump_insns_if_possible): Ditto.
- * lra.cc (lra_dump_insns): Dump all insns.
- (lra_dump_insns_if_possible): Dump all insns for lra_verbose >= 7.
- (lra_verbose): New global.
- (lra): Add new arg. Setup lra_verbose from its value.
- * lra-assigns.cc (lra_split_hard_reg_for): Dump insns if rtl
- was changed.
- * lra-remat.cc (lra_remat): Dump insns if rtl was changed.
- * lra-constraints.cc (lra_inheritance): Dump insns.
- (lra_constraints, lra_undo_inheritance): Dump insns if rtl
- was changed.
- (remove_inheritance_pseudos): Use restore reg if it is set up.
- * ira.cc: (lra): Pass internal_flag_ira_verbose.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- * doc/extend.texi (__builtin_addc, __builtin_addcl, __builtin_addcll,
- __builtin_subc, __builtin_subcl, __builtin_subcll,
- __builtin_stdc_bit_width, __builtin_stdc_count_ones,
- __builtin_stdc_count_zeros, __builtin_stdc_first_leading_one,
- __builtin_stdc_first_leading_zero, __builtin_stdc_first_trailing_one,
- __builtin_stdc_first_trailing_zero, __builtin_stdc_has_single_bit,
- __builtin_stdc_leading_ones, __builtin_stdc_leading_zeros,
- __builtin_stdc_trailing_ones, __builtin_stdc_trailing_zeros,
- __builtin_nvptx_brev, __builtin_nvptx_brevll, __builtin_darn,
- __builtin_darn_raw, __builtin_ia32_vec_ext_v2di,
- __builtin_ia32_crc32qi, __builtin_ia32_crc32hi,
- __builtin_ia32_crc32si, __builtin_ia32_crc32di): Put {}s around
- return type with spaces in it.
- (__builtin_rx_mvfachi, __builtin_rx_mvfacmi): Remove superfluous
- whitespace.
-
-2023-12-01 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-core.h (emit_diagnostic_valist): New overload decl.
- * diagnostic-format-sarif.cc (sarif_builder::make_result_object):
- When we have metadata, call its maybe_add_sarif_properties vfunc.
- * diagnostic-metadata.h (class sarif_object): Forward decl.
- (diagnostic_metadata::~diagnostic_metadata): New.
- (diagnostic_metadata::maybe_add_sarif_properties): New vfunc.
- * diagnostic.cc (emit_diagnostic_valist): New overload.
-
-2023-12-01 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/103533
- * doc/extend.texi: Remove stray reference to
- -fanalyzer-checker=taint.
-
-2023-12-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Support highpart overlap for vx/vf.
-
-2023-12-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Support highpart overlap for indexed load.
-
-2023-12-01 Richard Biener <rguenther@suse.de>
-
- * tree-vectorizer.h (vect_get_vec_defs): Re-order arguments.
- * tree-vect-stmts.cc (vect_get_vec_defs): Likewise.
- (vectorizable_condition): Update caller.
- (vectorizable_comparison_1): Likewise.
- (vectorizable_conversion): Specify the vector type to be
- used for invariant/external defs.
- * tree-vect-loop.cc (vect_transform_reduction): Update caller.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112770
- * gimple-lower-bitint.cc (gimple_lower_bitint): When adjusting
- lhs of middle _BitInt setter which ends bb, insert cast on
- the fallthru edge rather than after stmt.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112771
- * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
- Use mp = 1 if it is zero.
-
-2023-12-01 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf.cc (bpf_asm_named_section): New function.
- (TARGET_ASM_NAMED_SECTION): Set to bpf_asm_named_section.
-
-2023-12-01 Di Zhao <dizhao@os.amperecomputing.com>
-
- * config/aarch64/aarch64-tuning-flags.def
- (AARCH64_EXTRA_TUNING_OPTION): New tuning option to avoid
- cross-loop FMA.
- * config/aarch64/aarch64.cc
- (aarch64_override_options_internal): Set
- param_avoid_fma_max_bits according to tuning option.
- * config/aarch64/tuning_models/ampere1.h (ampere1_tunings):
- Modify tunings related with FMA.
- * config/aarch64/tuning_models/ampere1a.h (ampere1a_tunings):
- Likewise.
- * config/aarch64/tuning_models/ampere1b.h (ampere1b_tunings):
- Likewise.
-
-2023-12-01 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h
- (function_expander::result_mode): New member function.
- * config/aarch64/aarch64-sve-builtins-base.cc
- (svld234_impl::expand): Use it.
- * config/aarch64/aarch64-sve-builtins.cc
- (function_expander::get_reg_target): Likewise.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- * gimple-lower-bitint.cc (range_to_prec): Don't return -1 for
- signed types.
- (bitint_large_huge::lower_addsub_overflow): Fix up computation of
- prec2.
- (bitint_large_huge::lower_mul_overflow): Likewise.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- * gimple-lower-bitint.cc (bitint_large_huge::finish_arith_overflow):
- When replacing use_stmt which is gsi_stmt (m_gsi), update m_gsi to
- the new statement.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112750
- * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
- Use NE_EXPR rather than EQ_EXPR for g2 if !single_comparison and
- adjust probabilities.
-
-2023-12-01 Xi Ruoyao <xry111@xry111.site>
-
- * doc/install.texi: Deem srcdir == objdir broken, but objdir
- as a subdirectory of srcdir fine.
-
-2023-12-01 Juergen Christ <jchrist@linux.ibm.com>
-
- PR target/112753
- * config/s390/s390.cc (s390_md_asm_adjust): Return after dealing
- with the outputs, if no further processing of long doubles is
- required.
-
-2023-12-01 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112725
- * config/s390/s390.cc (s390_invalid_arg_for_unprototyped_fn): Return
- NULL for __builtin_classify_type calls with vector arguments.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document
- -Wdeclaration-missing-parameter-type.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document changes.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document that
- -Wreturn-mismatch is a permerror in C99 and later.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- PR c/91093
- PR c/96284
- * doc/invoke.texi (Warning Options): Document changes.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document changes.
-
-2023-12-01 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document changes.
-
-2023-12-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112776
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::pre_global_vsetvl_info): Fix ratio.
-
-2023-11-30 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- PR target/111404
- * config/aarch64/aarch64.cc (aarch64_split_compare_and_swap):
- For 128-bit store the loaded value and loop if needed.
-
-2023-11-30 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- PR target/103100
- * config/aarch64/aarch64.md (cpymemdi): Remove pattern condition.
- (setmemdi): Likewise.
- * config/aarch64/aarch64.cc (aarch64_expand_cpymem): Support
- strict-align. Cleanup condition for using MOPS.
- (aarch64_expand_setmem): Likewise.
-
-2023-11-30 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112767
- * tree-scalar-evolution.cc (final_value_replacement_loop):
- Propagate constants to immediate uses immediately.
-
-2023-11-30 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112766
- * gimple-predicate-analysis.cc (find_var_cmp_const):
- Support continuing the iteration and report every candidate.
- (uninit_analysis::overlap): Iterate over all flag var
- candidates.
-
-2023-11-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Add widening overlap of vf2/vf4.
-
-2023-11-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Remove earlyclobber for wx/wf instructions.
-
-2023-11-30 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112733
- * wide-int.cc (wi::mul_internal): Don't allocate twice as much
- space for u, v and r as needed.
- (divmod_internal_2): Change return type from void to int, for n == 1
- return 1, otherwise before writing b_dividend into b_remainder set
- n to MIN (n, m) and at the end return it.
- (wi::divmod_internal): Don't allocate 4 times as much space for
- b_quotient, b_remainder, b_dividend and b_divisor. Set n to
- result of divmod_internal_2.
- (wide_int_cc_tests): Add test for unsigned widest_int
- wi::multiple_of_p of 1 and -128.
-
-2023-11-30 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md (sdot_prodv64qi): New expander.
- (sseunpackmodelower): New mode attr.
- (sdot_prod<mode>): Emulate sdot_prodv*qi with sodt_prov*hi
- when TARGET_VNNIINT8 is not available.
-
-2023-11-30 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md: (reduc_plus_scal_<mode>): Use
- vec_extract_lo instead of subreg.
- (reduc_<code>_scal_<mode>): Ditto.
- (reduc_<code>_scal_<mode>): Ditto.
- (reduc_<code>_scal_<mode>): Ditto.
- (reduc_<code>_scal_<mode>): Ditto.
-
-2023-11-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112431
- * config/riscv/vector.md: Add widenning overlap.
-
-2023-11-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Fix constraint.
- * config/riscv/riscv.md (no,W21,W42,W84,W41,W81,W82): Rename vconstraint into group_overlap.
- (no,yes): Ditto.
- (none,W21,W42,W84,W43,W86,W87): Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-11-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Support highpart overlap for vext.vf2
-
-2023-11-29 Philipp Tomsich <philipp.tomsich@vrull.eu>
-
- * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add ampere-1b
- * config/aarch64/aarch64-cost-tables.h: Add ampere1b_extra_costs
- * config/aarch64/aarch64-tune.md: Regenerate
- * config/aarch64/aarch64.cc: Include ampere1b tuning model
- * doc/invoke.texi: Document -mcpu=ampere1b
- * config/aarch64/tuning_models/ampere1b.h: New file.
-
-2023-11-29 David Faust <david.faust@oracle.com>
-
- * config/bpf/bpf.h (ASM_COMMENT_START): Change from ';' to '#'.
-
-2023-11-29 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112725
- * config/rs6000/rs6000.cc (invalid_arg_for_unprototyped_fn): Return
- NULL for __builtin_classify_type calls with vector arguments.
-
-2023-11-29 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/111922
- * ipa-cp.cc (ipa_vr_operation_and_type_effects): Check the
- operands are valid before calling fold_range.
-
-2023-11-29 Andrew MacLeod <amacleod@redhat.com>
-
- * range-op-mixed.h (operator_equal::operand_check_p): New.
- (operator_not_equal::operand_check_p): New.
- (operator_lt::operand_check_p): New.
- (operator_le::operand_check_p): New.
- (operator_gt::operand_check_p): New.
- (operator_ge::operand_check_p): New.
- (operator_plus::operand_check_p): New.
- (operator_abs::operand_check_p): New.
- (operator_minus::operand_check_p): New.
- (operator_negate::operand_check_p): New.
- (operator_mult::operand_check_p): New.
- (operator_bitwise_not::operand_check_p): New.
- (operator_bitwise_xor::operand_check_p): New.
- (operator_bitwise_and::operand_check_p): New.
- (operator_bitwise_or::operand_check_p): New.
- (operator_min::operand_check_p): New.
- (operator_max::operand_check_p): New.
- * range-op.cc (range_op_handler::fold_range): Check operand
- parameter types.
- (range_op_handler::op1_range): Ditto.
- (range_op_handler::op2_range): Ditto.
- (range_op_handler::operand_check_p): New.
- (range_operator::operand_check_p): New.
- (operator_lshift::operand_check_p): New.
- (operator_rshift::operand_check_p): New.
- (operator_logical_and::operand_check_p): New.
- (operator_logical_or::operand_check_p): New.
- (operator_logical_not::operand_check_p): New.
- * range-op.h (range_operator::operand_check_p): New.
- (range_op_handler::operand_check_p): New.
-
-2023-11-29 Martin Jambor <mjambor@suse.cz>
-
- PR tree-optimization/112711
- PR tree-optimization/112721
- * tree-sra.cc (build_access_from_call_arg): New parameter
- CAN_BE_RETURNED, disqualify any candidate passed by reference if it is
- true. Adjust leading comment.
- (scan_function): Pass appropriate value to CAN_BE_RETURNED of
- build_access_from_call_arg.
-
-2023-11-29 Thomas Schwinge <thomas@codesourcery.com>
-
- * doc/sourcebuild.texi (Final Actions): Document
- 'only_for_offload_target' wrapper.
-
-2023-11-29 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
-
- PR testsuite/112729
- * doc/sourcebuild.texi (Effective-Target Keywords, Environment
- attributes): Document cfi.
-
-2023-11-29 Richard Biener <rguenther@suse.de>
-
- PR middle-end/110237
- * internal-fn.cc (expand_partial_load_optab_fn): Clear
- MEM_EXPR and MEM_OFFSET.
- (expand_partial_store_optab_fn): Likewise.
-
-2023-11-29 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112733
- * fold-const.cc (multiple_of_p): Pass SIGNED rather than
- UNSIGNED for wi::multiple_of_p on widest_int arguments.
-
-2023-11-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
- kito-cheng <kito.cheng@sifive.com>
- kito-cheng <kito.cheng@gmail.com>
-
- PR target/112431
- * config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): New register filters.
- * config/riscv/riscv.md (no,W21,W42,W84,W41,W81,W82): Ditto.
- (no,yes): Ditto.
- * config/riscv/vector.md: Support highpart register overlap for vwcvt.
-
-2023-11-29 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv.cc (riscv_option_override): Eliminate warning.
-
-2023-11-29 Jakub Jelinek <jakub@redhat.com>
-
- PR bootstrap/111601
- * fold-mem-offsets.cc (get_uses): Ignore DEBUG_INSN uses. Otherwise,
- punt if use is in a different basic block from INSN or appears before
- INSN in the same basic block. Formatting fixes.
- (get_single_def_in_bb): Formatting fixes.
- (fold_offsets_1, pass_fold_mem_offsets::execute): Comment formatting
- fixes.
-
-2023-11-29 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/simd.md (LSX_SCALAR_FRINT): New int iterator.
- (VLSX_FOR_FMODE): New mode attribute.
- (<simd_for_scalar_frint_pattern><mode>2): New expander,
- expanding to vreplvei.{w/d} + frint{rp/rz/rm/rne}.{s.d}.
-
-2023-11-29 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (lrint_allow_inexact): Remove.
- (<lrint_pattern><ANYF:mode><ANYFI:mode>2): Check if <LRINT>
- == UNSPEC_FTINT instead of <lrint_allow_inexact>.
-
-2023-11-29 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/lsx.md (bitimm): Move to ...
- (UNSPEC_LSX_VROTR): Remove.
- (lsx_vrotr_<lsxfmt>): Remove.
- (lsx_vrotri_<lsxfmt>): Remove.
- * config/loongarch/lasx.md (UNSPEC_LASX_XVROTR): Remove.
- (lsx_vrotr_<lsxfmt>): Remove.
- (lsx_vrotri_<lsxfmt>): Remove.
- * config/loongarch/simd.md (bitimm): ... here. Expand it to
- cover LASX modes.
- (vrotr<mode>3): New define_insn.
- (vrotri<mode>3): New define_insn.
- * config/loongarch/loongarch-builtins.cc:
- (CODE_FOR_lsx_vrotr_b): Use standard pattern name.
- (CODE_FOR_lsx_vrotr_h): Likewise.
- (CODE_FOR_lsx_vrotr_w): Likewise.
- (CODE_FOR_lsx_vrotr_d): Likewise.
- (CODE_FOR_lasx_xvrotr_b): Likewise.
- (CODE_FOR_lasx_xvrotr_h): Likewise.
- (CODE_FOR_lasx_xvrotr_w): Likewise.
- (CODE_FOR_lasx_xvrotr_d): Likewise.
- (CODE_FOR_lsx_vrotri_b): Define to standard pattern name.
- (CODE_FOR_lsx_vrotri_h): Likewise.
- (CODE_FOR_lsx_vrotri_w): Likewise.
- (CODE_FOR_lsx_vrotri_d): Likewise.
- (CODE_FOR_lasx_xvrotri_b): Likewise.
- (CODE_FOR_lasx_xvrotri_h): Likewise.
- (CODE_FOR_lasx_xvrotri_w): Likewise.
- (CODE_FOR_lasx_xvrotri_d): Likewise.
-
-2023-11-29 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/simd.md (muh): New code attribute mapping
- any_extend to smul_highpart or umul_highpart.
- (<su>mul<mode>3_highpart): New define_insn.
- * config/loongarch/lsx.md (UNSPEC_LSX_VMUH_S): Remove.
- (UNSPEC_LSX_VMUH_U): Remove.
- (lsx_vmuh_s_<lsxfmt>): Remove.
- (lsx_vmuh_u_<lsxfmt>): Remove.
- * config/loongarch/lasx.md (UNSPEC_LASX_XVMUH_S): Remove.
- (UNSPEC_LASX_XVMUH_U): Remove.
- (lasx_xvmuh_s_<lasxfmt>): Remove.
- (lasx_xvmuh_u_<lasxfmt>): Remove.
- * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vmuh_b):
- Redefine to standard pattern name.
- (CODE_FOR_lsx_vmuh_h): Likewise.
- (CODE_FOR_lsx_vmuh_w): Likewise.
- (CODE_FOR_lsx_vmuh_d): Likewise.
- (CODE_FOR_lsx_vmuh_bu): Likewise.
- (CODE_FOR_lsx_vmuh_hu): Likewise.
- (CODE_FOR_lsx_vmuh_wu): Likewise.
- (CODE_FOR_lsx_vmuh_du): Likewise.
- (CODE_FOR_lasx_xvmuh_b): Likewise.
- (CODE_FOR_lasx_xvmuh_h): Likewise.
- (CODE_FOR_lasx_xvmuh_w): Likewise.
- (CODE_FOR_lasx_xvmuh_d): Likewise.
- (CODE_FOR_lasx_xvmuh_bu): Likewise.
- (CODE_FOR_lasx_xvmuh_hu): Likewise.
- (CODE_FOR_lasx_xvmuh_wu): Likewise.
- (CODE_FOR_lasx_xvmuh_du): Likewise.
-
-2023-11-29 Xi Ruoyao <xry111@xry111.site>
-
- PR target/112578
- * config/loongarch/lsx.md (UNSPEC_LSX_VFTINT_S,
- UNSPEC_LSX_VFTINTRNE, UNSPEC_LSX_VFTINTRP,
- UNSPEC_LSX_VFTINTRM, UNSPEC_LSX_VFRINTRNE_S,
- UNSPEC_LSX_VFRINTRNE_D, UNSPEC_LSX_VFRINTRZ_S,
- UNSPEC_LSX_VFRINTRZ_D, UNSPEC_LSX_VFRINTRP_S,
- UNSPEC_LSX_VFRINTRP_D, UNSPEC_LSX_VFRINTRM_S,
- UNSPEC_LSX_VFRINTRM_D): Remove.
- (ILSX, FLSX): Move into ...
- (VIMODE): Move into ...
- (FRINT_S, FRINT_D): Remove.
- (frint_pattern_s, frint_pattern_d, frint_suffix): Remove.
- (lsx_vfrint_<flsxfmt>, lsx_vftint_s_<ilsxfmt>_<flsxfmt>,
- lsx_vftintrne_w_s, lsx_vftintrne_l_d, lsx_vftintrp_w_s,
- lsx_vftintrp_l_d, lsx_vftintrm_w_s, lsx_vftintrm_l_d,
- lsx_vfrintrne_s, lsx_vfrintrne_d, lsx_vfrintrz_s,
- lsx_vfrintrz_d, lsx_vfrintrp_s, lsx_vfrintrp_d,
- lsx_vfrintrm_s, lsx_vfrintrm_d,
- <FRINT_S:frint_pattern_s>v4sf2,
- <FRINT_D:frint_pattern_d>v2df2, round<mode>2,
- fix_trunc<mode>2): Remove.
- * config/loongarch/lasx.md: Likewise.
- * config/loongarch/simd.md: New file.
- (ILSX, ILASX, FLSX, FLASX, VIMODE): ... here.
- (IVEC, FVEC): New mode iterators.
- (VIMODE): ... here. Extend it to work for all LSX/LASX vector
- modes.
- (x, wu, simd_isa, WVEC, vimode, simdfmt, simdifmt_for_f,
- elebits): New mode attributes.
- (UNSPEC_SIMD_FRINTRP, UNSPEC_SIMD_FRINTRZ, UNSPEC_SIMD_FRINT,
- UNSPEC_SIMD_FRINTRM, UNSPEC_SIMD_FRINTRNE): New unspecs.
- (SIMD_FRINT): New int iterator.
- (simd_frint_rounding, simd_frint_pattern): New int attributes.
- (<simd_isa>_<x>vfrint<simd_frint_rounding>_<simdfmt>): New
- define_insn template for frint instructions.
- (<simd_isa>_<x>vftint<simd_frint_rounding>_<simdifmt_for_f>_<simdfmt>):
- Likewise, but for ftint instructions.
- (<simd_frint_pattern><mode>2): New define_expand with
- flag_fp_int_builtin_inexact checked.
- (l<simd_frint_pattern><mode><vimode>2): Likewise.
- (ftrunc<mode>2): New define_expand. It does not require
- flag_fp_int_builtin_inexact.
- (fix_trunc<mode><vimode>2): New define_insn_and_split. It does
- not require flag_fp_int_builtin_inexact.
- (include): Add lsx.md and lasx.md.
- * config/loongarch/loongarch.md (include): Include simd.md,
- instead of including lsx.md and lasx.md directly.
- * config/loongarch/loongarch-builtins.cc
- (CODE_FOR_lsx_vftint_w_s, CODE_FOR_lsx_vftint_l_d,
- CODE_FOR_lasx_xvftint_w_s, CODE_FOR_lasx_xvftint_l_d):
- Remove.
-
-2023-11-29 Alexandre Oliva <oliva@adacore.com>
-
- * doc/extend.texi (hardbool): New type attribute.
- * doc/invoke.texi (-ftrivial-auto-var-init): Document
- representation vs values.
-
-2023-11-29 Alexandre Oliva <oliva@adacore.com>
-
- * expr.cc (emit_block_move_hints): Take ctz of len. Obey
- -finline-stringops. Use oriented or sized loop.
- (emit_block_move): Take ctz of len, and pass it on.
- (emit_block_move_via_sized_loop): New.
- (emit_block_move_via_oriented_loop): New.
- (emit_block_move_via_loop): Take incr. Move an incr-sized
- block per iteration.
- (emit_block_cmp_via_cmpmem): Take ctz of len. Obey
- -finline-stringops.
- (emit_block_cmp_via_loop): New.
- * expr.h (emit_block_move): Add ctz of len defaulting to zero.
- (emit_block_move_hints): Likewise.
- (emit_block_cmp_hints): Likewise.
- * builtins.cc (expand_builtin_memory_copy_args): Pass ctz of
- len to emit_block_move_hints.
- (try_store_by_multiple_pieces): Support starting with a loop.
- (expand_builtin_memcmp): Pass ctz of len to
- emit_block_cmp_hints.
- (expand_builtin): Allow inline expansion of memset, memcpy,
- memmove and memcmp if requested.
- * common.opt (finline-stringops): New.
- (ilsop_fn): New enum.
- * flag-types.h (enum ilsop_fn): New.
- * doc/invoke.texi (-finline-stringops): Add.
-
-2023-11-29 Pan Li <pan2.li@intel.com>
-
- PR target/112743
- * config/riscv/riscv-string.cc (expand_block_move): Add
- precondition check for exact_div.
-
-2023-11-28 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.md: Make output template whitespace consistent.
-
-2023-11-28 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * varasm.cc (assemble_external_libcall): Refer in assert only ifdef
- ASM_OUTPUT_EXTERNAL.
-
-2023-11-28 Andrew Pinski <quic_apinski@quicinc.com>
-
- PR tree-optimization/112738
- * match.pd (`(nop_convert)-(convert)a`): Reject
- when the outer type is boolean.
-
-2023-11-28 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112732
- * tree.cc (build_opaque_vector_type): Reset TYPE_ALIAS_SET
- of the newly built type.
-
-2023-11-28 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112494
- * config/i386/i386.md (cmpstrnqi_1): Set FLAGS_REG to its previous
- value when operand 2 equals zero.
- (*cmpstrnqi_1): Ditto.
- (*cmpstrnqi_1 peephole2): Ditto.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- Revert:
- 2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/bpf.cc (bpf_output_call): Report error in case the
- function call is for a builtin.
- (bpf_external_libcall): Added target hook to detect and report
- error when other external calls that are not builtins.
-
-2023-11-28 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- PR target/109253
- * varasm.cc (pending_libcall_symbols): New variable.
- (process_pending_assemble_externals): Process
- pending_libcall_symbols.
- (assemble_external_libcall): Defer emitting external libcall
- symbols to process_pending_assemble_externals.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * btfout.cc (btf_calc_num_vbytes): Fixed logic for enum64.
- (btf_asm_enum_const): Corrected logic for enum64 and smaller
- than 4 bytes values.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/bpf.cc (bpf_output_call): Report error in case the
- function call is for a builtin.
- (bpf_external_libcall): Added target hook to detect and report
- error when other external calls that are not builtins.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/bpf.cc (bpf_use_by_pieces_infrastructure_p): Added
- function to bypass default behaviour.
- * config/bpf/bpf.h (COMPARE_MAX_PIECES): Defined to 1024 bytes.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/core-builtins.cc (core_mark_as_access_index):
- Corrected check.
-
-2023-11-28 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/core-builtins.cc
- (bpf_resolve_overloaded_core_builtin): Removed call.
- (execute_lower_bpf_core): Added all to remove_parser_plugin.
-
-2023-11-28 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112694
- * config/riscv/riscv-v.cc (expand_vec_perm_const): Disallow poly size (1, 1) VLA SLP.
-
-2023-11-28 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112719
- * match.pd (parity(X)^parity(Y) -> parity(X^Y)): Handle case of
- mismatched types.
- * gimple-match-exports.cc (build_call_internal): Add special-case for
- bit query ifns on large/huge BITINT_TYPE before bitint lowering.
-
-2023-11-28 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112719
- * match.pd (popcount (X) + popcount (Y) -> POPCOUNT (X | Y)): Deal
- with argument types with different precisions.
-
-2023-11-28 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/109077
- * Makefile.in (PLUGIN_HEADERS): Add analyzer headers.
- (install-plugin): Keep the directory structure for files in
- "analyzer".
-
-2023-11-28 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112713
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix regression.
-
-2023-11-28 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-show-locus.cc (layout::maybe_add_location_range):
- Don't print annotation lines for ranges when there's no column
- info.
- (selftest::test_one_liner_no_column): New.
- (selftest::test_diagnostic_show_locus_one_liner): Call it.
-
-2023-11-28 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_get_location_text): Convert to...
- (diagnostic_context::get_location_text): ...this, and convert
- return type from char * to label_text.
- (diagnostic_build_prefix): Update for above change.
- (default_diagnostic_start_span_fn): Likewise.
- (selftest::assert_location_text): Likewise.
- * diagnostic.h (diagnostic_context::get_location_text): New decl.
-
-2023-11-27 Andrew Pinski <quic_apinski@quicinc.com>
-
- * config/aarch64/aarch64.cc (aarch64_if_then_else_costs):
- Handle csinv/csinc case of 1/-1.
-
-2023-11-27 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
- Richard Sandiford <richard.sandiford@arm.com>
-
- PR middle-end/111754
- * fold-const.cc (fold_vec_perm_cst): Set result's encoding to sel's
- encoding, and set res_nelts_per_pattern to 2 if sel contains stepped
- sequence but input vectors do not.
- (test_nunits_min_2): New test Case 8.
- (test_nunits_min_4): New tests Case 8 and Case 9.
-
-2023-11-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_needs_frame_chain): Do not
- force frame chain for eh_return.
-
-2023-11-27 Szabolcs Nagy <szabolcs.nagy@arm.com>
-
- * config/aarch64/aarch64-protos.h (aarch64_eh_return_handler_rtx):
- Remove.
- * config/aarch64/aarch64.cc (aarch64_return_address_signing_enabled):
- Sign return address even in functions with eh_return.
- (aarch64_expand_epilogue): Conditionally return with br or ret.
- (aarch64_eh_return_handler_rtx): Remove.
- * config/aarch64/aarch64.h (EH_RETURN_TAKEN_RTX): Define.
- (EH_RETURN_STACKADJ_RTX): Change to R5.
- (EH_RETURN_HANDLER_RTX): Change to R6.
- * df-scan.cc: Handle EH_RETURN_TAKEN_RTX.
- * doc/tm.texi: Regenerate.
- * doc/tm.texi.in: Document EH_RETURN_TAKEN_RTX.
- * except.cc (expand_eh_return): Handle EH_RETURN_TAKEN_RTX.
-
-2023-11-27 Thomas Schwinge <thomas@codesourcery.com>
-
- * config.gcc <amdgcn-*-amdhsa> (extra_gcc_objs): Don't set.
- * config/gcn/driver-gcn.cc: Remove.
- * config/gcn/gcn-hsa.h (ASM_SPEC, EXTRA_SPEC_FUNCTIONS): Remove
- 'last_arg' spec function.
- * config/gcn/t-gcn-hsa (driver-gcn.o): Remove.
-
-2023-11-27 Thomas Schwinge <thomas@codesourcery.com>
-
- PR target/112669
- * config/gcn/gcn.opt (march=, mtune=): Tag as 'Negative' of
- themselves.
-
-2023-11-27 Samuel Thibault <samuel.thibault@gnu.org>
-
- * config/i386/gnu.h: Use PIE_SPEC, add static-pie case.
- * config/i386/gnu64.h: Use PIE_SPEC, add static-pie case.
-
-2023-11-27 Samuel Thibault <samuel.thibault@gnu.org>
-
- * config/i386/t-gnu64: New file.
- * config.gcc [x86_64-*-gnu*]: Add i386/t-gnu64 to
- tmake_file.
-
-2023-11-27 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/106326
- * config/aarch64/aarch64-sve-builtins.h (is_ptrue): Declare.
- * config/aarch64/aarch64-sve-builtins.cc (is_ptrue): New function.
- (gimple_folder::redirect_pred_x): Likewise.
- (gimple_folder::fold): Use it.
-
-2023-11-27 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64-sve-builtins.h (vector_cst_all_same): Declare.
- * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same): New
- function, a generalized replacement of...
- * config/aarch64/aarch64-sve-builtins-base.cc
- (svlast_impl::vect_all_same): ...this.
- (svlast_impl::fold): Update accordingly.
-
-2023-11-27 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112653
- * gimple-ssa.h (gimple_df): Add escaped_return solution.
- * tree-ssa.cc (init_tree_ssa): Reset it.
- (delete_tree_ssa): Likewise.
- * tree-ssa-structalias.cc (escaped_return_id): New.
- (find_func_aliases): Handle non-IPA return stmts by
- adding to ESCAPED_RETURN.
- (set_uids_in_ptset): Adjust HEAP escaping to also cover
- escapes through return.
- (init_base_vars): Initialize ESCAPED_RETURN.
- (compute_points_to_sets): Replace ESCAPED post-processing
- with recording the ESCAPED_RETURN solution.
- * tree-ssa-alias.cc (ref_may_alias_global_p_1): Check
- the ESCAPED_RETUNR solution.
- (dump_alias_info): Dump it.
- * cfgexpand.cc (update_alias_info_with_stack_vars): Update it.
- * ipa-icf.cc (sem_item_optimizer::fixup_points_to_sets):
- Likewise.
- * tree-inline.cc (expand_call_inline): Reset it.
- * tree-parloops.cc (parallelize_loops): Likewise.
- * tree-sra.cc (maybe_add_sra_candidate): Check it.
-
-2023-11-27 Richard Biener <rguenther@suse.de>
- Richard Sandiford <richard.sandiford@arm.com>
-
- PR tree-optimization/112661
- * tree-vect-slp.cc (vect_get_and_check_slp_defs): Defer duplicate-and-
- interleave test to...
- (vect_build_slp_tree_2): ...here, once we have all the operands.
- Skip the test for uniform vectors.
- (vect_create_constant_vectors): Detect uniform vectors. Avoid
- redundant conversions in that case. Use gimple_build_vector_from_val
- to build the vector.
-
-2023-11-27 Richard Sandiford <richard.sandiford@arm.com>
-
- * attribs.cc (excl_hash_traits): Delete.
- (test_attribute_exclusions): Use pair_hash and nofree_string_hash
- instead.
-
-2023-11-27 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Disallow TImode.
-
-2023-11-27 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtin-types.def (BT_FN_UV8HI_UV8HI_UINT):
- Add missing builtin type.
-
-2023-11-27 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtin-types.def: Remove types.
- * config/s390/s390-builtins.def (O_U64): Remove 64-bit literal support.
- Don't restrict s390_vec_rli and s390_verll[bhfg] to immediates.
- * config/s390/s390.cc (s390_const_operand_ok): Remove 64-bit
- literal support.
-
-2023-11-27 Alex Coplan <alex.coplan@arm.com>
- Iain Sandoe <iain@sandoe.co.uk>
-
- PR c++/60512
- * doc/cpp.texi: Document __has_{feature,extension}.
-
-2023-11-27 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112706
- * match.pd (ptr + o ==/!=/- ptr + o'): New patterns.
-
-2023-11-27 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtin-types.def: Add/remove types.
- * config/s390/s390-builtins.def
- (s390_vclfnhs,s390_vclfnls,s390_vcrnfs,s390_vcfn,s390_vcnf):
- Replace type V8HI with UV8HI.
-
-2023-11-27 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtins.def
- (s390_vcefb,s390_vcdgb,s390_vcelfb,s390_vcdlgb,s390_vcfeb,s390_vcgdb,
- s390_vclfeb,s390_vclgdb): Remove flags for non-existing operands
- 2 and 3.
-
-2023-11-27 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.md (*cmphi_ccu): For immediate operand 1 make
- use of constraint n instead of D and chop of high bits in the
- output template.
-
-2023-11-27 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112300
- * config.gcc (mips*-sde-elf*): Append to tm_defines rather than
- overwriting them.
-
-2023-11-27 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md
- (mask_len_gather_load<RATIO1:mode><RATIO1:mode>):
- Remove gather_scatter_valid_offset_mode_p.
- (mask_len_gather_load<mode><mode>): Ditto.
- (mask_len_scatter_store<RATIO1:mode><RATIO1:mode>): Ditto.
- (mask_len_scatter_store<mode><mode>): Ditto.
- * config/riscv/predicates.md (const_1_or_8_operand): New predicate.
- (vector_gs_scale_operand_64): Remove.
- * config/riscv/riscv-protos.h (gather_scatter_valid_offset_mode_p): Remove.
- * config/riscv/riscv-v.cc (expand_gather_scatter): Refine code.
- (gather_scatter_valid_offset_mode_p): Remove.
- * config/riscv/vector-iterators.md: Fix iterator bugs.
-
-2023-11-27 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc
- (riscv_ext_version_table): Set version to ratified 2.0.
- (riscv_subset_list::parse_std_ext): Allow RV64E.
- * config.gcc: Parse base ISA 'rv64e' and ABI 'lp64e'.
- * config/riscv/arch-canonicalize: Parse base ISA 'rv64e'.
- * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
- Define different macro per XLEN. Add handling for ABI_LP64E.
- * config/riscv/riscv-d.cc (riscv_d_handle_target_float_abi):
- Add handling for ABI_LP64E.
- * config/riscv/riscv-opts.h (enum riscv_abi_type): Add ABI_LP64E.
- * config/riscv/riscv.cc (riscv_option_override): Enhance error
- handling to support RV64E and LP64E.
- (riscv_conditional_register_usage): Change "RV32E" in a comment
- to "RV32E/RV64E".
- * config/riscv/riscv.h
- (UNITS_PER_FP_ARG): Add handling for ABI_LP64E.
- (STACK_BOUNDARY): Ditto.
- (ABI_STACK_BOUNDARY): Ditto.
- (MAX_ARGS_IN_REGISTERS): Ditto.
- (ABI_SPEC): Add support for "lp64e".
- * config/riscv/riscv.opt: Parse -mabi=lp64e as ABI_LP64E.
- * doc/invoke.texi: Add documentation of the LP64E ABI.
-
-2023-11-27 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf-helpers.h: Remove.
- * config.gcc: Adapt accordingly.
-
-2023-11-27 Guo Jie <guojie@loongson.cn>
-
- * config/loongarch/loongarch.cc (loongarch_split_plus_constant):
- avoid left shift of negative value -0x8000.
-
-2023-11-27 Guo Jie <guojie@loongson.cn>
-
- * config/loongarch/loongarch.cc
- (enum loongarch_load_imm_method): Add new method.
- (loongarch_build_integer): Add relevant implementations for
- new method.
- (loongarch_move_integer): Ditto.
-
-2023-11-26 Alexander Monakov <amonakov@ispras.ru>
-
- * sort.cc: Use 'sorting networks' in comments.
-
-2023-11-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112599
- * config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p): Add slidedown.
- (vlmax_ta_p): Ditto.
- (pass_avlprop::get_vlmax_ta_preferred_avl): Ditto.
-
-2023-11-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-avlprop.cc (alv_can_be_propagated_p): Fix typo.
- (avl_can_be_propagated_p): Ditto.
- (vlmax_ta_p): Ditto.
-
-2023-11-25 Gerald Pfeifer <gerald@pfeifer.com>
-
- PR other/69374
- * doc/install.texi (Downloading the source): Sort the list of
- front ends and add D, Go, and Modula-2.
-
-2023-11-25 Gerald Pfeifer <gerald@pfeifer.com>
-
- PR target/69374
- * doc/install.texi (Specific) <*-*-freebsd*>: Remove older
- contents referencing GCC 4.x.
-
-2023-11-25 Gerald Pfeifer <gerald@pfeifer.com>
-
- * doc/standards.texi (Standards): Update ISO C++ reference.
-
-2023-11-25 Jakub Jelinek <jakub@redhat.com>
-
- PR target/111408
- * config/i386/i386.md (*jcc_bt<mode>_mask,
- *jcc_bt<SWI48:mode>_mask_1): Add (const_int 0) as expected
- second operand of bt_comparison_operator.
-
-2023-11-25 Andrew Pinski <pinskia@gmail.com>
- Jakub Jelinek <jakub@redhat.com>
-
- PR target/109977
- * config/aarch64/aarch64-simd.md (aarch64_simd_stp<mode>): Use <vwcore>
- rather than %<vw> for alternative with r constraint on input operand.
-
-2023-11-24 Tobias Burnus <tobias@codesourcery.com>
-
- * doc/install.texi (amdgcn-*-amdhsa): Fix URL to ROCm;
- change 'in the future' to 'in LLVM 18'.
-
-2023-11-24 John David Anglin <danglin@gcc.gnu.org>
-
- * config/pa/pa.cc (pa_emit_move_sequence): Use INT14_OK_STRICT
- in a couple of places.
-
-2023-11-24 Martin Jambor <mjambor@suse.cz>
-
- PR middle-end/109849
- * tree-sra.cc (passed_by_ref_in_call): New.
- (sra_initialize): Allocate passed_by_ref_in_call.
- (sra_deinitialize): Free passed_by_ref_in_call.
- (create_access): Add decl pool candidates only if they are not
- already candidates.
- (build_access_from_expr_1): Bail out on ADDR_EXPRs.
- (build_access_from_call_arg): New function.
- (asm_visit_addr): Rename to scan_visit_addr, change the
- disqualification dump message.
- (scan_function): Check taken addresses for all non-call statements,
- including phi nodes. Process all call arguments, including the static
- chain, build_access_from_call_arg.
- (maybe_add_sra_candidate): Relax need_to_live_in_memory check to allow
- non-escaped local variables.
- (sort_and_splice_var_accesses): Disallow smaller-than-precision
- replacements for aggregates passed by reference to functions.
- (sra_modify_expr): Use a separate stmt iterator for adding satements
- before the processed statement and after it.
- (enum out_edge_check): New type.
- (abnormal_edge_after_stmt_p): New function.
- (sra_modify_call_arg): New function.
- (sra_modify_assign): Adjust calls to sra_modify_expr.
- (sra_modify_function_body): Likewise, use sra_modify_call_arg to
- process call arguments, including the static chain.
-
-2023-11-24 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112686
- * config/i386/i386.cc (ix86_expand_split_stack_prologue): Load
- function address to a register for ix86_cmodel == CM_LARGE.
-
-2023-11-24 Tobias Burnus <tobias@codesourcery.com>
-
- * doc/invoke.texi (-Wopenmp): Add.
- * gimplify.cc (gimplify_omp_for): Add OPT_Wopenmp to warning_at.
- * omp-expand.cc (expand_omp_ordered_sink): Likewise.
- * omp-general.cc (omp_check_context_selector): Likewise.
- * omp-low.cc (scan_omp_for, check_omp_nesting_restrictions,
- lower_omp_ordered_clauses): Likewise.
- * omp-simd-clone.cc (simd_clone_clauses_extract): Likewise.
-
-2023-11-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112694
- * config/riscv/riscv-v.cc (preferred_simd_mode): Allow poly_int (1,1) vectors.
-
-2023-11-24 Alexander Monakov <amonakov@ispras.ru>
-
- * config.in: Regenerate.
- * configure: Regenerate.
- * configure.ac: Delete manual checks for old Valgrind headers.
- * system.h (VALGRIND_MAKE_MEM_NOACCESS): Delete.
- (VALGRIND_MAKE_MEM_DEFINED): Delete.
- (VALGRIND_MAKE_MEM_UNDEFINED): Delete.
- (VALGRIND_MALLOCLIKE_BLOCK): Delete.
- (VALGRIND_FREELIKE_BLOCK): Delete.
-
-2023-11-24 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112681
- * config/i386/i386-expand.cc (ix86_expand_branch): Use
- ix86_expand_vector_logical_operator to expand vector XOR rather than
- gen_rtx_SET on gen_rtx_XOR.
-
-2023-11-24 Alex Coplan <alex.coplan@arm.com>
-
- * rtl-ssa/access-utils.h (filter_accesses): New.
- (remove_regno_access): New.
- (check_remove_regno_access): New.
- * rtl-ssa/accesses.cc (rtl_ssa::remove_note_accesses_base): Use
- new filter_accesses helper.
-
-2023-11-24 Alex Coplan <alex.coplan@arm.com>
-
- * rtl-ssa/accesses.cc (function_info::create_set): New.
- * rtl-ssa/accesses.h (access_info::is_temporary): New.
- * rtl-ssa/changes.cc (move_insn): Handle new (temporary) insns.
- (function_info::finalize_new_accesses): Handle new/temporary
- user-created accesses.
- (function_info::apply_changes_to_insn): Ensure m_is_temp flag
- on new insns gets cleared.
- (function_info::change_insns): Handle new/temporary insns.
- (function_info::create_insn): New.
- * rtl-ssa/changes.h (class insn_change): Make function_info a
- friend class.
- * rtl-ssa/functions.h (function_info): Declare new entry points:
- create_set, create_insn. Declare new change_alloc helper.
- * rtl-ssa/insns.cc (insn_info::print_full): Identify temporary insns in
- dump.
- * rtl-ssa/insns.h (insn_info): Add new m_is_temp flag and accompanying
- is_temporary accessor.
- * rtl-ssa/internals.inl (insn_info::insn_info): Initialize m_is_temp to
- false.
- * rtl-ssa/member-fns.inl (function_info::change_alloc): New.
- * rtl-ssa/movement.h (restrict_movement_for_defs_ignoring): Add
- handling for temporary defs.
-
-2023-11-24 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112673
- * match.pd (bit_field_ref (vce @0) -> bit_field_ref @0): Only simplify
- if either @0 doesn't have scalar integral type or if it has mode
- precision.
-
-2023-11-24 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112679
- * gimple-lower-bitint.cc (gimple_lower_bitint): Also stop first loop on
- floating point SSA_NAME set in FLOAT_EXPR assignment from BITINT_TYPE
- INTEGER_CST. Set has_large_huge for those if that BITINT_TYPE is large
- or huge. Set kind to such FLOAT_EXPR assignment rhs1 BITINT_TYPE's kind.
-
-2023-11-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112677
- * tree-vect-loop.cc (vectorizable_reduction): Use alloca
- to allocate vectype_op.
-
-2023-11-24 Haochen Gui <guihaoc@gcc.gnu.org>
-
- * expr.cc (by_pieces_ninsns): Include by pieces compare when
- do the adjustment for overlap operations. Replace mov_optab
- checks with gcc assertion.
-
-2023-11-24 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112668
- * gimple-iterator.h (gsi_end, gsi_end_bb): New inline functions.
- * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): After
- temporarily adding statements after m_init_gsi, update m_init_gsi
- such that later additions after it will be after the added statements.
- (bitint_large_huge::handle_load): Likewise. When splitting
- gsi_bb (m_init_gsi) basic block, update m_preheader_bb if needed
- and update saved m_gsi as well if needed.
- (bitint_large_huge::lower_mergeable_stmt,
- bitint_large_huge::lower_comparison_stmt,
- bitint_large_huge::lower_mul_overflow,
- bitint_large_huge::lower_bit_query): Use gsi_end_bb.
-
-2023-11-24 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/112619
- * tree.cc (try_catch_may_fallthru): If second operand of
- TRY_CATCH_EXPR is not a STATEMENT_LIST, handle it as if it was a
- STATEMENT_LIST containing a single statement.
-
-2023-11-24 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112344
- * tree-chrec.cc (chrec_apply): Only use an unsigned add
- when the overall increment doesn't fit the signed type.
-
-2023-11-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112599
- * config/riscv/riscv-v.cc (shuffle_extract_and_slide1up_patterns): New function.
- (expand_vec_perm_const_1): Add new optimization.
-
-2023-11-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (shuffle_bswap_pattern): Disable for NUNIT < 4.
-
-2023-11-24 Haochen Jiang <haochen.jiang@intel.com>
-
- PR target/112643
- * config/i386/driver-i386.cc (check_avx10_avx512_features):
- Renamed to ...
- (check_avx512_features): this and remove avx10 check.
- (host_detect_local_cpu): Never append -mno-avx10.1-{256,512} to
- avoid emitting warnings when building GCC with native arch.
- * config/i386/i386-builtin.def (BDESC): Add missing AVX512VL for
- 128/256 bit builtin for AVX512VP2INTERSECT.
- * config/i386/i386-options.cc (ix86_option_override_internal):
- Also check whether the AVX512 flags is set when trying to reset.
- * config/i386/i386.h
- (PTA_SKYLAKE_AVX512): Add missing PTA_EVEX512.
- (PTA_ZNVER4): Ditto.
-
-2023-11-23 Georg-Johann Lay <avr@gjlay.de>
-
- PR target/86776
- * config/avr/avr.cc (TARGET_HAVE_SPECULATION_SAFE_VALUE): Define
- to speculation_safe_value_not_needed.
-
-2023-11-23 Marek Polacek <polacek@redhat.com>
-
- * common.opt (Whardened, fhardened): New options.
- * config.in: Regenerate.
- * config/bpf/bpf.cc: Include "opts.h".
- (bpf_option_override): If flag_stack_protector_set_by_fhardened_p, do
- not inform that -fstack-protector does not work.
- * config/i386/i386-options.cc (ix86_option_override_internal): When
- -fhardened, maybe enable -fcf-protection=full.
- * config/linux-protos.h (linux_fortify_source_default_level): Declare.
- * config/linux.cc (linux_fortify_source_default_level): New.
- * config/linux.h (TARGET_FORTIFY_SOURCE_DEFAULT_LEVEL): Redefine.
- * configure: Regenerate.
- * configure.ac: Check if the linker supports '-z now' and '-z relro'.
- Check if -fhardened is supported on $target_os.
- * doc/invoke.texi: Document -fhardened and -Whardened.
- * doc/tm.texi: Regenerate.
- * doc/tm.texi.in (TARGET_FORTIFY_SOURCE_DEFAULT_LEVEL): Add.
- * gcc.cc (driver_handle_option): Remember if any link options or -static
- were specified on the command line.
- (process_command): When -fhardened, maybe enable -pie and
- -Wl,-z,relro,-z,now.
- * opts.cc (flag_stack_protector_set_by_fhardened_p): New global.
- (finish_options): When -fhardened, enable
- -ftrivial-auto-var-init=zero and -fstack-protector-strong.
- (print_help_hardened): New.
- (print_help): Call it.
- * opts.h (flag_stack_protector_set_by_fhardened_p): Declare.
- * target.def (fortify_source_default_level): New target hook.
- * targhooks.cc (default_fortify_source_default_level): New.
- * targhooks.h (default_fortify_source_default_level): Declare.
- * toplev.cc (process_options): When -fhardened, enable
- -fstack-clash-protection. If flag_stack_protector_set_by_fhardened_p,
- do not warn that -fstack-protector not supported for this target.
- Don't enable -fhardened when !HAVE_FHARDENED_SUPPORT.
-
-2023-11-23 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-functions.h
- (full_width_access::memory_vector_mode): Add default clause.
-
-2023-11-23 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112672
- * config/i386/i386.md (parityhi2):
- Use temporary register in the call to gen_parityhi2_cmp.
-
-2023-11-23 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/89316
- * config/i386/i386.cc (ix86_expand_split_stack_prologue): Obtain
- scratch regno when flag_force_indirect_call is set. On 64-bit
- targets, call __morestack_large_model when flag_force_indirect_call
- is set and on 32-bit targets with -fpic, manually expand PIC sequence
- to call __morestack. Move the function address to an indirect
- call scratch register.
-
-2023-11-23 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- PR tree-optimization/112678
- * tree-profile.cc (tree_profiling): Do not use atomic operations
- for -fprofile-update=single.
-
-2023-11-23 Juergen Christ <jchrist@linux.ibm.com>
-
- * config/s390/s390-c.cc (s390_cpu_cpp_builtins): Define
- __GCC_ASM_FLAG_OUTPUTS__.
- * config/s390/s390.cc (s390_canonicalize_comparison): More
- UNSPEC_CC_TO_INT cases.
- (s390_md_asm_adjust): Implement flags output.
- * config/s390/s390.md (ccstore4): Allow mask operands.
- * doc/extend.texi: Document flags output.
-
-2023-11-23 Juergen Christ <jchrist@linux.ibm.com>
-
- * config/s390/s390.md: Split TImode loads.
-
-2023-11-23 Juergen Christ <jchrist@linux.ibm.com>
-
- * config/s390/vector.md: (*vec_extract) Fix.
-
-2023-11-23 Di Zhao <dizhao@os.amperecomputing.com>
-
- * tree-ssa-reassoc.cc (get_reassociation_width): check
- for loop dependent FMAs.
- (reassociate_bb): For 3 ops, refine the condition to call
- swap_ops_for_binary_stmt.
-
-2023-11-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (emit_vec_extract): New function.
- * config/riscv/riscv-v.cc (emit_vec_extract): Ditto.
- * config/riscv/riscv.cc (riscv_legitimize_move): Refine codes.
-
-2023-11-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112599
- PR target/112670
- * config/riscv/riscv-avlprop.cc (alv_can_be_propagated_p): New function.
- (vlmax_ta_p): Disable vrgather AVL propagation.
-
-2023-11-23 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112336
- * expr.cc (EXTEND_BITINT): Don't call reduce_to_bit_field_precision
- if modifier is EXPAND_INITIALIZER.
-
-2023-11-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Refine codes.
- (emit_vlmax_masked_gather_mu_insn): Ditto.
- (modulo_sel_indices): Ditto.
- (expand_vec_perm): Ditto.
- (shuffle_generic_patterns): Ditto.
-
-2023-11-23 Jakub Jelinek <jakub@redhat.com>
-
- * doc/extend.texi (__builtin_stdc_bit_ceil, __builtin_stdc_bit_floor,
- __builtin_stdc_bit_width, __builtin_stdc_count_ones,
- __builtin_stdc_count_zeros, __builtin_stdc_first_leading_one,
- __builtin_stdc_first_leading_zero, __builtin_stdc_first_trailing_one,
- __builtin_stdc_first_trailing_zero, __builtin_stdc_has_single_bit,
- __builtin_stdc_leading_ones, __builtin_stdc_leading_zeros,
- __builtin_stdc_trailing_ones, __builtin_stdc_trailing_zeros): Document.
-
-2023-11-23 Richard Biener <rguenther@suse.de>
-
- PR middle-end/32667
- * doc/md.texi (cpymem): Document that exact overlap of source
- and destination needs to work.
- * doc/standards.texi (ffreestanding): Mention memcpy is required
- to handle the exact overlap case.
-
-2023-11-23 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/110348
- * doc/invoke.texi (-Wno-c++26-extensions): Document.
-
-2023-11-23 Manolis Tsamis <manolis.tsamis@vrull.eu>
-
- * ifcvt.cc (noce_convert_multiple_sets_1): Remove old code.
-
-2023-11-23 Pan Li <pan2.li@intel.com>
-
- PR target/111720
- * dse.cc (get_stored_val): Allow vector mode if read size is
- less than or equal to stored size.
-
-2023-11-23 Costas Argyris <costas.argyris@gmail.com>
-
- * configure.ac: Handle new --enable-win32-utf8-manifest
- option.
- * config.host: allow win32 utf8 manifest to be disabled
- by user.
- * configure: Regenerate.
-
-2023-11-22 John David Anglin <danglin@gcc.gnu.org>
-
- PR target/112592
- * config/pa/pa.h (MAX_FIXED_MODE_SIZE): Define.
-
-2023-11-22 John David Anglin <danglin@gcc.gnu.org>
-
- PR target/112617
- * config/pa/predicates.md (integer_store_memory_operand): Return
- true for REG+D addresses when reload_in_progress is true.
-
-2023-11-22 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112344
- * tree-chrec.cc (chrec_apply): Perform the overall increment
- calculation and increment in an unsigned type.
-
-2023-11-22 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-valu.md (*mov<mode>_4reg): Disparage AVGPR use when a
- reload is required.
-
-2023-11-22 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/112610
- * ira-costs.cc: (find_costs_and_classes): Remove arg.
- Use ira_dump_file for printing.
- (print_allocno_costs, print_pseudo_costs): Ditto.
- (ira_costs): Adjust call of find_costs_and_classes.
- (ira_set_pseudo_classes): Set up and restore ira_dump_file.
-
-2023-11-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112598
- * config/riscv/riscv-v.cc (shuffle_compress_patterns): Fix vcompress bug.
-
-2023-11-22 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64-simd.md
- (aarch64_uaddw<mode>_<PERM_EXTEND:perm_hilo>_zip,
- aarch64_usubw<mode>_<PERM_EXTEND:perm_hilo>_zip): Split into...
- (aarch64_uaddw<mode>_lo_zip, aarch64_uaddw<mode>_hi_zip,
- "aarch64_usubw<mode>_lo_zip, "aarch64_usubw<mode>_hi_zip): ... This.
- * config/aarch64/iterators.md (PERM_EXTEND, perm_index): Remove.
- (perm_hilo): Remove UNSPEC_ZIP1, UNSPEC_ZIP2.
-
-2023-11-22 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins.cc
- (function_resolver::infer_pointer_type): Remove spurious line.
-
-2023-11-22 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/lsx.md (vec_perm<mode:LSX>): Make the
- selector VIMODE.
- * config/loongarch/loongarch.cc (loongarch_expand_vec_perm):
- Use the mode of the selector (instead of the shuffled vector)
- for truncating it. Operate on subregs in the selector mode if
- the shuffled vector has a different mode (i. e. it's a
- floating-point vector).
-
-2023-11-22 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386.md (push2_di): Adjust operand order for AT&T
- syntax.
- (pop2_di): Likewise.
- (push2p_di): Likewise.
- (pop2p_di): Likewise.
-
-2023-11-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112598
- * config/riscv/riscv-v.cc (emit_vlmax_gather_insn): Adapt the priority.
- (shuffle_generic_patterns): Fix permutation indice bug.
- * config/riscv/vector-iterators.md: Fix VEI16 bug.
-
-2023-11-22 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/sse.md (cbranch<mode>4): Extend to Vector
- HI/QImode.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- PR target/111815
- * config/vax/vax.cc (index_term_p): Only accept the index scaler
- as the RHS operand to ASHIFT.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/predicates.md (order_operator): Remove predicate.
- * config/riscv/riscv.cc (riscv_rtx_costs): Update accordingly.
- * config/riscv/riscv.md (*branch<mode>, *mov<GPR:mode><X:mode>cc)
- (cstore<mode>4): Likewise.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv-protos.h (riscv_expand_float_scc): Add
- `invert_ptr' parameter.
- * config/riscv/riscv.cc (riscv_emit_float_compare): Add NE
- inversion handling.
- (riscv_expand_float_scc): Pass `invert_ptr' through to
- `riscv_emit_float_compare'.
- (riscv_expand_conditional_move): Pass `&invert' to
- `riscv_expand_float_scc'.
- * config/riscv/riscv.md (add<mode>cc): Likewise.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_emit_float_compare) <NE>: Handle
- separately.
- <EQ, LE, LT, GE, GT>: Return operands supplied as is.
- (riscv_emit_binary): Call `riscv_emit_binary' directly rather
- than going through a temporary register for word-mode targets.
- (riscv_expand_conditional_branch): Canonicalize the comparison
- if not against constant zero.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/predicates.md (ne_operator): New predicate.
- * config/riscv/riscv.cc (riscv_insn_cost): Handle branches on a
- floating-point condition.
- * config/riscv/riscv.md (@cbranch<mode>4): Rename expander to...
- (@cbranch<ANYF:mode>4): ... this. Only expand the RTX via
- `riscv_expand_conditional_branch' for `!signed_order_operator'
- operators, otherwise let it through.
- (*cbranch<ANYF:mode>4, *cbranch<ANYF:mode>4): New insns and
- splitters.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Don't
- bail out in floating-point conditions.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_float_scc): Suppress the
- use of SUBREG if the conditional-set target is word-mode.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.md (add<mode>cc): New expander.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/predicates.md (movcc_operand): New predicate.
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Handle
- generic targets.
- * config/riscv/riscv.md (mov<mode>cc): Likewise.
- * config/riscv/riscv.opt (mmovcc): New option.
- * doc/invoke.texi (Option Summary): Document it.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv-protos.h (riscv_emit_unary): New prototype.
- * config/riscv/riscv.cc (riscv_emit_unary): New function.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Unify
- conditional-move handling across all the relevant targets.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Also
- accept constants for T-Head data input operands.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Also
- accept constants for T-Head comparison operands.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Remove
- the check for operand 1 being constant 0 in the Ventana/Zicond
- case for equality comparisons.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Also
- invert the condition for GEU and LEU.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_insn_cost): New function.
- (riscv_max_noce_ifcvt_seq_cost): Likewise.
- (riscv_noce_conversion_profitable_p): Likewise.
- (TARGET_INSN_COST): New macro.
- (TARGET_MAX_NOCE_IFCVT_SEQ_COST): New macro.
- (TARGET_NOCE_CONVERSION_PROFITABLE_P): New macro.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Remove
- extraneous variable for EQ vs NE operation selection.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Use
- `nullptr' rather than 0 to initialize a pointer.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Use
- `mode0' and `mode1' for `GET_MODE (op0)' and `GET_MODE (op1)'.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_expand_conditional_move): Use
- `mode' for `GET_MODE (dest)' throughout.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.cc (riscv_emit_int_compare): Bail out if
- NEED_EQ_NE_P but the comparison is neither EQ nor NE.
-
-2023-11-22 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.md (mov<mode>cc): Move comment on SFB
- patterns over to...
- (*mov<GPR:mode><X:mode>cc): ... here.
-
-2023-11-21 Robin Dapp <rdapp@ventanamicro.com>
-
- PR middle-end/112406
- * tree-vect-loop.cc (vectorize_fold_left_reduction): Allow
- reduction index != 1.
- (vect_transform_reduction): Handle reduction index != 1.
-
-2023-11-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * common.md (aligned_register_operand): New predicate.
-
-2023-11-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * ira-int.h (ira_allocno): Add a register_filters field.
- (ALLOCNO_REGISTER_FILTERS): New macro.
- (ALLOCNO_SET_REGISTER_FILTERS): Likewise.
- * ira-build.cc (ira_create_allocno): Initialize register_filters.
- (create_cap_allocno): Propagate register_filters.
- (propagate_allocno_info): Likewise.
- (propagate_some_info_from_allocno): Likewise.
- * ira-lives.cc (process_register_constraint_filters): New function.
- (process_bb_node_lives): Use it to record register filter
- information.
- * ira-color.cc (assign_hard_reg): Check register filters.
- (improve_allocation, fast_allocation): Likewise.
-
-2023-11-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * lra-constraints.cc (process_alt_operands): Check register filters.
-
-2023-11-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * recog.h (operand_alternative): Add a register_filters field.
- (alternative_register_filters): New function.
- * recog.cc (preprocess_constraints): Calculate the filters field.
- (constrain_operands): Check register filters.
-
-2023-11-21 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl.def (DEFINE_REGISTER_CONSTRAINT): Add an optional filter
- operand.
- * doc/md.texi (define_register_constraint): Document it.
- * doc/tm.texi.in: Reference it in discussion about aligned registers.
- * doc/tm.texi: Regenerate.
- * gensupport.h (register_filters, get_register_filter_id): Declare.
- * gensupport.cc (register_filter_map, register_filters): New variables.
- (get_register_filter_id): New function.
- (process_define_register_constraint): Likewise.
- (process_rtx): Pass define_register_constraints to
- process_define_register_constraint.
- * genconfig.cc (main): Emit a definition of NUM_REGISTER_FILTERS.
- * genpreds.cc (constraint_data): Add a filter field.
- (add_constraint): Update accordingly.
- (process_define_register_constraint): Pass the filter operand.
- (write_init_reg_class_start_regs): New function.
- (write_get_register_filter): Likewise.
- (write_get_register_filter_id): Likewise.
- (write_tm_preds_h): Write a definition of target_constraints,
- plus helpers to test its contents. Write the get_register_filter*
- functions.
- (write_insn_preds_c): Write init_reg_class_start_regs.
- * reginfo.cc (init_reg_class_start_regs): Declare.
- (init_reg_sets): Call it.
- * target-globals.h (this_target_constraints): Declare.
- (target_globals): Add a constraints field.
- (restore_target_globals): Update accordingly.
- * target-globals.cc: Include tm_p.h.
- (default_target_globals): Initialize the constraints field.
- (save_target_globals): Handle the constraints field.
- (target_globals::~target_globals): Likewise.
-
-2023-11-21 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112623
- * tree-ssa-forwprop.cc (simplify_vector_constructor):
- Check the source mode of the insn for vector pack/unpacks.
-
-2023-11-21 Richard Biener <rguenther@suse.de>
-
- * tree-vect-loop.cc (vect_analyze_loop_2): Move check
- of VF against max_vf until VF is final.
-
-2023-11-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112598
- * config/riscv/riscv.cc (riscv_const_insns): Disallow DI CONST_VECTOR on RV32.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_override_options): Rework warnings.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- PR target/111370
- * config/aarch64/aarch64-arches.def (armv9-a, armv9.1-a, armv9.2-a,
- armv9.3-a): Update to generic-armv9-a.
- * config/aarch64/aarch64-cores.def (generic-armv9-a): New.
- * config/aarch64/aarch64-tune.md: Regenerate.
- * config/aarch64/aarch64.cc: Include generic_armv9_a.h.
- * config/aarch64/tuning_models/generic_armv9_a.h: New file.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- PR target/111370
- * config/aarch64/aarch64-arches.def (armv8-9, armv8-a, armv8.1-a,
- armv8.2-a, armv8.3-a, armv8.4-a, armv8.5-a, armv8.6-a, armv8.7-a,
- armv8.8-a): Update to generic_armv8_a.
- * config/aarch64/aarch64-cores.def (generic-armv8-a): New.
- * config/aarch64/aarch64-tune.md: Regenerate.
- * config/aarch64/aarch64.cc: Include generic_armv8_a.h
- * config/aarch64/aarch64.h (TARGET_CPU_DEFAULT): Change to
- TARGET_CPU_generic_armv8_a.
- * config/aarch64/tuning_models/generic_armv8_a.h: New file.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- PR target/111370
- * config/aarch64/aarch64-cores.def: Add generic.
- * config/aarch64/aarch64-opts.h (enum aarch64_proc): Remove generic.
- * config/aarch64/aarch64-tune.md: Regenerate
- * config/aarch64/aarch64.cc (all_cores): Remove generic
- * config/aarch64/aarch64.h (enum target_cpus): Remove
- TARGET_CPU_generic.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- PR target/111370
- * config/aarch64/aarch64.cc (generic_addrcost_table,
- exynosm1_addrcost_table,
- xgene1_addrcost_table,
- thunderx2t99_addrcost_table,
- thunderx3t110_addrcost_table,
- tsv110_addrcost_table,
- qdf24xx_addrcost_table,
- a64fx_addrcost_table,
- neoversev1_addrcost_table,
- neoversen2_addrcost_table,
- neoversev2_addrcost_table,
- generic_regmove_cost,
- cortexa57_regmove_cost,
- cortexa53_regmove_cost,
- exynosm1_regmove_cost,
- thunderx_regmove_cost,
- xgene1_regmove_cost,
- qdf24xx_regmove_cost,
- thunderx2t99_regmove_cost,
- thunderx3t110_regmove_cost,
- tsv110_regmove_cost,
- a64fx_regmove_cost,
- neoversen2_regmove_cost,
- neoversev1_regmove_cost,
- neoversev2_regmove_cost,
- generic_vector_cost,
- a64fx_vector_cost,
- qdf24xx_vector_cost,
- thunderx_vector_cost,
- tsv110_vector_cost,
- cortexa57_vector_cost,
- exynosm1_vector_cost,
- xgene1_vector_cost,
- thunderx2t99_vector_cost,
- thunderx3t110_vector_cost,
- ampere1_vector_cost,
- generic_branch_cost,
- generic_tunings,
- cortexa35_tunings,
- cortexa53_tunings,
- cortexa57_tunings,
- cortexa72_tunings,
- cortexa73_tunings,
- exynosm1_tunings,
- thunderxt88_tunings,
- thunderx_tunings,
- tsv110_tunings,
- xgene1_tunings,
- emag_tunings,
- qdf24xx_tunings,
- saphira_tunings,
- thunderx2t99_tunings,
- thunderx3t110_tunings,
- neoversen1_tunings,
- ampere1_tunings,
- ampere1a_tunings,
- neoversev1_vector_cost,
- neoversev1_tunings,
- neoverse512tvb_vector_cost,
- neoverse512tvb_tunings,
- neoversen2_vector_cost,
- neoversen2_tunings,
- neoversev2_vector_cost,
- neoversev2_tunings
- a64fx_tunings): Split into own files.
- * config/aarch64/tuning_models/a64fx.h: New file.
- * config/aarch64/tuning_models/ampere1.h: New file.
- * config/aarch64/tuning_models/ampere1a.h: New file.
- * config/aarch64/tuning_models/cortexa35.h: New file.
- * config/aarch64/tuning_models/cortexa53.h: New file.
- * config/aarch64/tuning_models/cortexa57.h: New file.
- * config/aarch64/tuning_models/cortexa72.h: New file.
- * config/aarch64/tuning_models/cortexa73.h: New file.
- * config/aarch64/tuning_models/emag.h: New file.
- * config/aarch64/tuning_models/exynosm1.h: New file.
- * config/aarch64/tuning_models/generic.h: New file.
- * config/aarch64/tuning_models/neoverse512tvb.h: New file.
- * config/aarch64/tuning_models/neoversen1.h: New file.
- * config/aarch64/tuning_models/neoversen2.h: New file.
- * config/aarch64/tuning_models/neoversev1.h: New file.
- * config/aarch64/tuning_models/neoversev2.h: New file.
- * config/aarch64/tuning_models/qdf24xx.h: New file.
- * config/aarch64/tuning_models/saphira.h: New file.
- * config/aarch64/tuning_models/thunderx.h: New file.
- * config/aarch64/tuning_models/thunderx2t99.h: New file.
- * config/aarch64/tuning_models/thunderx3t110.h: New file.
- * config/aarch64/tuning_models/thunderxt88.h: New file.
- * config/aarch64/tuning_models/tsv110.h: New file.
- * config/aarch64/tuning_models/xgene1.h: New file.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64-simd.md (vec_unpack<su>_lo_<mode,
- vec_unpack<su>_lo_<mode): Split into...
- (vec_unpacku_lo_<mode, vec_unpacks_lo_<mode,
- vec_unpacku_lo_<mode, vec_unpacks_lo_<mode): ...These.
- (aarch64_usubw<mode>_<PERM_EXTEND:perm_hilo>_zip): New.
- (aarch64_uaddw<mode>_<PERM_EXTEND:perm_hilo>_zip): New.
- * config/aarch64/iterators.md (PERM_EXTEND, perm_index): New.
- (perm_hilo): Add UNSPEC_ZIP1, UNSPEC_ZIP2.
-
-2023-11-21 Tamar Christina <tamar.christina@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_adjust_stmt_cost): Guard mla.
- (aarch64_vector_costs::count_ops): Likewise.
-
-2023-11-21 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- PR middle-end/112634
- * tree-profile.cc (gen_assign_counter_update): Cast the unsigned result type of
- __atomic_add_fetch() to the signed counter type.
- (gen_counter_update): Fix formatting.
-
-2023-11-21 Jakub Jelinek <jakub@redhat.com>
-
- * tree-profile.cc (gen_counter_update, tree_profiling): Formatting
- fixes.
-
-2023-11-21 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112639
- * builtins.cc (fold_builtin_bit_query): If arg0 has side-effects, arg1
- is specified but cleared, call save_expr on arg0.
-
-2023-11-21 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/i386-expand.h (gen_push): Add default bool
- parameter.
- (gen_pop): Likewise.
- * config/i386/i386-opts.h (enum apx_features): Add apx_ppx, add
- it to apx_all.
- * config/i386/i386.cc (ix86_emit_restore_reg_using_pop): Add
- ppx_p parameter for function declaration.
- (gen_push2): Add ppx_p parameter, emit push2p if ppx_p is true.
- (gen_push): Likewise.
- (ix86_emit_restore_reg_using_pop2): Likewise for pop2p.
- (ix86_emit_save_regs): Emit pushp/push2p under TARGET_APX_PPX.
- (ix86_emit_restore_reg_using_pop): Add ppx_p, emit popp insn
- and adjust cfi when ppx_p is ture.
- (ix86_emit_restore_reg_using_pop2): Add ppx_p and parse to its
- callee.
- (ix86_emit_restore_regs_using_pop2): Likewise.
- (ix86_expand_epilogue): Parse TARGET_APX_PPX to
- ix86_emit_restore_reg_using_pop.
- * config/i386/i386.h (TARGET_APX_PPX): New.
- * config/i386/i386.md (UNSPEC_APX_PPX): New unspec.
- (pushp_di): New define_insn.
- (popp_di): Likewise.
- (push2p_di): Likewise.
- (pop2p_di): Likewise.
- * config/i386/i386.opt: Add apx_ppx enum.
-
-2023-11-21 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111970
- * tree-vect-stmts.cc (vectorizable_load): Fix offset calculation
- for SLP gather load.
- (vectorizable_store): Likewise for SLP scatter store.
-
-2023-11-21 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-def.h (stdint.h): Guard with #if to
- exclude it for target libraries.
- (loongarch_isa_base_features): Likewise.
- (loongarch_isa): Likewise.
- (loongarch_abi): Likewise.
- (loongarch_target): Likewise.
- (loongarch_cpu_default_isa): Likewise.
-
-2023-11-21 liuhongt <hongtao.liu@intel.com>
-
- PR target/112325
- * config/i386/i386-expand.cc (emit_reduc_half): Hanlde
- V8QImode.
- * config/i386/mmx.md (reduc_<code>_scal_<mode>): New expander.
- (reduc_<code>_scal_v4qi): Ditto.
-
-2023-11-20 Marc Poulhiès <dkm@kataplop.net>
-
- * config/nvptx/nvptx.h (struct machine_function): Fix typo in variadic.
- * config/nvptx/nvptx.cc (nvptx_function_arg_advance): Adjust to use fixed name.
- (nvptx_declare_function_name): Likewise.
- (nvptx_call_args): Likewise.
- (nvptx_expand_call): Likewise.
-
-2023-11-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * tree-profile.cc (gen_counter_update): Use unshare_expr() for the
- counter expression in the second gimple_build_assign().
-
-2023-11-20 Jan Hubicka <jh@suse.cz>
-
- * cgraph.cc (add_detected_attribute_1): New function.
- (cgraph_node::add_detected_attribute): Likewise.
- * cgraph.h (cgraph_node::add_detected_attribute): Declare.
- * common.opt: Add -Wsuggest-attribute=returns_nonnull.
- * doc/invoke.texi: Document new flag.
- * gimple-range-fold.cc (fold_using_range::range_of_call):
- Use known reutrn value ranges.
- * ipa-prop.cc (struct ipa_return_value_summary): New type.
- (class ipa_return_value_sum_t): New type.
- (ipa_return_value_sum): New summary.
- (ipa_record_return_value_range): New function.
- (ipa_return_value_range): New function.
- * ipa-prop.h (ipa_return_value_range): Declare.
- (ipa_record_return_value_range): Declare.
- * ipa-pure-const.cc (warn_function_returns_nonnull): New funcion.
- * ipa-utils.h (warn_function_returns_nonnull): Declare.
- * symbol-summary.h: Fix comment.
- * tree-vrp.cc (execute_ranger_vrp): Record return values.
-
-2023-11-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112618
- * tree-vect-loop.cc (vect_transform_loop_stmt): For not
- relevant and unused .MASK_CALL make sure we remove the
- scalar stmt.
-
-2023-11-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112281
- * tree-loop-distribution.cc
- (loop_distribution::pg_add_dependence_edges): For = in the
- innermost common loop record a partition conflict.
-
-2023-11-20 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112622
- * convert.cc (convert_to_real_1): Use element_precision
- where a vector type might appear. Provide specific
- diagnostic for unexpected vector argument.
-
-2023-11-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112597
- * config/riscv/vector-iterators.md: Remove VDEMOTE and VMDEMOTE.
- * config/riscv/vector.md: Fix slide1 intermediate mode bug.
-
-2023-11-20 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv-v.cc (gather_scatter_valid_offset_mode_p):
- Add check for XLEN == 32.
- * config/riscv/vector-iterators.md: Change VLS part of the
- demote iterator to 2x elements modes
- * config/riscv/vector.md: Adjust iterators and insn conditions.
-
-2023-11-20 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-base.cc (vld1_impl, vld1q)
- (vst1_impl, vst1q): New.
- * config/arm/arm-mve-builtins-base.def (vld1q, vst1q): New.
- * config/arm/arm-mve-builtins-base.h (vld1q, vst1q): New.
- * config/arm/arm_mve.h
- (vld1q): Delete.
- (vst1q): Delete.
- (vld1q_s8): Delete.
- (vld1q_s32): Delete.
- (vld1q_s16): Delete.
- (vld1q_u8): Delete.
- (vld1q_u32): Delete.
- (vld1q_u16): Delete.
- (vld1q_f32): Delete.
- (vld1q_f16): Delete.
- (vst1q_f32): Delete.
- (vst1q_f16): Delete.
- (vst1q_s8): Delete.
- (vst1q_s32): Delete.
- (vst1q_s16): Delete.
- (vst1q_u8): Delete.
- (vst1q_u32): Delete.
- (vst1q_u16): Delete.
- (__arm_vld1q_s8): Delete.
- (__arm_vld1q_s32): Delete.
- (__arm_vld1q_s16): Delete.
- (__arm_vld1q_u8): Delete.
- (__arm_vld1q_u32): Delete.
- (__arm_vld1q_u16): Delete.
- (__arm_vst1q_s8): Delete.
- (__arm_vst1q_s32): Delete.
- (__arm_vst1q_s16): Delete.
- (__arm_vst1q_u8): Delete.
- (__arm_vst1q_u32): Delete.
- (__arm_vst1q_u16): Delete.
- (__arm_vld1q_f32): Delete.
- (__arm_vld1q_f16): Delete.
- (__arm_vst1q_f32): Delete.
- (__arm_vst1q_f16): Delete.
- (__arm_vld1q): Delete.
- (__arm_vst1q): Delete.
- * config/arm/mve.md (mve_vld1q_f<mode>): Rename into ...
- (@mve_vld1q_f<mode>): ... this.
- (mve_vld1q_<supf><mode>): Rename into ...
- (@mve_vld1q_<supf><mode>) ... this.
- (mve_vst1q_f<mode>): Rename into ...
- (@mve_vst1q_f<mode>): ... this.
- (mve_vst1q_<supf><mode>): Rename into ...
- (@mve_vst1q_<supf><mode>) ... this.
-
-2023-11-20 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-shapes.cc (load, store): New.
- * config/arm/arm-mve-builtins-shapes.h (load, store): New.
-
-2023-11-20 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-functions.h (multi_vector_function)
- (full_width_access): New classes.
- * config/arm/arm-mve-builtins.cc
- (find_type_suffix_for_scalar_type, infer_pointer_type)
- (require_pointer_type, get_contiguous_base, add_mem_operand)
- (add_fixed_operand, use_contiguous_load_insn)
- (use_contiguous_store_insn): New.
- * config/arm/arm-mve-builtins.h (memory_vector_mode)
- (infer_pointer_type, require_pointer_type, get_contiguous_base)
- (add_mem_operand)
- (add_fixed_operand, use_contiguous_load_insn)
- (use_contiguous_store_insn): New.
-
-2023-11-20 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-mve-builtins-shapes.cc (build_const_pointer):
- New.
- (parse_type): Add support for '_', 'al' and 'as'.
- * config/arm/arm-mve-builtins.h (function_instance): Add
- memory_scalar_type.
- (function_base): Likewise.
-
-2023-11-20 Christophe Lyon <christophe.lyon@linaro.org>
-
- * config/arm/arm-builtins.cc (arm_init_simd_builtin_types): Fix
- initialization of arm_simd_types[].eltype.
- * config/arm/arm-mve-builtins.def (DEF_MVE_TYPE): Fix scalar
- types.
-
-2023-11-20 Jakub Jelinek <jakub@redhat.com>
-
- * typeclass.h (enum type_class): Add vector_type_class.
- * builtins.cc (type_to_class): Return vector_type_class for
- VECTOR_TYPE.
- * doc/extend.texi (__builtin_classify_type): Mention bit-precise
- integer types and vector types.
-
-2023-11-20 Robin Dapp <rdapp@ventanamicro.com>
-
- PR middle-end/112406
- * tree-vect-patterns.cc (vect_recog_mask_conversion_pattern):
- Convert masks for conditional operations as well.
-
-2023-11-20 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/90693
- * tree-ssa-math-opts.cc (match_single_bit_test): Mark POPCOUNT with
- result only used in equality comparison against 1 with direct optab
- support as .POPCOUNT call with 2 arguments.
- * internal-fn.h (expand_POPCOUNT): Declare.
- * internal-fn.def (DEF_INTERNAL_INT_EXT_FN): New macro, document it,
- undefine at the end.
- (POPCOUNT): Use it instead of DEF_INTERNAL_INT_FN.
- * internal-fn.cc (DEF_INTERNAL_INT_EXT_FN): Define to nothing before
- inclusion to define expanders.
- (expand_POPCOUNT): New function.
-
-2023-11-20 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/90693
- * tree-ssa-math-opts.cc (match_single_bit_test): New function.
- (math_opts_dom_walker::after_dom_children): Call it for EQ_EXPR
- and NE_EXPR assignments and GIMPLE_CONDs.
-
-2023-11-20 Jakub Jelinek <jakub@redhat.com>
-
- * internal-fn.def: Document missing DEF_INTERNAL* macros and make sure
- they are all undefined at the end.
- * internal-fn.cc (lookup_hilo_internal_fn, lookup_evenodd_internal_fn,
- widening_fn_p, get_len_internal_fn): Don't undef DEF_INTERNAL_*FN
- macros after inclusion of internal-fn.def.
-
-2023-11-20 Haochen Jiang <haochen.jiang@intel.com>
-
- * common/config/i386/cpuinfo.h (get_available_features):
- Add avx10_set and version and detect avx10.1.
- (cpu_indicator_init): Handle avx10.1-512.
- * common/config/i386/i386-common.cc
- (OPTION_MASK_ISA2_AVX10_1_256_SET): New.
- (OPTION_MASK_ISA2_AVX10_1_256_SET): Ditto.
- (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
- (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
- (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10.1.
- (ix86_handle_option): Handle -mavx10.1-256 and -mavx10.1-512.
- Add indicator for explicit no-avx512 and no-avx10.1 options.
- * common/config/i386/i386-cpuinfo.h (enum processor_features):
- Add FEATURE_AVX10_1_256 and FEATURE_AVX10_1_512.
- * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
- AVX10_1_256 and AVX10_1_512.
- * config/i386/cpuid.h (bit_AVX10): New.
- (bit_AVX10_256): Ditto.
- (bit_AVX10_512): Ditto.
- * config/i386/driver-i386.cc (check_avx10_avx512_features): New.
- (host_detect_local_cpu): Do not append "-mno-" options under
- specific scenarios to avoid emitting a warning.
- * config/i386/i386-isa.def
- (EVEX512): Add DEF_PTA(EVEX512).
- (AVX10_1_256): Add DEF_PTA(AVX10_1_256).
- (AVX10_1_512): Add DEF_PTA(AVX10_1_512).
- * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1-256 and
- -mavx10.1-512.
- (ix86_function_specific_save): Save explicit no indicator.
- (ix86_function_specific_restore): Restore explicit no indicator.
- (ix86_valid_target_attribute_inner_p): Handle avx10.1, avx10.1-256 and
- avx10.1-512.
- (ix86_valid_target_attribute_tree): Handle avx512 function
- attributes with avx10.1 command line option.
- (ix86_option_override_internal): Handle AVX10.1 options.
- * config/i386/i386.h: Add PTA_EVEX512 for AVX512 target
- machines.
- * config/i386/i386.opt: Add variable ix86_no_avx512_explicit and
- ix86_no_avx10_1_explicit, option -mavx10.1, -mavx10.1-256 and
- -mavx10.1-512.
- * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512.
- * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512.
- * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256
- and avx10.1-512.
-
-2023-11-20 liuhongt <hongtao.liu@intel.com>
-
- PR target/112325
- * config/i386/sse.md (reduc_<code>_scal_<mode>): New expander.
- (REDUC_ANY_LOGIC_MODE): New iterator.
- (REDUC_PLUS_MODE): Extend to VxHI/SI/DImode.
- (REDUC_SSE_PLUS_MODE): Ditto.
-
-2023-11-20 xuli <xuli1@eswincomputing.com>
-
- PR target/112537
- * config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum): Strategy enum.
- * config/riscv/riscv-string.cc (riscv_expand_block_move): Disabled based on options.
- (expand_block_move): Ditto.
- * config/riscv/riscv.opt: Add -mmemcpy-strategy=.
-
-2023-11-20 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/gnu-user.h (MUSL_ABI_SPEC): Modify suffix.
-
-2023-11-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Optimize constant AVL.
-
-2023-11-19 Philipp Tomsich <philipp.tomsich@vrull.eu>
-
- * config/riscv/riscv-protos.h (extract_base_offset_in_addr): Prototype.
- * config/riscv/riscv.cc (riscv_fusion_pairs): New enum.
- (riscv_tune_param): Add fusible_ops field.
- (riscv_tune_param_rocket_tune_info): Initialize new field.
- (riscv_tune_param_sifive_7_tune_info): Likewise.
- (thead_c906_tune_info): Likewise.
- (generic_oo_tune_info): Likewise.
- (optimize_size_tune_info): Likewise.
- (riscv_macro_fusion_p): New function.
- (riscv_fusion_enabled_p): Likewise.
- (riscv_macro_fusion_pair_p): Likewise.
- (TARGET_SCHED_MACRO_FUSION_P): Define.
- (TARGET_SCHED_MACRO_FUSION_PAIR_P): Likewise.
- (extract_base_offset_in_addr): Moved into riscv.cc from...
- * config/riscv/thead.cc: Here.
- Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
- Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
-
-2023-11-19 Jeff Law <jlaw@ventanamicro.com>
-
- * config/c6x/c6x.md (mvilc): Add mode to UNSPEC source.
- * config/mips/mips.md (rdhwr_synci_step_<mode>): Likewise.
- * config/riscv/riscv.md (riscv_frcsr, riscv_frflags): Likewise.
- * config/s390/s390.md (@split_stack_call<mode>): Likewise.
- (@split_stack_cond_call<mode>): Likewise.
- * config/sh/sh.md (sp_switch_1): Likewise.
-
-2023-11-19 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.h: Include "rich-location.h".
- * edit-context.h (class fixit_hint): New forward decl.
- * gcc-rich-location.h: Include "rich-location.h".
- * genmatch.cc: Likewise.
- * pretty-print.h: Likewise.
-
-2023-11-19 David Malcolm <dmalcolm@redhat.com>
-
- * Makefile.in (CPPLIB_H): Add libcpp/include/rich-location.h.
- * coretypes.h (class rich_location): New forward decl.
-
-2023-11-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (expand_tuple_move): Fix bug.
-
-2023-11-19 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/107573
- * doc/invoke.texi: Add -Wanalyzer-undefined-behavior-strtok.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/predicates.md (const_call_insn_operand):
- Remove buggy "HAVE_AS_SUPPORT_CALL36" conditions. Change "1" to
- "true" to make the coding style consistent.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/genopts/isa-evolution.in: (lam-bh, lamcas):
- Add.
- * config/loongarch/loongarch-str.h: Regenerate.
- * config/loongarch/loongarch.opt: Regenerate.
- * config/loongarch/loongarch-cpucfg-map.h: Regenerate.
- * config/loongarch/loongarch-cpu.cc
- (ISA_BASE_LA64V110_FEATURES): Include OPTION_MASK_ISA_LAM_BH
- and OPTION_MASK_ISA_LAMCAS.
- * config/loongarch/sync.md (atomic_add<mode:SHORT>): Use
- TARGET_LAM_BH instead of ISA_BASE_IS_LA64V110. Remove empty
- lines from assembly output.
- (atomic_exchange<mode>_short): Likewise.
- (atomic_exchange<mode:SHORT>): Likewise.
- (atomic_fetch_add<mode>_short): Likewise.
- (atomic_fetch_add<mode:SHORT>): Likewise.
- (atomic_cas_value_strong<mode>_amcas): Use TARGET_LAMCAS instead
- of ISA_BASE_IS_LA64V110.
- (atomic_compare_and_swap<mode>): Likewise.
- (atomic_compare_and_swap<mode:GPR>): Likewise.
- (atomic_compare_and_swap<mode:SHORT>): Likewise.
- * config/loongarch/loongarch.cc (loongarch_asm_code_end): Dump
- status if -mlam-bh and -mlamcas if -fverbose-asm.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.cc (loongarch_print_operand): Don't
- print dbar 0x700 if TARGET_LD_SEQ_SA.
- * config/loongarch/sync.md (atomic_load<mode>): Likewise.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (DIV): New mode iterator.
- (<optab:ANY_DIV><mode:GPR>3): Don't expand if TARGET_DIV32.
- (<optab:ANY_DIV>di3_fake): Disable if TARGET_DIV32.
- (*<optab:ANY_DIV><mode:GPR>3): Allow SImode if TARGET_DIV32.
- (<optab:ANY_DIV>si3_extended): New insn if TARGET_DIV32.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-def.h:
- (loongarch_isa_base_features): Declare. Define it in ...
- * config/loongarch/loongarch-cpu.cc
- (loongarch_isa_base_features): ... here.
- (fill_native_cpu_config): If we know the base ISA of the CPU
- model from PRID, use it instead of la64 (v1.0). Check if all
- expected features of this base ISA is available, emit a warning
- if not.
- * config/loongarch/loongarch-opts.cc (config_target_isa): Enable
- the features implied by the base ISA if not -march=native.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/genopts/isa-evolution.in: New data file.
- * config/loongarch/genopts/genstr.sh: Translate info in
- isa-evolution.in when generating loongarch-str.h, loongarch.opt,
- and loongarch-cpucfg-map.h.
- * config/loongarch/genopts/loongarch.opt.in (isa_evolution):
- New variable.
- * config/loongarch/t-loongarch: (loongarch-cpucfg-map.h): New
- rule.
- (loongarch-str.h): Depend on isa-evolution.in.
- (loongarch.opt): Depend on isa-evolution.in.
- (loongarch-cpu.o): Depend on loongarch-cpucfg-map.h.
- * config/loongarch/loongarch-str.h: Regenerate.
- * config/loongarch/loongarch-def.h (loongarch_isa): Add field
- for evolution features. Add helper function to enable features
- in this field.
- Probe native CPU capability and save the corresponding options
- into preset.
- * config/loongarch/loongarch-cpu.cc (fill_native_cpu_config):
- Probe native CPU capability and save the corresponding options
- into preset.
- (cache_cpucfg): Simplify with C++11-style for loop.
- (cpucfg_useful_idx, N_CPUCFG_WORDS): Move to ...
- * config/loongarch/loongarch.cc
- (loongarch_option_override_internal): Enable the ISA evolution
- feature options implied by -march and not explicitly disabled.
- (loongarch_asm_code_end): New function, print ISA information as
- comments in the assembly if -fverbose-asm. It makes easier to
- debug things like -march=native.
- (TARGET_ASM_CODE_END): Define.
- * config/loongarch/loongarch.opt: Regenerate.
- * config/loongarch/loongarch-cpucfg-map.h: Generate.
- (cpucfg_useful_idx, N_CPUCFG_WORDS) ... here.
-
-2023-11-18 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/genopts/loongarch-strings:
- (STR_ISA_BASE_LA64V110): Add.
- * config/loongarch/genopts/loongarch.opt.in:
- (ISA_BASE_LA64V110): Add.
- * config/loongarch/loongarch-def.c
- (loongarch_isa_base_strings): Initialize [ISA_BASE_LA64V110]
- to STR_ISA_BASE_LA64V110.
- * config/loongarch/loongarch.opt: Regenerate.
- * config/loongarch/loongarch-str.h: Regenerate.
-
-2023-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * doc/invoke.texi (-fprofile-update): Clarify default method. Document
- the atomic method behaviour.
- * tree-profile.cc (enum counter_update_method): New.
- (counter_update): Likewise.
- (gen_counter_update): Use counter_update_method. Split the
- atomic counter update in two 32-bit atomic operations if
- necessary.
- (tree_profiling): Select counter_update_method.
-
-2023-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * tree-profile.cc (gen_assign_counter_update): New.
- (gen_counter_update): Likewise.
- (gimple_gen_edge_profiler): Use gen_counter_update().
- (gimple_gen_time_profiler): Likewise.
-
-2023-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * config/rtems.h (TARGET_HAVE_LIBATOMIC): Define.
- * doc/tm.texi: Regenerate.
- * doc/tm.texi.in (TARGET_HAVE_LIBATOMIC): Add.
- * target.def (have_libatomic): New.
-
-2023-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- Revert:
- 2023-11-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
-
- * config/sparc/rtemself.h (SPARC_GCOV_TYPE_SIZE): Define.
- * config/sparc/sparc.c (sparc_gcov_type_size): New.
- (TARGET_GCOV_TYPE_SIZE): Redefine if SPARC_GCOV_TYPE_SIZE is defined.
- * coverage.c (get_gcov_type): Use targetm.gcov_type_size().
- * doc/tm.texi (TARGET_GCOV_TYPE_SIZE): Add hook under "Misc".
- * doc/tm.texi.in: Regenerate.
- * target.def (gcov_type_size): New target hook.
- * targhooks.c (default_gcov_type_size): New.
- * targhooks.h (default_gcov_type_size): Declare.
- * tree-profile.c (gimple_gen_edge_profiler): Use precision of
- gcov_type_node.
- (gimple_gen_time_profiler): Likewise.
-
-2023-11-18 Kito Cheng <kito.cheng@sifive.com>
-
- * config/riscv/riscv-target-attr.cc
- (riscv_target_attr_parser::parse_arch): Use char[] for
- std::unique_ptr to prevent mismatched new delete issue.
- (riscv_process_one_target_attr): Ditto.
- (riscv_process_target_attr): Ditto.
-
-2023-11-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector-iterators.md: Refactor iterators.
-
-2023-11-18 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/sync.md (atomic_load<mode>): New template.
-
-2023-11-18 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/loongarch-def.h: Add comments.
- * config/loongarch/loongarch-opts.h (ISA_BASE_IS_LA64V110): Define macro.
- * config/loongarch/loongarch.cc (loongarch_memmodel_needs_rel_acq_fence):
- Remove redundant code implementations.
- * config/loongarch/sync.md (d): Added QI, HI support.
- (atomic_add<mode>): New template.
- (atomic_exchange<mode>_short): Likewise.
- (atomic_cas_value_strong<mode>_amcas): Likewise..
- (atomic_fetch_add<mode>_short): Likewise.
-
-2023-11-18 Lulu Cheng <chenglulu@loongson.cn>
-
- * config.gcc: Support LA664.
- * config/loongarch/genopts/loongarch-strings: Likewise.
- * config/loongarch/genopts/loongarch.opt.in: Likewise.
- * config/loongarch/loongarch-cpu.cc (fill_native_cpu_config): Likewise.
- * config/loongarch/loongarch-def.c: Likewise.
- * config/loongarch/loongarch-def.h (N_ISA_BASE_TYPES): Likewise.
- (ISA_BASE_LA64V110): Define macro.
- (N_ARCH_TYPES): Update value.
- (N_TUNE_TYPES): Update value.
- (CPU_LA664): New macro.
- * config/loongarch/loongarch-opts.cc (isa_default_abi): Likewise.
- (isa_base_compat_p): Likewise.
- * config/loongarch/loongarch-opts.h (TARGET_64BIT): This parameter is enabled
- when la_target.isa.base is equal to ISA_BASE_LA64V100 or ISA_BASE_LA64V110.
- (TARGET_uARCH_LA664): Define macro.
- * config/loongarch/loongarch-str.h (STR_CPU_LA664): Likewise.
- * config/loongarch/loongarch.cc (loongarch_cpu_sched_reassociation_width):
- Add LA664 support.
- * config/loongarch/loongarch.opt: Regenerate.
-
-2023-11-18 Lulu Cheng <chenglulu@loongson.cn>
- Xi Ruoyao <xry111@xry111.site>
-
- * config.in: Regenerate.
- * config/loongarch/loongarch-opts.h (HAVE_AS_SUPPORT_CALL36): Define macro.
- * config/loongarch/loongarch.cc (loongarch_legitimize_call_address):
- If binutils supports call36, the function call is not split over expand.
- * config/loongarch/loongarch.md: Add call36 generation code.
- * config/loongarch/predicates.md: Likewise.
- * configure: Regenerate.
- * configure.ac: Check whether binutils supports call36.
-
-2023-11-18 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/106147
- * Makefile.in (ANALYZER_OBJS): Add analyzer/infinite-loop.o.
- * doc/invoke.texi: Add -fdump-analyzer-infinite-loop and
- -Wanalyzer-infinite-loop. Add missing CWE link for
- -Wanalyzer-infinite-recursion.
- * timevar.def (TV_ANALYZER_INFINITE_LOOPS): New.
-
-2023-11-17 Robin Dapp <rdapp@ventanamicro.com>
-
- PR middle-end/112406
- PR middle-end/112552
- * tree-vect-loop.cc (vect_transform_reduction): Pass truth
- vectype for mask operand.
-
-2023-11-17 Jakub Jelinek <jakub@redhat.com>
-
- PR c++/107571
- * gimplify.cc (expand_FALLTHROUGH_r): Use wi->removed_stmt after
- gsi_remove, change the way of passing fallthrough stmt at the end
- of sequence to expand_FALLTHROUGH. Diagnose IFN_FALLTHROUGH
- with GF_CALL_NOTHROW flag.
- (expand_FALLTHROUGH): Change loc into array of 2 location_t elts,
- don't test wi.callback_result, instead check whether first
- elt is not UNKNOWN_LOCATION and in that case pedwarn with the
- second location.
- * gimple-walk.cc (walk_gimple_seq_mod): Clear wi->removed_stmt
- after the flag has been used.
- * internal-fn.def (FALLTHROUGH): Mention in comment the special
- meaning of the TREE_NOTHROW/GF_CALL_NOTHROW flag on the calls.
-
-2023-11-17 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112566
- PR tree-optimization/83171
- * match.pd (ctz(ext(X)) -> ctz(X), popcount(zext(X)) -> popcount(X),
- parity(ext(X)) -> parity(X), ffs(ext(X)) -> ffs(X)): New
- simplifications.
- ( __builtin_ffs (X) == 0 -> X == 0): Use FFS rather than
- BUILT_IN_FFS BUILT_IN_FFSL BUILT_IN_FFSLL BUILT_IN_FFSIMAX.
-
-2023-11-17 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112374
- * tree-vect-loop.cc (check_reduction_path): Perform the cond_fn_p
- special case only if op_use_stmt == use_stmt, use as_a rather than
- dyn_cast in that case.
-
-2023-11-17 Richard Biener <rguenther@suse.de>
-
- Revert:
- 2023-11-14 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112281
- * tree-loop-distribution.cc (pg_add_dependence_edges):
- Preserve stmt order when the innermost loop has exact
- overlap.
-
-2023-11-17 Georg-Johann Lay <avr@gjlay.de>
-
- PR target/53372
- * config/avr/avr.cc (avr_asm_named_section) [AVR_SECTION_PROGMEM]:
- Only return some .progmem*.data section if the user did not
- specify a section attribute.
- (avr_section_type_flags) [avr_progmem_p]: Unset SECTION_NOTYPE
- in returned section flags.
-
-2023-11-17 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/lsx.md (copysign<mode>3): Allow operand[2] to
- be an reg_or_vector_same_val_operand. If it's a const vector
- with same negative elements, expand the copysign with a bitset
- instruction. Otherwise, force it into an register.
- * config/loongarch/lasx.md (copysign<mode>3): Likewise.
-
-2023-11-17 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/111449
- * config/rs6000/vsx.md (*vsx_le_mem_to_mem_mov_ti): New.
-
-2023-11-17 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/111449
- * config/rs6000/altivec.md (cbranchv16qi4): New expand pattern.
- * config/rs6000/rs6000.cc (rs6000_generate_compare): Generate
- insn sequence for V16QImode equality compare.
- * config/rs6000/rs6000.h (MOVE_MAX_PIECES): Define.
- (STORE_MAX_PIECES): Define.
-
-2023-11-17 Li Wei <liwei@loongson.cn>
-
- * config/loongarch/loongarch.h (CLZ_DEFINED_VALUE_AT_ZERO):
- Implement.
- (CTZ_DEFINED_VALUE_AT_ZERO): Same.
-
-2023-11-17 Richard Biener <rguenther@suse.de>
-
- * dwarf2out.cc (add_AT_die_ref): Assert we do not add
- a self-ref DW_AT_abstract_origin or DW_AT_specification.
-
-2023-11-17 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/loongarch.cc
- (loongarch_builtin_vectorization_cost): Adjust.
-
-2023-11-16 Andrew Pinski <pinskia@gmail.com>
-
- PR rtl-optimization/112483
- * simplify-rtx.cc (simplify_binary_operation_1) <case COPYSIGN>:
- Call simplify_unary_operation for NEG instead of
- simplify_gen_unary.
-
-2023-11-16 Edwin Lu <ewlu@rivosinc.com>
-
- PR target/111557
- * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): update macro name
-
-2023-11-16 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/78904
- * config/i386/i386.md (*addqi_ext2<mode>_0):
- New define_insn_and_split pattern.
- (*subqi_ext2<mode>_0): Ditto.
- (*<code>qi_ext2<mode>_0): Ditto.
-
-2023-11-16 John David Anglin <danglin@gcc.gnu.org>
-
- PR rtl-optimization/112415
- * config/pa/pa.cc (pa_legitimate_address_p): Allow 14-bit
- displacements before reload. Simplify logic flow. Revise
- comments.
- * config/pa/pa.h (TARGET_ELF64): New define.
- (INT14_OK_STRICT): Update define and comment.
- * config/pa/pa64-linux.h (TARGET_ELF64): Define.
- * config/pa/predicates.md (base14_operand): Don't check
- alignment of short displacements.
- (integer_store_memory_operand): Don't return true when
- reload_in_progress is true. Remove INT_5_BITS check.
- (floating_point_store_memory_operand): Don't return true when
- reload_in_progress is true. Use INT14_OK_STRICT to check
- whether long displacements are always okay.
-
-2023-11-16 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112567
- * config/i386/i386.md (*<any_logic:code>qi_ext<mode>_1_slp):
- Fix generation of invalid RTX in split pattern.
-
-2023-11-16 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_context::set_option_hooks): Add
- "lang_mask" param.
- * diagnostic.h (diagnostic_context::option_enabled_p): Update for
- move of m_lang_mask.
- (diagnostic_context::set_option_hooks): Add "lang_mask" param.
- (diagnostic_context::get_lang_mask): New.
- (diagnostic_context::m_lang_mask): Move into m_option_callbacks,
- thus making private.
- * lto-wrapper.cc (main): Update for new lang_mask param of
- set_option_hooks.
- * toplev.cc (init_asm_output): Use get_lang_mask.
- (general_init): Move initialization of global_dc's lang_mask to
- new lang_mask param of set_option_hooks.
-
-2023-11-16 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/111878
- * tree-vect-loop-manip.cc (find_loop_location): Skip edges check if
- latch incorrect.
-
-2023-11-16 Kito Cheng <kito.cheng@sifive.com>
-
- * config.gcc (riscv): Add riscv-target-attr.o.
- * config/riscv/riscv-protos.h (riscv_declare_function_size) New.
- (riscv_option_valid_attribute_p): New.
- (riscv_override_options_internal): New.
- (struct riscv_tune_info): New.
- (riscv_parse_tune): New.
- * config/riscv/riscv-target-attr.cc
- (class riscv_target_attr_parser): New.
- (struct riscv_attribute_info): New.
- (riscv_attributes): New.
- (riscv_target_attr_parser::parse_arch): New.
- (riscv_target_attr_parser::handle_arch): New.
- (riscv_target_attr_parser::handle_cpu): New.
- (riscv_target_attr_parser::handle_tune): New.
- (riscv_target_attr_parser::update_settings): New.
- (riscv_process_one_target_attr): New.
- (num_occurences_in_str): New.
- (riscv_process_target_attr): New.
- (riscv_option_valid_attribute_p): New.
- * config/riscv/riscv.cc: Include target-globals.h and
- riscv-subset.h.
- (struct riscv_tune_info): Move to riscv-protos.h.
- (get_tune_str): New.
- (riscv_parse_tune): New parameter null_p.
- (riscv_declare_function_size): New.
- (riscv_option_override): Build target_option_default_node and
- target_option_current_node.
- (riscv_save_restore_target_globals): New.
- (riscv_option_restore): New.
- (riscv_previous_fndecl): New.
- (riscv_set_current_function): Apply the target attribute.
- (TARGET_OPTION_RESTORE): Define.
- (TARGET_OPTION_VALID_ATTRIBUTE_P): Ditto.
- * config/riscv/riscv.h (SWITCHABLE_TARGET): Define to 1.
- (ASM_DECLARE_FUNCTION_SIZE) Define.
- * config/riscv/riscv.opt (mtune=): Add Save attribute.
- (mcpu=): Ditto.
- (mcmodel=): Ditto.
- * config/riscv/t-riscv: Add build rule for riscv-target-attr.o
- * doc/extend.texi: Add doc for target attribute.
-
-2023-11-16 Kito Cheng <kito.cheng@sifive.com>
-
- PR target/112478
- * config/riscv/riscv.cc (riscv_save_return_addr_reg_p): Check ra
- is ever lived.
-
-2023-11-16 liuhongt <hongtao.liu@intel.com>
-
- PR target/112532
- * config/i386/mmx.md (*vec_dup<mode>): Extend for V4HI and
- V2HI.
-
-2023-11-16 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112526
- * config/i386/i386.md
- (mov imm,%rax; mov %rdi,%rdx; mulx %rax -> mov imm,%rdx; mulx %rdi):
- Verify in define_peephole2 that operands[2] dies or is overwritten
- at the end of multiplication.
-
-2023-11-16 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/112536
- * tree-vect-slp.cc (arg0_map): New variable.
- (vect_get_operand_map): For IFN_CLZ or IFN_CTZ, return arg0_map.
-
-2023-11-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR middle-end/112554
- * tree-vect-loop.cc (vect_determine_partial_vectors_and_peeling):
- Clear SELECT_VL_P for non-partial vectorization.
-
-2023-11-16 Hongyu Wang <hongyu.wang@intel.com>
-
- * config/i386/sse.md (vec_extract_hi_<mode>): Add noavx512vl
- alternative with attr addr gpr16 and "jm" constraint.
- (vec_extract_hi_<mode>): Likewise for SF vector modes.
- (@vec_extract_hi_<mode>): Likewise.
- (*vec_extractv2ti): Likewise.
- (vec_set_hi_<mode><mask_name>): Likewise.
- * config/i386/mmx.md (@sse4_1_insertps_<mode>): Correct gpr16 attr for
- each alternative.
-
-2023-11-15 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/78904
- * config/i386/i386.md (*movstrictqi_ext<mode>_1): New insn pattern.
- (*addqi_ext<mode>_2_slp): New define_insn_and_split pattern.
- (*subqi_ext<mode>_2_slp): Ditto.
- (*<any_logic:code>qi_ext<mode>_2_slp): Ditto.
-
-2023-11-15 Patrick O'Neill <patrick@rivosinc.com>
-
- * common/config/riscv/riscv-common.cc
- (riscv_subset_list::parse_std_ext): Emit an error and skip to
- the next extension when a non-canonical ordering is detected.
-
-2023-11-15 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
-
- * gcc-rich-location.cc (maybe_range_label_for_tree_type_mismatch::get_text):
- Revert using the macro CAN_HAVE_LOCATION_P.
-
-2023-11-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112447
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Insert
- local vsetvl info before LCM suggested one.
- Tested-by: Patrick O'Neill <patrick@rivosinc.com> # pre-commit-CI #679
- Co-developed-by: Vineet Gupta <vineetg@rivosinc.com>
-
-2023-11-15 Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/riscv.cc (riscv_sign_extend_if_not_subreg_prom): New.
- * (riscv_extend_comparands): Call New function on operands.
-
-2023-11-15 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (*addqi_ext<mode>_1_slp):
- Add "&& " before "reload_completed" in split condition.
- (*subqi_ext<mode>_1_slp): Ditto.
- (*<any_logic:code>qi_ext<mode>_1_slp): Ditto.
-
-2023-11-15 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112540
- * config/i386/i386.md (*addqi_ext<mode>_1_slp):
- Correct operand numbers in split pattern. Replace !Q constraint
- of operand 1 with !qm. Add insn constrain.
- (*subqi_ext<mode>_1_slp): Ditto.
- (*<any_logic:code>qi_ext<mode>_1_slp): Ditto.
-
-2023-11-15 Thomas Schwinge <thomas@codesourcery.com>
-
- * doc/extend.texi (Nvidia PTX Built-in Functions): Fix
- copy'n'paste-o in '__builtin_nvptx_brev' description.
-
-2023-11-15 Roger Sayle <roger@nextmovesoftware.com>
- Thomas Schwinge <thomas@codesourcery.com>
-
- * config/nvptx/nvptx.md (UNSPEC_BITREV): Delete.
- (bitrev<mode>2): Represent using bitreverse.
-
-2023-11-15 Andrew Stubbs <ams@codesourcery.com>
- Andrew Jenner <andrew@codesourcery.com>
-
- * config/gcn/constraints.md: Add "a" AVGPR constraint.
- * config/gcn/gcn-valu.md (*mov<mode>): Add AVGPR alternatives.
- (*mov<mode>_4reg): Likewise.
- (@mov<mode>_sgprbase): Likewise.
- (gather<mode>_insn_1offset<exec>): Likewise.
- (gather<mode>_insn_1offset_ds<exec>): Likewise.
- (gather<mode>_insn_2offsets<exec>): Likewise.
- (scatter<mode>_expr<exec_scatter>): Likewise.
- (scatter<mode>_insn_1offset_ds<exec_scatter>): Likewise.
- (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
- * config/gcn/gcn.cc (MAX_NORMAL_AVGPR_COUNT): Define.
- (gcn_class_max_nregs): Handle AVGPR_REGS and ALL_VGPR_REGS.
- (gcn_hard_regno_mode_ok): Likewise.
- (gcn_regno_reg_class): Likewise.
- (gcn_spill_class): Allow spilling to AVGPRs on TARGET_CDNA1_PLUS.
- (gcn_sgpr_move_p): Handle AVGPRs.
- (gcn_secondary_reload): Reload AVGPRs via VGPRs.
- (gcn_conditional_register_usage): Handle AVGPRs.
- (gcn_vgpr_equivalent_register_operand): New function.
- (gcn_valid_move_p): Check for validity of AVGPR moves.
- (gcn_compute_frame_offsets): Handle AVGPRs.
- (gcn_memory_move_cost): Likewise.
- (gcn_register_move_cost): Likewise.
- (gcn_vmem_insn_p): Handle TYPE_VOP3P_MAI.
- (gcn_md_reorg): Handle AVGPRs.
- (gcn_hsa_declare_function_name): Likewise.
- (print_reg): Likewise.
- (gcn_dwarf_register_number): Likewise.
- * config/gcn/gcn.h (FIRST_AVGPR_REG): Define.
- (AVGPR_REGNO): Define.
- (LAST_AVGPR_REG): Define.
- (SOFT_ARG_REG): Update.
- (FRAME_POINTER_REGNUM): Update.
- (DWARF_LINK_REGISTER): Update.
- (FIRST_PSEUDO_REGISTER): Update.
- (AVGPR_REGNO_P): Define.
- (enum reg_class): Add AVGPR_REGS and ALL_VGPR_REGS.
- (REG_CLASS_CONTENTS): Add new register classes and add entries for
- AVGPRs to all classes.
- (REGISTER_NAMES): Add AVGPRs.
- * config/gcn/gcn.md (FIRST_AVGPR_REG, LAST_AVGPR_REG): Define.
- (AP_REGNUM, FP_REGNUM): Update.
- (define_attr "type"): Add vop3p_mai.
- (define_attr "unit"): Handle vop3p_mai.
- (define_attr "gcn_version"): Add "cdna2".
- (define_attr "enabled"): Handle cdna2.
- (*mov<mode>_insn): Add AVGPR alternatives.
- (*movti_insn): Likewise.
- * config/gcn/mkoffload.cc (isa_has_combined_avgprs): New.
- (process_asm): Process avgpr_count.
- * config/gcn/predicates.md (gcn_avgpr_register_operand): New.
- (gcn_avgpr_hard_register_operand): New.
- * doc/md.texi: Document the "a" constraint.
-
-2023-11-15 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-valu.md (mov<mode>_sgprbase): Add @ modifier.
- (reload_in<mode>): Delete.
- (reload_out<mode>): Delete.
- * config/gcn/gcn.cc (CODE_FOR): Delete.
- (get_code_for_##PREFIX##vN##SUFFIX): Delete.
- (CODE_FOR_OP): Delete.
- (get_code_for_##PREFIX): Delete.
- (gcn_secondary_reload): Replace "get_code_for" with "code_for".
-
-2023-11-15 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/t-s390: Generate s390-gen-builtins.h without
- linemarkers.
-
-2023-11-15 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112282
- * tree-if-conv.cc (ifcvt_hoist_invariants): Only hoist from
- the loop header.
-
-2023-11-15 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (vect_slp_region): Also clear visited flag when
- we skipped an instance due to -fdbg-cnt.
-
-2023-11-15 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.cc
- (loongarch_memmodel_needs_release_fence): Remove.
- (loongarch_cas_failure_memorder_needs_acquire): New static
- function.
- (loongarch_print_operand): Redefine 'G' for the barrier on CAS
- failure.
- * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
- Remove the redundant barrier before the LL instruction, and
- emit an acquire barrier on failure if needed by
- failure_memorder.
- (atomic_cas_value_cmp_and_7_<mode>): Likewise.
- (atomic_cas_value_add_7_<mode>): Remove the unnecessary barrier
- before the LL instruction.
- (atomic_cas_value_sub_7_<mode>): Likewise.
- (atomic_cas_value_and_7_<mode>): Likewise.
- (atomic_cas_value_xor_7_<mode>): Likewise.
- (atomic_cas_value_or_7_<mode>): Likewise.
- (atomic_cas_value_nand_7_<mode>): Likewise.
- (atomic_cas_value_exchange_7_<mode>): Likewise.
-
-2023-11-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc (expand_vector_init_trailing_same_elem): New function.
- (expand_vec_init): Add trailing optimization.
-
-2023-11-15 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (rvv_builder::get_merge_scalar_mask):
- Add inner_mode mask arg for mask int mode.
- (get_repeating_sequence_dup_machine_mode): Add mask_bit_mode arg
- to get the good enough vector int mode on precision.
- (expand_vector_init_merge_repeating_sequence): Pass required args
- to above func.
-
-2023-11-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112535
- * config/riscv/riscv.cc (riscv_legitimate_address_p): Disallow RVV modes base address.
-
-2023-11-15 David Malcolm <dmalcolm@redhat.com>
-
- * json.cc (selftest::assert_print_eq): Add "loc" param and use
- ASSERT_STREQ_AT.
- (ASSERT_PRINT_EQ): New macro.
- (selftest::test_writing_objects): Use ASSERT_PRINT_EQ to capture
- source location of assertion.
- (selftest::test_writing_arrays): Likewise.
- (selftest::test_writing_float_numbers): Likewise.
- (selftest::test_writing_integer_numbers): Likewise.
- (selftest::test_writing_strings): Likewise.
- (selftest::test_writing_literals): Likewise.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- PR analyzer/103533
- * doc/invoke.texi (Static Analyzer Options): Add the six
- -Wanalyzer-tainted-* warnings. Update documentation of each
- warning to reflect removed requirement to use
- -fanalyzer-checker=taint. Remove discussion of
- -fanalyzer-checker=taint.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-format-json.cc
- (json_output_format::on_end_diagnostic): Update calls to m_context
- callbacks to use member functions; tighten up scopes.
- * diagnostic-format-sarif.cc (sarif_builder::make_result_object):
- Likewise.
- (sarif_builder::make_reporting_descriptor_object_for_warning):
- Likewise.
- * diagnostic.cc (diagnostic_context::initialize): Update for
- callbacks being moved into m_option_callbacks and being renamed.
- (diagnostic_context::set_option_hooks): New.
- (diagnostic_option_classifier::classify_diagnostic): Update call
- to global_dc->m_option_enabled to use option_enabled_p.
- (diagnostic_context::print_option_information): Update calls to
- m_context callbacks to use member functions; tighten up scopes.
- (diagnostic_context::diagnostic_enabled): Likewise.
- * diagnostic.h (diagnostic_option_enabled_cb): New typedef.
- (diagnostic_make_option_name_cb): New typedef.
- (diagnostic_make_option_url_cb): New typedef.
- (diagnostic_context::option_enabled_p): New.
- (diagnostic_context::make_option_name): New.
- (diagnostic_context::make_option_url): New.
- (diagnostic_context::set_option_hooks): New decl.
- (diagnostic_context::m_option_enabled): Rename to
- m_option_enabled_cb and move within m_option_callbacks, using
- typedef.
- (diagnostic_context::m_option_state): Move within
- m_option_callbacks.
- (diagnostic_context::m_option_name): Rename to
- m_make_option_name_cb and move within m_option_callbacks, using
- typedef.
- (diagnostic_context::m_get_option_url): Likewise, renaming to
- m_make_option_url_cb.
- * lto-wrapper.cc (print_lto_docs_link): Update call to m_context
- callback to use member function.
- (main): Use diagnostic_context::set_option_hooks.
- * opts-diagnostic.h (option_name): Make context param const.
- (get_option_url): Likewise.
- * opts.cc (option_name): Likewise.
- (get_option_url): Likewise.
- * toplev.cc (general_init): Use
- diagnostic_context::set_option_hooks.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * selftest-diagnostic.cc
- (test_diagnostic_context::test_diagnostic_context): Use
- diagnostic_start_span.
- * tree-diagnostic-path.cc (struct event_range): Likewise.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-show-locus.cc (diagnostic_context::show_locus):
- Update for renaming of text callbacks fields.
- * diagnostic.cc (diagnostic_context::initialize): Likewise.
- * diagnostic.h (class diagnostic_context): Add "friend" for
- accessors to m_text_callbacks.
- (diagnostic_context::m_text_callbacks): Make private, and add an
- "m_" prefix to field names.
- (diagnostic_starter): Convert from macro to inline function.
- (diagnostic_start_span): New.
- (diagnostic_finalizer): Convert from macro to inline function.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.h (diagnostic_ready_p): Convert from macro to inline
- function.
-
-2023-11-14 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/78904
- * config/i386/i386.md (*addqi_ext<mode>_1_slp):
- New define_insn_and_split pattern.
- (*subqi_ext<mode>_1_slp): Ditto.
- (*<any_logic:code>qi_ext<mode>_1_slp): Ditto.
-
-2023-11-14 Andrew Stubbs <ams@codesourcery.com>
-
- PR target/112481
- * expr.cc (store_constructor): Use OPTAB_WIDEN for mask adjustment.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-format-sarif.cc (sarif_builder::get_sarif_column):
- Use m_context's file_cache.
- (sarif_builder::maybe_make_artifact_content_object): Likewise.
- (sarif_builder::get_source_lines): Likewise.
- * diagnostic-show-locus.cc
- (exploc_with_display_col::exploc_with_display_col): Add file_cache
- param.
- (layout::m_file_cache): New field.
- (make_range): Add file_cache param.
- (selftest::test_layout_range_for_single_point): Create and use a
- temporary file_cache.
- (selftest::test_layout_range_for_single_line): Likewise.
- (selftest::test_layout_range_for_multiple_lines): Likewise.
- (layout::layout): Initialize m_file_cache from the context and use it.
- (layout::maybe_add_location_range): Use m_file_cache.
- (layout::calculate_x_offset_display): Likewise.
- (get_affected_range): Add file_cache param.
- (get_printed_columns): Likewise.
- (line_corrections::line_corrections): Likewwise.
- (line_corrections::m_file_cache): New field.
- (source_line::source_line): Add file_cache param.
- (line_corrections::add_hint): Use m_file_cache.
- (layout::print_trailing_fixits): Likewise.
- (layout::print_line): Likewise.
- (selftest::test_layout_x_offset_display_utf8): Create and use a
- temporary file_cache.
- (selftest::test_layout_x_offset_display_tab): Likewise.
- (selftest::test_diagnostic_show_locus_one_liner_utf8): Likewise.
- (selftest::test_add_location_if_nearby): Pass global_dc's
- file_cache to temp_source_file ctor.
- (selftest::test_overlapped_fixit_printing): Create and use a
- temporary file_cache.
- (selftest::test_overlapped_fixit_printing_utf8): Likewise.
- (selftest::test_overlapped_fixit_printing_2): Use dc's file_cache.
- * diagnostic.cc (diagnostic_context::initialize): Always create a
- file_cache.
- (diagnostic_context::initialize_input_context): Assume
- m_file_cache has already been created.
- (diagnostic_context::create_edit_context): Pass m_file_cache to
- edit_context.
- (convert_column_unit): Add file_cache param.
- (diagnostic_context::converted_column): Use context's file_cache.
- (print_parseable_fixits): Add file_cache param.
- (diagnostic_context::report_diagnostic): Use context's file_cache.
- (selftest::test_print_parseable_fixits_none): Create and use a
- temporary file_cache.
- (selftest::test_print_parseable_fixits_insert): Likewise.
- (selftest::test_print_parseable_fixits_remove): Likewise.
- (selftest::test_print_parseable_fixits_replace): Likewise.
- (selftest::test_print_parseable_fixits_bytes_vs_display_columns):
- Likewise.
- * diagnostic.h (diagnostic_context::file_cache_init): Delete.
- (diagnostic_context::get_file_cache): Convert return type from
- pointer to reference.
- * edit-context.cc (edited_file::get_file_cache): New.
- (edited_file::m_edit_context): New.
- (edit_context::edit_context): Add file_cache param.
- (edit_context::get_or_insert_file): Pass this to edited_file's
- ctor.
- (edited_file::edited_file): Add edit_context param.
- (edited_file::print_content): Use get_file_cache.
- (edited_file::print_diff_hunk): Likewise.
- (edited_file::print_run_of_changed_lines): Likewise.
- (edited_file::get_or_insert_line): Likewise.
- (edited_file::get_num_lines): Likewise.
- (edited_line::edited_line): Pass in file_cache and use it.
- (selftest::test_get_content): Create and use a
- temporary file_cache.
- (selftest::test_applying_fixits_insert_before): Likewise.
- (selftest::test_applying_fixits_insert_after): Likewise.
- (selftest::test_applying_fixits_insert_after_at_line_end):
- Likewise.
- (selftest::test_applying_fixits_insert_after_failure): Likewise.
- (selftest::test_applying_fixits_insert_containing_newline):
- Likewise.
- (selftest::test_applying_fixits_growing_replace): Likewise.
- (selftest::test_applying_fixits_shrinking_replace): Likewise.
- (selftest::test_applying_fixits_replace_containing_newline):
- Likewise.
- (selftest::test_applying_fixits_remove): Likewise.
- (selftest::test_applying_fixits_multiple): Likewise.
- (selftest::test_applying_fixits_multiple_lines): Likewise.
- (selftest::test_applying_fixits_modernize_named_init): Likewise.
- (selftest::test_applying_fixits_modernize_named_init): Likewise.
- (selftest::test_applying_fixits_unreadable_file): Likewise.
- (selftest::test_applying_fixits_line_out_of_range): Likewise.
- (selftest::test_applying_fixits_column_validation): Likewise.
- (selftest::test_applying_fixits_column_validation): Likewise.
- (selftest::test_applying_fixits_column_validation): Likewise.
- (selftest::test_applying_fixits_column_validation): Likewise.
- * edit-context.h (edit_context::edit_context): Add file_cache
- param.
- (edit_context::get_file_cache): New.
- (edit_context::m_file_cache): New.
- * final.cc: Include "diagnostic.h".
- (asm_show_source): Use global_dc's file_cache.
- * gcc-rich-location.cc (blank_line_before_p): Add file_cache
- param.
- (use_new_line): Likewise.
- (gcc_rich_location::add_fixit_insert_formatted): Use global dc's
- file_cache.
- * input.cc (diagnostic_file_cache_init): Delete.
- (diagnostic_context::file_cache_init): Delete.
- (diagnostics_file_cache_forcibly_evict_file): Delete.
- (file_cache::missing_trailing_newline_p): New.
- (file_cache::evicted_cache_tab_entry): Don't call
- diagnostic_file_cache_init.
- (location_get_source_line): Delete.
- (get_source_text_between): Add file_cache param.
- (get_source_file_content): Delete.
- (location_missing_trailing_newline): Delete.
- (location_compute_display_column): Add file_cache param.
- (dump_location_info): Create and use temporary file_cache.
- (get_substring_ranges_for_loc): Add file_cache param.
- (get_location_within_string): Likewise.
- (get_source_range_for_char): Likewise.
- (get_num_source_ranges_for_substring): Likewise.
- (selftest::test_reading_source_line): Create and use temporary
- file_cache.
- (selftest::lexer_test::m_file_cache): New field.
- (selftest::assert_char_at_range): Use test.m_file_cache.
- (selftest::assert_num_substring_ranges): Likewise.
- (selftest::assert_has_no_substring_ranges): Likewise.
- (selftest::test_lexer_string_locations_concatenation_2): Likewise.
- * input.h (class file_cache): New forward decl.
- (location_compute_display_column): Add file_cache param.
- (location_get_source_line): Delete.
- (get_source_text_between): Add file_cache param.
- (get_source_file_content): Delete.
- (location_missing_trailing_newline): Delete.
- (file_cache::missing_trailing_newline_p): New decl.
- (diagnostics_file_cache_forcibly_evict_file): Delete.
- * selftest.cc (named_temp_file::named_temp_file): Add file_cache
- param.
- (named_temp_file::~named_temp_file): Optionally evict the file
- from the given file_cache.
- (temp_source_file::temp_source_file): Add file_cache param.
- * selftest.h (class file_cache): New forward decl.
- (named_temp_file::named_temp_file): Add file_cache param.
- (named_temp_file::m_file_cache): New field.
- (temp_source_file::temp_source_file): Add file_cache param.
- * substring-locations.h (get_location_within_string): Add
- file_cache param.
-
-2023-11-14 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-format-json.cc: Use type-specific "set_*" functions
- of json::object to avoid naked new of json value subclasses.
- * diagnostic-format-sarif.cc: Likewise.
- * gcov.cc: Likewise.
- * json.cc (object::set_string): New.
- (object::set_integer): New.
- (object::set_float): New.
- (object::set_bool): New.
- (selftest::test_writing_objects): Use object::set_string.
- * json.h (object::set_string): New decl.
- (object::set_integer): New decl.
- (object::set_float): New decl.
- (object::set_bool): New decl.
- * optinfo-emit-json.cc: Use type-specific "set_*" functions of
- json::object to avoid naked new of json value subclasses.
- * timevar.cc: Likewise.
- * tree-diagnostic-path.cc: Likewise.
-
-2023-11-14 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/112509
- * tree-vrp.cc (find_case_label_range): Create range from case labels.
-
-2023-11-14 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390-builtin-types.def: Add/remove types.
- * config/s390/s390-builtins.def (s390_vec_scatter_element_flt):
- The type for the offset should be UV4SI instead of V4SF.
-
-2023-11-14 Saurabh Jha <saurabh.jha@arm.com>
-
- PR target/112337
- * config/arm/arm.cc (mve_vector_mem_operand): Add a REG_P check for INC
- and DEC operations.
-
-2023-11-14 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111233
- PR tree-optimization/111652
- PR tree-optimization/111727
- PR tree-optimization/111838
- PR tree-optimization/112113
- * tree-ssa-loop-split.cc (patch_loop_exit): Get the new
- guard code instead of the old guard stmt.
- (split_loop): Adjust.
-
-2023-11-14 Richard Biener <rguenther@suse.de>
-
- * tree-loop-distribution.cc (loop_distribution::data_dep_in_cycle_p):
- Consider all loops in the nest when looking for
- lambda_vector_zerop.
-
-2023-11-14 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112281
- * tree-loop-distribution.cc (pg_add_dependence_edges):
- Preserve stmt order when the innermost loop has exact
- overlap.
-
-2023-11-14 Jakub Jelinek <jakub@redhat.com>
-
- PR target/112523
- PR ada/112514
- * config/i386/i386.md (<insn><dwi>3_doubleword_lowpart): Move
- operands[1] aka low part of input rather than operands[3] aka high
- part of input to output if not the same register.
-
-2023-11-14 Andreas Krebbel <krebbel@linux.ibm.com>
-
- * config.gcc: Add s390-gen-builtins.h to target_gtfiles.
- * config/s390/s390-builtins.h (s390_builtin_types)
- (s390_builtin_fn_types, s390_builtin_decls): Add GTY marker.
- * config/s390/t-s390 (EXTRA_GTYPE_DEPS): Add s390-gen-builtins.h.
- Add build rule for s390-gen-builtins.h.
-
-2023-11-14 Andreas Krebbel <krebbel@linux.ibm.com>
-
- * config/s390/s390-c.cc (s390_fn_types_compatible): Add a check
- for error_mark_node.
-
-2023-11-14 Jakub Jelinek <jakub@redhat.com>
-
- PR c/111309
- * builtins.def (BUILT_IN_CLZG, BUILT_IN_CTZG, BUILT_IN_CLRSBG,
- BUILT_IN_FFSG, BUILT_IN_PARITYG, BUILT_IN_POPCOUNTG): New
- builtins.
- * builtins.cc (fold_builtin_bit_query): New function.
- (fold_builtin_1): Use it for
- BUILT_IN_{CLZ,CTZ,CLRSB,FFS,PARITY,POPCOUNT}G.
- (fold_builtin_2): Use it for BUILT_IN_{CLZ,CTZ}G.
- * fold-const-call.cc: Fix comment typo on tm.h inclusion.
- (fold_const_call_ss): Handle
- CFN_BUILT_IN_{CLZ,CTZ,CLRSB,FFS,PARITY,POPCOUNT}G.
- (fold_const_call_sss): New function.
- (fold_const_call_1): Call it for 2 argument functions returning
- scalar when passed 2 INTEGER_CSTs.
- * genmatch.cc (cmp_operand): For function calls also compare
- number of arguments.
- (fns_cmp): New function.
- (dt_node::gen_kids): Sort fns and generic_fns.
- (dt_node::gen_kids_1): Handle fns with the same id but different
- number of arguments.
- * match.pd (CLZ simplifications): Drop checks for defined behavior
- at zero. Add variant of simplifications for IFN_CLZ with 2 arguments.
- (CTZ simplifications): Drop checks for defined behavior at zero,
- don't optimize precisions above MAX_FIXED_MODE_SIZE. Add variant of
- simplifications for IFN_CTZ with 2 arguments.
- (a != 0 ? CLZ(a) : CST -> .CLZ(a)): Use TREE_TYPE (@3) instead of
- type, add BITINT_TYPE handling, create 2 argument IFN_CLZ rather than
- one argument. Add variant for matching CLZ with 2 arguments.
- (a != 0 ? CTZ(a) : CST -> .CTZ(a)): Similarly.
- * gimple-lower-bitint.cc (bitint_large_huge::lower_bit_query): New
- method.
- (bitint_large_huge::lower_call): Use it for IFN_{CLZ,CTZ,CLRSB,FFS}
- and IFN_{PARITY,POPCOUNT} calls.
- * gimple-range-op.cc (cfn_clz::fold_range): Don't check
- CLZ_DEFINED_VALUE_AT_ZERO for m_gimple_call_internal_p, instead
- assume defined value at zero if the call has 2 arguments and use
- second argument value for that case.
- (cfn_ctz::fold_range): Similarly.
- (gimple_range_op_handler::maybe_builtin_call): Use op_cfn_clz_internal
- or op_cfn_ctz_internal only if internal fn call has 2 arguments and
- set m_op2 in that case.
- * tree-vect-patterns.cc (vect_recog_ctz_ffs_pattern,
- vect_recog_popcount_clz_ctz_ffs_pattern): For value defined at zero
- use second argument of calls if present, otherwise assume UB at zero,
- create 2 argument .CLZ/.CTZ calls if needed.
- * tree-vect-stmts.cc (vectorizable_call): Handle 2 argument .CLZ/.CTZ
- calls.
- * tree-ssa-loop-niter.cc (build_cltz_expr): Create 2 argument
- .CLZ/.CTZ calls if needed.
- * tree-ssa-forwprop.cc (simplify_count_trailing_zeroes): Create 2
- argument .CTZ calls if needed.
- * tree-ssa-phiopt.cc (cond_removal_in_builtin_zero_pattern): Handle
- 2 argument .CLZ/.CTZ calls, handle BITINT_TYPE, create 2 argument
- .CLZ/.CTZ calls.
- * doc/extend.texi (__builtin_clzg, __builtin_ctzg, __builtin_clrsbg,
- __builtin_ffsg, __builtin_parityg, __builtin_popcountg): Document.
-
-2023-11-14 Xi Ruoyao <xry111@xry111.site>
-
- PR target/112330
- * config/loongarch/genopts/loongarch.opt.in: Add
- -m[no]-pass-relax-to-as. Change the default of -m[no]-relax to
- account conditional branch relaxation support status.
- * config/loongarch/loongarch.opt: Regenerate.
- * configure.ac (gcc_cv_as_loongarch_cond_branch_relax): Check if
- the assembler supports conditional branch relaxation.
- * configure: Regenerate.
- * config.in: Regenerate. Note that there are some unrelated
- changes introduced by r14-5424 (which does not contain a
- config.in regeneration).
- * config/loongarch/loongarch-opts.h
- (HAVE_AS_COND_BRANCH_RELAXATION): Define to 0 if not defined.
- * config/loongarch/loongarch-driver.h (ASM_MRELAX_DEFAULT):
- Define.
- (ASM_MRELAX_SPEC): Define.
- (ASM_SPEC): Use ASM_MRELAX_SPEC instead of "%{mno-relax}".
- * config/loongarch/loongarch.cc: Take the setting of
- -m[no-]relax into account when determining the default of
- -mexplicit-relocs=.
- * doc/invoke.texi: Document -m[no-]relax and
- -m[no-]pass-mrelax-to-as for LoongArch. Update the default
- value of -mexplicit-relocs=.
-
-2023-11-14 liuhongt <hongtao.liu@intel.com>
-
- PR tree-optimization/112496
- * tree-vect-loop.cc (vectorizable_nonlinear_induction): Return
- false when !tree_nop_conversion_p (TREE_TYPE (vectype),
- TREE_TYPE (init_expr)).
-
-2023-11-14 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/sync.md (mem_thread_fence): Remove redundant
- check.
- (mem_thread_fence_1): Emit finer-grained DBAR hints for
- different memory models, instead of 0.
-
-2023-11-14 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112511
- * tree.cc (type_contains_placeholder_1): Handle BITINT_TYPE like
- INTEGER_TYPE.
-
-2023-11-14 Jakub Jelinek <jakub@redhat.com>
- Hu, Lin1 <lin1.hu@intel.com>
-
- PR target/112435
- * config/i386/sse.md (avx512vl_shuf_<shuffletype>32x4_1<mask_name>,
- <mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>): Add
- alternative with just x instead of v constraints and xjm instead of
- vm and use vblendps as optimization only with that alternative.
-
-2023-11-14 liuhongt <hongtao.liu@intel.com>
-
- PR tree-optimization/105735
- PR tree-optimization/111972
- * tree-scalar-evolution.cc
- (analyze_and_compute_bitop_with_inv_effect): Handle bitop with
- INTEGER_CST.
-
-2023-11-13 Arsen Arsenović <arsen@aarsen.me>
-
- * configure: Regenerate.
- * aclocal.m4: Regenerate.
- * Makefile.in (LIBDEPS): Remove (potential) ./ prefix from
- LIBINTL_DEP.
- * doc/install.texi: Document new (notable) flags added by the
- optional gettext tree and by AM_GNU_GETTEXT. Document libintl/libc
- with gettext dependency.
-
-2023-11-13 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386-expand.h (gen_pushfl): New prototype.
- (gen_popfl): Ditto.
- * config/i386/i386-expand.cc (ix86_expand_builtin)
- [case IX86_BUILTIN_READ_FLAGS]: Use gen_pushfl.
- [case IX86_BUILTIN_WRITE_FLAGS]: Use gen_popfl.
- * config/i386/i386.cc (gen_pushfl): New function.
- (gen_popfl): Ditto.
- * config/i386/i386.md (unspec): Add UNSPEC_PUSHFL and UNSPEC_POPFL.
- (@pushfl<mode>2): Rename from *pushfl<mode>2.
- Rewrite as unspec using UNSPEC_PUSHFL.
- (@popfl<mode>1): Rename from *popfl<mode>1.
- Rewrite as unspec using UNSPEC_POPFL.
-
-2023-11-13 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112494
- * config/i386/i386.cc (ix86_cc_mode) [default]: Return CCmode.
-
-2023-11-13 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/riscv-vsetvl.cc (source_equal_p): Use pointer
- equality for REG_EQUAL.
-
-2023-11-13 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112495
- * tree-data-ref.cc (runtime_alias_check_p): Reject checks
- between different address spaces.
-
-2023-11-13 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112487
- * tree-inline.cc (setup_one_parameter): When the parameter
- is unused only insert a debug bind when there's not a gross
- mismatch in value and declared parameter type. Do not assert
- there effectively isn't.
-
-2023-11-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-v.cc
- (rvv_builder::combine_sequence_use_merge_profitable_p): New function.
- (expand_vector_init_merge_combine_sequence): Ditto.
- (expand_vec_init): Adapt for new optimization.
-
-2023-11-13 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/i386-expand.cc
- (ix86_expand_vector_init_duplicate): Handle V4HF/V4BF and
- V2HF/V2BF.
- (ix86_expand_vector_init_one_nonzero): Ditto.
- (ix86_expand_vector_init_one_var): Ditto.
- (ix86_expand_vector_init_general): Ditto.
- (ix86_expand_vector_set_var): Ditto.
- (ix86_expand_vector_set): Ditto.
- (ix86_expand_vector_extract): Ditto.
- * config/i386/mmx.md
- (mmxdoublevecmode): Extend to V4HF/V4BF/V2HF/V2BF.
- (*mmx_pinsrw): Extend to V4FI_64, add a new alternative (&x,
- x, x), add a new define_split after the pattern.
- (*mmx_pextrw<mode>): New define_insn.
- (mmx_pshufw_1): Rename to ..
- (mmx_pshufw<mode>_1): .. this, extend to V4FI_64.
- (*mmx_pblendw64): Extend to V4FI_64.
- (*vec_dup<mode>): New define_insn.
- (vec_setv4hi): Rename to ..
- (vec_set<mode>): .. this, and extend to V4FI_64
- (vec_extractv4hihi): Rename to ..
- (vec_extract<mode><mmxscalarmodelower>): .. this, and extend
- to V4FI_64.
- (vec_init<mode><mmxscalarmodelower>): New define_insn.
- (*pinsrw): Extend to V2FI_32, add a new alternative (&x,
- x, x), and add a new define_split after it.
- (*pextrw<mode>): New define_insn.
- (vec_setv2hi): Rename to ..
- (vec_set<mode>): .. this, extend to V2FI_32.
- (vec_extractv2hihi): Rename to ..
- (vec_extract<mode><mmxscalarmodelower>): .. this, extend to
- V2FI_32.
- (*punpckwd): Extend to V2FI_32.
- (*pshufw_1): Rename to ..
- (*pshufw<mode>_1): .. this, extend to V2FI_32.
- (vec_initv2hihi): Rename to ..
- (vec_init<mode><mmxscalarmodelower>): .. this, and extend to
- V2FI_32.
- (*vec_dup<mode>): New define_insn.
- * config/i386/sse.md (*vec_extract<mode>): Refine constraint
- from v to Yw.
-
-2023-11-13 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.md (UNSPEC_ARC_CC_NEZ): New UNSPEC that
- represents the carry flag being set if the operand is non-zero.
- (adc_f): New define_insn representing adc with updated flags.
- (ashrdi3): New define_expand that only handles shifts by 1.
- (ashrdi3_cnt1): New pre-reload define_insn_and_split.
- (lshrdi3): New define_expand that only handles shifts by 1.
- (lshrdi3_cnt1): New pre-reload define_insn_and_split.
- (rrcsi2): New define_insn for rrc (SImode rotate right through carry).
- (rrcsi2_carry): Likewise for rrc.f, as above but updating flags.
- (rotldi3): New define_expand that only handles rotates by 1.
- (rotldi3_cnt1): New pre-reload define_insn_and_split.
- (rotrdi3): New define_expand that only handles rotates by 1.
- (rotrdi3_cnt1): New pre-reload define_insn_and_split.
- (lshrsi3_cnt1_carry): New define_insn for lsr.f.
- (ashrsi3_cnt1_carry): New define_insn for asr.f.
- (btst_0_carry): New define_insn for asr.f without result.
-
-2023-11-13 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.cc (TARGET_FOLD_BUILTIN): Define to
- arc_fold_builtin.
- (arc_fold_builtin): New function. Convert ARC_BUILTIN_SWAP
- into a rotate. Evaluate ARC_BUILTIN_NORM and
- ARC_BUILTIN_NORMW of constant arguments.
- * config/arc/arc.md (UNSPEC_ARC_SWAP): Delete.
- (normw): Make output template/assembler whitespace consistent.
- (swap): Remove define_insn, only use of SWAP UNSPEC.
- * config/arc/builtins.def: Tweak indentation.
- (SWAP): Expand using rotlsi2_cnt16 instead of using swap.
-
-2023-11-13 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386.md (<insn><dwi>3_doubleword_lowpart): New
- define_insn_and_split to optimize register usage of doubleword
- right shifts followed by truncation.
-
-2023-11-13 Jakub Jelinek <jakub@redhat.com>
-
- * config/i386/constraints.md: Remove j constraint letter from list of
- unused letters.
-
-2023-11-13 Xi Ruoyao <xry111@xry111.site>
-
- PR rtl-optimization/112483
- * simplify-rtx.cc (simplify_binary_operation_1) <case COPYSIGN>:
- Fix the simplification of (fcopysign x, NEGATIVE_CONST).
-
-2023-11-13 Jakub Jelinek <jakub@redhat.com>
-
- PR tree-optimization/111967
- * gimple-range-cache.cc (block_range_cache::set_bb_range): Grow
- m_ssa_ranges to num_ssa_names rather than num_ssa_names + 1.
- (block_range_cache::dump): Iterate from 1 rather than 0. Don't use
- ssa_name (x) unless m_ssa_ranges[x] is non-NULL. Iterate to
- m_ssa_ranges.length () rather than num_ssa_names.
-
-2023-11-13 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.md (LD_AT_LEAST_32_BIT): New mode
- iterator.
- (ST_ANY): New mode iterator.
- (define_peephole2): Use LD_AT_LEAST_32_BIT instead of GPR and
- ST_ANY instead of QHWD for applicable patterns.
-
-2023-11-13 Xi Ruoyao <xry111@xry111.site>
-
- PR target/112476
- * config/loongarch/loongarch.cc
- (loongarch_expand_vec_cond_mask_expr): Call simplify_gen_subreg
- instead of gen_rtx_SUBREG.
-
-2023-11-13 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Add bridge mode to lrint and lround
- pattern.
- * config/riscv/riscv-protos.h (expand_vec_lrint): Add new arg
- bridge machine mode.
- (expand_vec_lround): Ditto.
- * config/riscv/riscv-v.cc (emit_vec_widden_cvt_f_f): New helper
- func impl to emit vfwcvt.f.f.
- (emit_vec_rounding_to_integer): Handle the HF to DI rounding
- with the bridge mode.
- (expand_vec_lrint): Reorder the args.
- (expand_vec_lround): Ditto.
- (expand_vec_lceil): Ditto.
- (expand_vec_lfloor): Ditto.
- * config/riscv/vector-iterators.md: Add vector HFmode and bridge
- mode for converting to DI.
-
-2023-11-12 Jeff Law <jlaw@ventanamicro.com>
-
- Revert:
- 2023-11-11 Jin Ma <jinma@linux.alibaba.com>
-
- * haifa-sched.cc (use_or_clobber_starts_range_p): New.
- (prune_ready_list): USE or CLOBBER should delay execution
- if it starts a new live range.
-
-2023-11-12 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (*stack_protect_set_4s_<mode>_di):
- Remove alternative 0.
-
-2023-11-11 Eric Botcazou <ebotcazou@adacore.com>
-
- * ipa-cp.cc (print_ipcp_constant_value): Move to...
- (values_equal_for_ipcp_p): Deal with VAR_DECLs from the
- constant pool.
- * ipa-prop.cc (ipa_print_constant_value): ...here. Likewise.
- (ipa_print_node_jump_functions_for_edge): Call the function
- ipa_print_constant_value to print IPA_JF_CONST elements.
-
-2023-11-11 Jin Ma <jinma@linux.alibaba.com>
-
- * haifa-sched.cc (use_or_clobber_starts_range_p): New.
- (prune_ready_list): USE or CLOBBER should delay execution
- if it starts a new live range.
-
-2023-11-11 Jakub Jelinek <jakub@redhat.com>
-
- PR middle-end/112430
- * tree-ssa-math-opts.cc (match_uaddc_usubc): Remove temp_stmts in the
- order they were pushed rather than in reverse order. Call
- release_defs after gsi_remove.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (mode_switching.backprop): New hook.
- * doc/tm.texi.in (TARGET_MODE_BACKPROP): New @hook.
- * doc/tm.texi: Regenerate.
- * mode-switching.cc (struct bb_info): Add single_succ.
- (confluence_info): Add transp field.
- (single_succ_confluence_n, single_succ_transfer): New functions.
- (backprop_confluence_n, backprop_transfer): Likewise.
- (optimize_mode_switching): Use them. Push mode transitions onto
- a block's incoming edges, if the backprop hook requires it.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (mode_switching.confluence): New hook.
- * doc/tm.texi (TARGET_MODE_CONFLUENCE): New @hook.
- * doc/tm.texi.in: Regenerate.
- * mode-switching.cc (confluence_info): New variable.
- (mode_confluence, forward_confluence_n, forward_transfer): New
- functions.
- (optimize_mode_switching): Use them to calculate mode_in when
- TARGET_MODE_CONFLUENCE is defined.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (commit_mode_sets): Use 1-based edge aux values.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (mode_switching.after): Add a regs_live parameter.
- * doc/tm.texi: Regenerate.
- * config/epiphany/epiphany-protos.h (epiphany_mode_after): Update
- accordingly.
- * config/epiphany/epiphany.cc (epiphany_mode_needed): Likewise.
- (epiphany_mode_after): Likewise.
- * config/i386/i386.cc (ix86_mode_after): Likewise.
- * config/riscv/riscv.cc (riscv_mode_after): Likewise.
- * config/sh/sh.cc (sh_mode_after): Likewise.
- * mode-switching.cc (optimize_mode_switching): Likewise.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (mode_switching.needed): Add a regs_live parameter.
- * doc/tm.texi: Regenerate.
- * config/epiphany/epiphany-protos.h (epiphany_mode_needed): Update
- accordingly.
- * config/epiphany/epiphany.cc (epiphany_mode_needed): Likewise.
- * config/epiphany/mode-switch-use.cc (insert_uses): Likewise.
- * config/i386/i386.cc (ix86_mode_needed): Likewise.
- * config/riscv/riscv.cc (riscv_mode_needed): Likewise.
- * config/sh/sh.cc (sh_mode_needed): Likewise.
- * mode-switching.cc (optimize_mode_switching): Likewise.
- (create_pre_exit): Likewise, using the DF simulate functions
- to calculate the required information.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def (mode_switching.eh_handler): New hook.
- * doc/tm.texi.in (TARGET_MODE_EH_HANDLER): New @hook.
- * doc/tm.texi: Regenerate.
- * mode-switching.cc (optimize_mode_switching): Use eh_handler
- to get the mode on entry to an exception handler.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (optimize_mode_switching): Mark the exit
- block as nontransparent if it requires a specific mode.
- Handle the entry and exit mode as sibling rather than nested
- concepts. Remove outdated comment.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (optimize_mode_switching): Initially
- compute transparency in a bit-per-block bitmap.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (seginfo): Add a prev_mode field.
- (new_seginfo): Take and initialize the prev_mode.
- (optimize_mode_switching): Update calls accordingly.
- Use the recorded modes during the emit phase, rather than
- computing one on the fly.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (add_seginfo): Replace head pointer with
- a pointer to the tail pointer.
- (optimize_mode_switching): Update calls accordingly.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc (optimize_mode_switching): Call
- df_note_add_problem.
-
-2023-11-11 Richard Sandiford <richard.sandiford@arm.com>
-
- * target.def: Tweak documentation of mode-switching hooks.
- * doc/tm.texi.in (OPTIMIZE_MODE_SWITCHING): Tweak documentation.
- (NUM_MODES_FOR_MODE_SWITCHING): Likewise.
- * doc/tm.texi: Regenerate.
-
-2023-11-11 Martin Uecker <uecker@tugraz.at>
-
- PR c/110815
- PR c/112428
- * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
- remove warning for parameters declared with `static`.
-
-2023-11-11 Joern Rennecke <joern.rennecke@embecosm.com>
-
- * doc/sourcebuild.texi (Scan the assembly output): Document change.
-
-2023-11-10 Mao <sray@live.com>
-
- PR middle-end/110983
- * doc/invoke.texi (Option Summary): Add -fpatchable-function-entry.
-
-2023-11-10 Maciej W. Rozycki <macro@embecosm.com>
-
- * config/riscv/riscv.md (length): Fix indentation for branch and
- jump length calculation expressions.
-
-2023-11-10 Eric Botcazou <ebotcazou@adacore.com>
-
- * fold-const.cc (operand_compare::operand_equal_p) <CONSTRUCTOR>:
- Deal with nonempty constant CONSTRUCTORs.
- (operand_compare::hash_operand) <CONSTRUCTOR>: Hash DECL_FIELD_OFFSET
- and DECL_FIELD_BIT_OFFSET for FIELD_DECLs.
-
-2023-11-10 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR target/112337
- * ira-costs.cc: (validate_autoinc_and_mem_addr_p): New function.
- (equiv_can_be_consumed_p): Use it.
-
-2023-11-10 Richard Sandiford <richard.sandiford@arm.com>
-
- * read-rtl.cc (md_reader::read_mapping): Allow iterators to
- include other iterators.
- * doc/md.texi: Document the change.
- * config/aarch64/iterators.md (DREG2, VQ2, TX2, DX2, SX2): Include
- the iterator that is being duplicated, rather than reproducing it.
- (VSTRUCT_D): Redefine using VSTRUCT_[234]D.
- (VSTRUCT_Q): Likewise VSTRUCT_[234]Q.
- (VSTRUCT_2QD, VSTRUCT_3QD, VSTRUCT_4QD, VSTRUCT_QD): Redefine using
- the individual D and Q iterators.
-
-2023-11-10 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (stack_protect_set_1 peephole2):
- Explicitly check operand 2 for word_mode.
- (stack_protect_set_1 peephole2 #2): Ditto.
- (stack_protect_set_2 peephole2): Ditto.
- (stack_protect_set_3 peephole2): Ditto.
- (*stack_protect_set_4z_<mode>_di): New insn patter.
- (*stack_protect_set_4s_<mode>_di): Ditto.
- (stack_protect_set_4 peephole2): New peephole2 pattern to
- substitute stack protector scratch register clear with unrelated
- register initialization involving zero/sign-extend instruction.
-
-2023-11-10 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (shift): Use SAL insted of SLL
- for ashift insn mnemonic.
-
-2023-11-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR tree-optimization/112438
- * tree-vect-loop.cc (vectorizable_induction): Bugfix when
- LOOP_VINFO_USING_SELECT_VL_P.
-
-2023-11-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (enum insn_type): New enum.
- * config/riscv/riscv-v.cc
- (rvv_builder::combine_sequence_use_slideup_profitable_p): New function.
- (expand_vector_init_slideup_combine_sequence): Ditto.
- (expand_vec_init): Add slideup combine optimization.
-
-2023-11-10 Robin Dapp <rdapp@ventanamicro.com>
-
- PR tree-optimization/112464
- * tree-vect-loop.cc (vectorize_fold_left_reduction): Use
- vect_orig_stmt on scalar_dest_def_info.
-
-2023-11-10 Jin Ma <jinma@linux.alibaba.com>
-
- * config/riscv/riscv.cc (riscv_for_each_saved_reg): Place the interrupt
- operation before the XTheadMemPair.
-
-2023-11-10 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110221
- * tree-vect-slp.cc (vect_schedule_slp_node): When loop
- masking / len is applied make sure to not schedule
- intenal defs outside of the loop.
-
-2023-11-10 Andrew Stubbs <ams@codesourcery.com>
-
- * expr.cc (store_constructor): Add "and" operation to uniform mask
- generation.
-
-2023-11-10 Andrew Stubbs <ams@codesourcery.com>
-
- PR target/112308
- * config/gcn/gcn-valu.md (add<mode>3<exec_clobber>): Fix B constraint
- and switch to the new format.
- (add<mode>3_dup<exec_clobber>): Likewise.
- (add<mode>3_vcc<exec_vcc>): Likewise.
- (add<mode>3_vcc_dup<exec_vcc>): Likewise.
- (add<mode>3_vcc_zext_dup): Likewise.
- (add<mode>3_vcc_zext_dup_exec): Likewise.
- (add<mode>3_vcc_zext_dup2): Likewise.
- (add<mode>3_vcc_zext_dup2_exec): Likewise.
-
-2023-11-10 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112469
- * match.pd (cond ? op a : b -> .COND_op (cond, a, b)): Add
- missing view_converts.
-
-2023-11-10 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn.cc (gcn_expand_reduc_scalar): Add clobber to DImode
- min/max instructions.
-
-2023-11-10 Chenghui Pan <panchenghui@loongson.cn>
-
- * config/loongarch/lsx.md: Fix instruction name typo in
- lsx_vreplgr2vr_<lsxfmt_f> template.
-
-2023-11-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec.md (vec_init<mode><vel>): Split patterns.
-
-2023-11-10 Pan Li <pan2.li@intel.com>
-
- Revert:
- 2023-11-10 Pan Li <pan2.li@intel.com>
- * config/riscv/riscv-v.cc (expand_vector_init_trailing_same_elem):
- New fun impl to expand the insn when trailing same elements.
- (expand_vec_init): Try trailing same elements when vec_init.
-
-2023-11-10 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (expand_vector_init_trailing_same_elem):
- New fun impl to expand the insn when trailing same elements.
- (expand_vec_init): Try trailing same elements when vec_init.
-
-2023-11-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_copysign<mode>): Remove.
- * config/riscv/autovec.md (cond_copysign<mode>): New pattern.
-
-2023-11-10 Pan Li <pan2.li@intel.com>
-
- PR target/112432
- * internal-fn.def (LRINT): Add FLOATN support.
- (LROUND): Ditto.
- (LLRINT): Ditto.
- (LLROUND): Ditto.
-
-2023-11-10 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/combiner.md (single bit sign_extract): Avoid recently
- added patterns for H8/SX.
- (single bit zero_extract): New patterns.
-
-2023-11-10 liuhongt <hongtao.liu@intel.com>
-
- PR target/112443
- * config/i386/sse.md (*avx2_pcmp<mode>3_4): Fix swap condition
- from LT to GT since there's not in the pattern.
- (*avx2_pcmp<mode>3_5): Ditto.
-
-2023-11-10 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * config/bpf/bpf.cc (bpf_print_register): Accept modifier code 'W'
- to force emitting register names using the wN form.
- * config/bpf/bpf.md (*mulsidi3_zeroextend): Force operands to
- always use wN written form in pseudo-C assembly syntax.
-
-2023-11-09 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-show-locus.cc (layout::m_line_table): New field.
- (compatible_locations_p): Convert to...
- (layout::compatible_locations_p): ...this, replacing uses of
- line_table global with m_line_table.
- (layout::layout): Convert "richloc" param from a pointer to a
- const reference. Initialize m_line_table member.
- (layout::maybe_add_location_range): Replace uses of line_table
- global with m_line_table. Pass the latter to
- linemap_client_expand_location_to_spelling_point.
- (layout::print_leading_fixits): Pass m_line_table to
- affects_line_p.
- (layout::print_trailing_fixits): Likewise.
- (gcc_rich_location::add_location_if_nearby): Update for change
- to layout ctor params.
- (diagnostic_show_locus): Convert to...
- (diagnostic_context::maybe_show_locus): ...this, converting
- richloc param from a pointer to a const reference. Make "loc"
- const. Split out printing part of function to...
- (diagnostic_context::show_locus): ...this.
- (selftest::test_offset_impl): Update for change to layout ctor
- params.
- (selftest::test_layout_x_offset_display_utf8): Likewise.
- (selftest::test_layout_x_offset_display_tab): Likewise.
- (selftest::test_tab_expansion): Likewise.
- * diagnostic.h (diagnostic_context::maybe_show_locus): New decl.
- (diagnostic_context::show_locus): New decl.
- (diagnostic_show_locus): Convert from a decl to an inline function.
- * gdbinit.in (break-on-diagnostic): Update from a breakpoint
- on diagnostic_show_locus to one on
- diagnostic_context::maybe_show_locus.
- * genmatch.cc (linemap_client_expand_location_to_spelling_point):
- Add "set" param and use it in place of line_table global.
- * input.cc (expand_location_1): Likewise.
- (expand_location): Update for new param of expand_location_1.
- (expand_location_to_spelling_point): Likewise.
- (linemap_client_expand_location_to_spelling_point): Add "set"
- param and use it in place of line_table global.
- * tree-diagnostic-path.cc (event_range::print): Pass line_table
- for new param of linemap_client_expand_location_to_spelling_point.
-
-2023-11-09 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (@stack_protect_set_1_<PTR:mode>_<W:mode>):
- Use W mode iterator instead of SWI48. Output MOV instead of XOR
- for TARGET_USE_MOV0.
- (stack_protect_set_1 peephole2): Use integer modes with
- mode size <= word mode size for operand 3.
- (stack_protect_set_1 peephole2 #2): New peephole2 pattern to
- substitute stack protector scratch register clear with unrelated
- register initialization, originally in front of stack
- protector sequence.
- (*stack_protect_set_3_<PTR:mode>_<SWI48:mode>): New insn pattern.
- (stack_protect_set_1 peephole2): New peephole2 pattern to
- substitute stack protector scratch register clear with unrelated
- register initialization involving LEA instruction.
-
-2023-11-09 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/110215
- * ira-lives.cc: (add_conflict_from_region_landing_pads): New
- function.
- (process_bb_node_lives): Use it.
-
-2023-11-09 Alexandre Oliva <oliva@adacore.com>
-
- * config/i386/i386.cc (symbolic_base_address_p,
- base_address_p): New, factored out from...
- (extract_base_offset_in_addr): ... here and extended to
- recognize REG+GOTOFF, as in gcc.target/i386/sse2-load-multi.c
- and sse2-store-multi.c with PIE enabled by default.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * config/aarch64/aarch64-sve.md (cond_copysign<mode>): New.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * config/aarch64/aarch64.md (copysign<GPF:mode>3): Handle
- copysign (x, -1).
- * config/aarch64/aarch64-simd.md (copysign<mode>3): Likewise.
- * config/aarch64/aarch64-sve.md (copysign<mode>3): Likewise.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * config/aarch64/aarch64.md (<optab><mode>3): Add SVE split case.
- * config/aarch64/aarch64-simd.md (ior<mode>3<vczle><vczbe>): Likewise.
- * config/aarch64/predicates.md(aarch64_orr_imm_sve_advsimd): New.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * config/aarch64/aarch64.md (*mov<mode>_aarch64, *movsi_aarch64,
- *movdi_aarch64): Add new w -> Z case.
- * config/aarch64/iterators.md (Vbtype): Add QI and HI.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * config/aarch64/aarch64-protos.h (aarch64_simd_special_constant_p,
- aarch64_maybe_generate_simd_constant): New.
- * config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VQMOV:mode>,
- *aarch64_simd_mov<VDMOV:mode>): Add new coden for special constants.
- * config/aarch64/aarch64.cc (aarch64_extract_vec_duplicate_wide_int):
- Take optional mode.
- (aarch64_simd_special_constant_p,
- aarch64_maybe_generate_simd_constant): New.
- * config/aarch64/aarch64.md (*movdi_aarch64): Add new codegen for
- special constants.
- * config/aarch64/constraints.md (Dx): new.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * internal-fn.def (COPYSIGN): New.
- * match.pd (UNCOND_BINARY, COND_BINARY): Map IFN_COPYSIGN to
- IFN_COND_COPYSIGN.
- * optabs.def (cond_copysign_optab, cond_len_copysign_optab): New.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * match.pd: Add new neg+abs rule, remove inverse copysign rule.
-
-2023-11-09 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/109154
- * match.pd: expand existing copysign optimizations.
-
-2023-11-09 Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
-
- PR driver/111605
- * collect2.cc (main): Do not prepend target triple to
- -fuse-ld=lld,mold.
-
-2023-11-09 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111133
- * tree-vect-stmts.cc (vect_build_scatter_store_calls):
- Remove and refactor to ...
- (vect_build_one_scatter_store_call): ... this new function.
- (vectorizable_store): Use vect_check_scalar_mask to record
- the SLP node for the mask operand. Code generate scatters
- with builtin decls from the main scatter vectorization
- path and prepare that for SLP.
- * tree-vect-slp.cc (vect_get_operand_map): Do not look
- at the VDEF to decide between scatter or gather since that
- doesn't work for patterns. Use the LHS being an SSA_NAME
- or not instead.
-
-2023-11-09 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv.cc (riscv_frm_emit_after_bb_end): Only
- perform once emit when at least one succ edge is abnormal.
-
-2023-11-09 Richard Biener <rguenther@suse.de>
-
- * tree-vect-loop.cc (vect_verify_full_masking_avx512):
- Check we have integer mode masks as required by
- vect_get_loop_mask.
-
-2023-11-09 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112444
- * tree-ssa-sccvn.cc (visit_phi): Avoid using not visited
- defs as undefined vals.
-
-2023-11-09 YunQiang Su <yunqiang.su@cipunited.com>
-
- * config/mips/mips.cc(mips_option_override): Set mips_abs to
- 2008, if mips_abs is default and mips_nan is 2008.
-
-2023-11-09 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Document
- -Wreturn-mismatch. Update -Wreturn-type documentation.
-
-2023-11-09 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.md: Remove UNSPEC_VEC_ELTSWAP.
- * config/s390/vector.md (eltswapv16qi): New expander.
- (*eltswapv16qi): New insn and splitter.
- (eltswapv8hi): New insn and splitter.
- (eltswap<mode>): New insn and splitter for modes V_HW_4 as well
- as V_HW_2.
- * config/s390/vx-builtins.md (eltswap<mode>): Remove.
- (*eltswapv16qi): Remove.
- (*eltswap<mode>): Remove.
- (*eltswap<mode>_emu): Remove.
-
-2023-11-09 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.cc (expand_perm_with_rot): Remove.
- (expand_perm_reverse_elements): New.
- (expand_perm_with_vster): Remove.
- (expand_perm_with_vstbrq): Remove.
- (vectorize_vec_perm_const_1): Replace removed functions with new
- one.
-
-2023-11-09 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.cc (expand_perm_with_merge): Deal with cases
- where vmr{l,h} are still applicable if the operands are swapped.
- (expand_perm_with_vpdi): Likewise for vpdi.
-
-2023-11-09 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * config/s390/s390.md (VX_CONV_INT): Remove iterator.
- (gf): Add float mappings.
- (TOINT, toint): New attribute.
- (*fixuns_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_z13):
- Remove.
- (*fixuns_trunc<mode><toint>2_z13): Add.
- (*fix_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_bfp_z13):
- Remove.
- (*fix_trunc<mode><toint>2_bfp_z13): Add.
- (*floatuns<VX_CONV_INT:mode><VX_CONV_BFP:mode>2_z13): Remove.
- (*floatuns<toint><mode>2_z13): Add.
- * config/s390/vector.md (VX_VEC_CONV_INT): Remove iterator.
- (float<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2): Remove.
- (float<tointvec><mode>2): Add.
- (floatuns<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2): Remove.
- (floatuns<tointvec><mode>2): Add.
- (fix_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2):
- Remove.
- (fix_trunc<mode><tointvec>2): Add.
- (fixuns_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2):
- Remove.
- (fixuns_trunc<VX_VEC_CONV_BFP:mode><tointvec>2): Add.
-
-2023-11-09 Jakub Jelinek <jakub@redhat.com>
-
- PR c/112339
- * attribs.cc (attribute_ignored_p): Only return true for
- attr_namespace_ignored_p if as is NULL.
- (decl_attributes): Never add ignored attributes.
-
-2023-11-09 Jin Ma <jinma@linux.alibaba.com>
-
- * config/riscv/bitmanip.md: Avoid the conflict between
- zbb and xtheadmemidx in patterns.
-
-2023-11-09 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Record
- to the correct simd_clone_info.
-
-2023-11-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vector-costs.cc (costs::preferred_new_lmul_p): Fix ICE.
-
-2023-11-09 Alexandre Oliva <oliva@adacore.com>
-
- * tree-cfg.cc (assign_discriminators): Handle debug stmts.
-
-2023-11-08 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/82524
- * config/i386/i386.md (*add<mode>_1_slp):
- Split insn only for unmatched operand 0.
- (*sub<mode>_1_slp): Ditto.
- (*<any_logic:code><mode>_1_slp): Merge pattern from "*and<mode>_1_slp"
- and "*<any_logic:code><mode>_1_slp" using any_logic code iterator.
- Split insn only for unmatched operand 0.
- (*neg<mode>1_slp): Split insn only for unmatched operand 0.
- (*one_cmpl<mode>_1_slp): Ditto.
- (*ashl<mode>3_1_slp): Ditto.
- (*<any_shiftrt:insn><mode>_1_slp): Ditto.
- (*<any_rotate:insn><mode>_1_slp): Ditto.
- (*addqi_ext<mode>_1): Redefine as define_insn_and_split. Add
- alternative 1 and split insn after reload for unmatched operand 0.
- (*<plusminus:insn>qi_ext<mode>_2): Merge pattern from
- "*addqi_ext<mode>_2" and "*subqi_ext<mode>_2" using plusminus code
- iterator. Redefine as define_insn_and_split. Add alternative 1
- and split insn after reload for unmatched operand 0.
- (*subqi_ext<mode>_1): Redefine as define_insn_and_split. Add
- alternative 1 and split insn after reload for unmatched operand 0.
- (*<any_logic:code>qi_ext<mode>_0): Merge pattern from
- "*andqi_ext<mode>_0" and and "*<any_logic:code>qi_ext<mode>_0" using
- any_logic code iterator.
- (*<any_logic:code>qi_ext<mode>_1): Merge pattern from
- "*andqi_ext<mode>_1" and "*<any_logic:code>qi_ext<mode>_1" using
- any_logic code iterator. Redefine as define_insn_and_split. Add
- alternative 1 and split insn after reload for unmatched operand 0.
- (*<any_logic:code>qi_ext<mode>_1_cc): Merge pattern from
- "*andqi_ext<mode>_1_cc" and "*xorqi_ext<mode>_1_cc" using any_logic
- code iterator. Redefine as define_insn_and_split. Add alternative 1
- and split insn after reload for unmatched operand 0.
- (*<any_logic:code>qi_ext<mode>_2): Merge pattern from
- "*andqi_ext<mode>_2" and "*<any_or:code>qi_ext<mode>_2" using
- any_logic code iterator. Redefine as define_insn_and_split. Add
- alternative 1 and split insn after reload for unmatched operand 0.
- (*<any_logic:code>qi_ext<mode>_3): Redefine as define_insn_and_split.
- Add alternative 1 and split insn after reload for unmatched operand 0.
- (*negqi_ext<mode>_1): Rename from "*negqi_ext<mode>_2". Add
- alternative 1 and split insn after reload for unmatched operand 0.
- (*one_cmplqi_ext<mode>_1): Ditto.
- (*ashlqi_ext<mode>_1): Ditto.
- (*<any_shiftrt:insn>qi_ext<mode>_1): Ditto.
-
-2023-11-08 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vectorizable_load): Adjust offset
- vector gathering for SLP of emulated gathers.
-
-2023-11-08 Richard Biener <rguenther@suse.de>
-
- * tree-vectorizer.h (vect_slp_child_index_for_operand):
- Add gatherscatter_p argument.
- * tree-vect-slp.cc (vect_slp_child_index_for_operand): Likewise.
- Pass it on.
- * tree-vect-stmts.cc (vect_check_store_rhs): Turn the rhs
- argument into an output, also output the SLP node associated
- with it.
- (vectorizable_simd_clone_call): Adjust.
- (vectorizable_store): Likewise.
- (vectorizable_load): Likewise.
-
-2023-11-08 Richard Biener <rguenther@suse.de>
-
- * tree-vect-stmts.cc (vectorizable_load): Use the correct
- vectorized mask operand.
-
-2023-11-08 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/vector.md (*vsetvldi_no_side_effects_si_extend):
- New combine pattern.
-
-2023-11-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc: Fix ICE.
-
-2023-11-08 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-c.cc (riscv_check_builtin_call): Eliminate warning.
-
-2023-11-08 Hongyu Wang <hongyu.wang@intel.com>
-
- PR target/112394
- * config/i386/constraints.md (jc): New constraint that prohibits
- EGPR on -mno-avx.
- * config/i386/i386.md (*movdi_internal): Change r constraint
- corresponds to Yd.
- (*movti_internal): Likewise.
-
-2023-11-08 Florian Weimer <fweimer@redhat.com>
-
- * doc/invoke.texi (Warning Options): Mention C diagnostics
- for -fpermissive.
-
-2023-11-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112092
- * config/riscv/riscv-vector-builtins-bases.cc: Normalize the vsetvls.
-
-2023-11-08 Haochen Jiang <haochen.jiang@intel.com>
-
- PR target/111907
- * config/i386/i386.md (avx_noavx512vl): New definition for isa
- attribute.
- * config/i386/sse.md (*andnot<mode>3): Change isa attribute from
- avx_noavx512f to avx_noavx512vl.
-
-2023-11-07 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Remove the size check of lfloor.
- * config/riscv/riscv-v.cc (expand_vec_lfloor): Leverage
- emit_vec_rounding_to_integer for floor.
-
-2023-11-07 Robin Dapp <rdapp@ventanamicro.com>
-
- PR tree-optimization/112361
- PR target/112359
- PR middle-end/112406
- * tree-if-conv.cc (convert_scalar_cond_reduction): Remember if
- loop was versioned and only then create COND_OPs.
- (predicate_scalar_phi): Do not create COND_OP when not
- vectorizing.
- * tree-vect-loop.cc (vect_expand_fold_left): Re-create
- VEC_COND_EXPR.
- (vectorize_fold_left_reduction): Pass mask to
- vect_expand_fold_left.
-
-2023-11-07 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/predicates.md ("flags_reg_operand"):
- Make predicate special to avoid automatic mode checks.
-
-2023-11-07 Martin Jambor <mjambor@suse.cz>
-
- * configure: Regenerate.
-
-2023-11-07 Kwok Cheung Yeung <kcy@codesourcery.com>
-
- * lto-cgraph.cc (enum LTO_symtab_tags): Add tag for indirect
- functions.
- (output_offload_tables): Write indirect functions.
- (input_offload_tables): read indirect functions.
- * lto-section-names.h (OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): New.
- * omp-builtins.def (BUILT_IN_GOMP_TARGET_MAP_INDIRECT_PTR): New.
- * omp-offload.cc (offload_ind_funcs): New.
- (omp_discover_implicit_declare_target): Add functions marked with
- 'omp declare target indirect' to indirect functions list.
- (omp_finish_file): Add indirect functions to section for offload
- indirect functions.
- (execute_omp_device_lower): Redirect indirect calls on target by
- passing function pointer to BUILT_IN_GOMP_TARGET_MAP_INDIRECT_PTR.
- (pass_omp_device_lower::gate): Run pass_omp_device_lower if
- indirect functions are present on an accelerator device.
- * omp-offload.h (offload_ind_funcs): New.
- * tree-core.h (omp_clause_code): Add OMP_CLAUSE_INDIRECT.
- * tree.cc (omp_clause_num_ops): Add entry for OMP_CLAUSE_INDIRECT.
- (omp_clause_code_name): Likewise.
- * tree.h (OMP_CLAUSE_INDIRECT_EXPR): New.
- * config/gcn/mkoffload.cc (process_asm): Process offload_ind_funcs
- section. Count number of indirect functions.
- (process_obj): Emit number of indirect functions.
- * config/nvptx/mkoffload.cc (ind_func_ids, ind_funcs_tail): New.
- (process): Emit offload_ind_func_table in PTX code. Emit indirect
- function names and count in image.
- * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Mark
- indirect functions in PTX code with IND_FUNC_MAP.
-
-2023-11-07 Tobias Burnus <tobias@codesourcery.com>
-
- * doc/invoke.texi (-fopenmp, -fopenmp-simd): Adjust wording for
- attribute syntax supported also in C.
-
-2023-11-07 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_print_operand): Add a %Z
- modifier for SVE registers.
-
-2023-11-07 Joseph Myers <joseph@codesourcery.com>
-
- * builtins.def (DEF_C2X_BUILTIN): Rename to DEF_C23_BUILTIN and
- use flag_isoc23 and function_c23_misc.
- * config/rl78/rl78.cc (rl78_option_override): Compare
- lang_hooks.name with "GNU C23" not "GNU C2X".
- * coretypes.h (function_c2x_misc): Rename to function_c23_misc.
- * doc/cpp.texi (@code{__has_attribute}): Refer to C23 instead of
- C2x.
- * doc/extend.texi: Likewise.
- * doc/invoke.texi: Likewise.
- * dwarf2out.cc (highest_c_language, gen_compile_unit_die): Compare
- against and return "GNU C23" language string instead of "GNU C2X".
- * ginclude/float.h: Refer to C23 instead of C2X in comments.
- * ginclude/stdint-gcc.h: Likewise.
- * glimits.h: Likewise.
- * tree.h: Likewise.
-
-2023-11-07 Alexandre Oliva <oliva@adacore.com>
-
- * doc/sourcebuild.texi (opt_mstrict_align): New target.
-
-2023-11-07 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec-opt.md (*cond_len_<optab><v_double_trunc><mode>):
- New combine pattern.
- (*cond_len_<optab><v_quad_trunc><mode>): Ditto.
- (*cond_len_<optab><v_oct_trunc><mode>): Ditto.
- (*cond_len_extend<v_double_trunc><mode>): Ditto.
- (*cond_len_widen_reduc_plus_scal_<mode>): Ditto.
-
-2023-11-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112399
- * config/riscv/riscv-avlprop.cc
- (pass_avlprop::get_vlmax_ta_preferred_avl): Enhance AVL propagation.
- * config/riscv/t-riscv: Add new include.
-
-2023-11-07 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Remove the size check of lceil.l
- * config/riscv/riscv-v.cc (expand_vec_lceil): Leverage
- emit_vec_rounding_to_integer for ceil.
-
-2023-11-06 John David Anglin <danglin@gcc.gnu.org>
-
- * config/pa/pa.cc (pa_asm_trampoline_template): Fix typo.
-
-2023-11-06 John David Anglin <danglin@gcc.gnu.org>
-
- * config/pa/pa-linux.h (NEED_INDICATE_EXEC_STACK): Define to 1.
-
-2023-11-06 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic-show-locus.cc (class colorizer): Take just a
- pretty_printer rather than a diagnostic_context.
- (layout::layout): Make context param a const reference,
- and pretty_printer param non-optional.
- (layout::m_context): Drop field.
- (layout::m_options): New field.
- (layout::m_colorize_source_p): Drop field.
- (layout::m_show_labels_p): Drop field.
- (layout::m_show_line_numbers_p): Drop field.
- (layout::print_gap_in_line_numbering): Use m_options.
- (layout::calculate_line_spans): Likewise.
- (layout::calculate_linenum_width): Likewise.
- (layout::calculate_x_offset_display): Likewise.
- (layout::print_source_line): Likewise.
- (layout::start_annotation_line): Likewise.
- (layout::print_annotation_line): Likewise.
- (layout::print_line): Likewise.
- (gcc_rich_location::add_location_if_nearby): Update for changes to
- layout ctor.
- (diagnostic_show_locus): Likewise.
- (selftest::test_offset_impl): Likewise.
- (selftest::test_layout_x_offset_display_utf8): Likewise.
- (selftest::test_layout_x_offset_display_tab): Likewise.
- (selftest::test_tab_expansion): Likewise.
- * diagnostic.h (diagnostic_context::m_source_printing): Move
- declaration of struct outside diagnostic_context as...
- (struct diagnostic_source_printing_options)... this.
-
-2023-11-06 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_context::push_diagnostics): Convert
- to...
- (diagnostic_option_classifier::push): ...this.
- (diagnostic_context::pop_diagnostics): Convert to...
- (diagnostic_option_classifier::pop): ...this.
- (diagnostic_context::initialize): Move code to...
- (diagnostic_option_classifier::init): ...this new function.
- (diagnostic_context::finish): Move code to...
- (diagnostic_option_classifier::fini): ...this new function.
- (diagnostic_context::classify_diagnostic): Convert to...
- (diagnostic_option_classifier::classify_diagnostic): ...this.
- (diagnostic_context::update_effective_level_from_pragmas): Convert
- to...
- (diagnostic_option_classifier::update_effective_level_from_pragmas):
- ...this.
- (diagnostic_context::diagnostic_enabled): Update for refactoring.
- * diagnostic.h (struct diagnostic_classification_change_t): Move into...
- (class diagnostic_option_classifier): ...this new class.
- (diagnostic_context::option_unspecified_p): Update for move of
- fields into m_option_classifier.
- (diagnostic_context::classify_diagnostic): Likewise.
- (diagnostic_context::push_diagnostics): Likewise.
- (diagnostic_context::pop_diagnostics): Likewise.
- (diagnostic_context::update_effective_level_from_pragmas): Delete.
- (diagnostic_context::m_classify_diagnostic): Move into class
- diagnostic_option_classifier.
- (diagnostic_context::m_option_classifier): Likewise.
- (diagnostic_context::m_classification_history): Likewise.
- (diagnostic_context::m_n_classification_history): Likewise.
- (diagnostic_context::m_push_list): Likewise.
- (diagnostic_context::m_n_push): Likewise.
- (diagnostic_context::m_option_classifier): New.
-
-2023-11-06 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_context::set_urlifier): New.
- * diagnostic.h (diagnostic_context::set_urlifier): New decl.
- (diagnostic_context::m_urlifier): Make private.
- * gcc.cc (driver::global_initializations): Use set_urlifier rather
- than directly setting field.
- * toplev.cc (general_init): Likewise.
-
-2023-11-06 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_context::check_max_errors): Replace
- uses of diagnostic_kind_count with simple field acesss.
- (diagnostic_context::report_diagnostic): Likewise.
- (diagnostic_text_output_format::~diagnostic_text_output_format):
- Replace use of diagnostic_kind_count with
- diagnostic_context::diagnostic_count.
- * diagnostic.h (diagnostic_kind_count): Delete.
- (errorcount): Replace use of diagnostic_kind_count with
- diagnostic_context::diagnostic_count.
- (warningcount): Likewise.
- (werrorcount): Likewise.
- (sorrycount): Likewise.
-
-2023-11-06 Christophe Lyon <christophe.lyon@linaro.org>
-
- * doc/sourcebuild.texi (Other attributes): Document thread_fence
- effective-target.
-
-2023-11-06 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/constraints.md (Bc): Remove constraint.
- (Bn): Rewrite to use x86_extended_reg_mentioned_p predicate.
- * config/i386/i386.cc (ix86_memory_address_reg_class):
- Do not limit processing to TARGET_APX_EGPR. Exit early for
- NULL insn. Do not check recog_data.insn before calling
- extract_insn_cached.
- (ix86_insn_base_reg_class): Handle ADDR_GPR8.
- (ix86_regno_ok_for_insn_base_p): Ditto.
- (ix86_insn_index_reg_class): Ditto.
- * config/i386/i386.md (*cmpqi_ext<mode>_1_mem_rex64):
- Remove insn pattern and corresponding peephole2 pattern.
- (*cmpi_ext<mode>_1): Remove (m,Q) alternative.
- Change (QBc,Q) alternative to (QBn,Q). Add "addr" attribute.
- (*cmpqi_ext<mode>_3_mem_rex64): Remove insn pattern
- and corresponding peephole2 pattern.
- (*cmpi_ext<mode>_3): Remove (Q,m) alternative.
- Change (Q,QnBc) alternative to (Q,QnBn). Add "addr" attribute.
- (*extzvqi_mem_rex64): Remove insn pattern and
- corresponding peephole2 pattern.
- (*extzvqi): Remove (Q,m) alternative. Change (Q,QnBc)
- alternative to (Q,QnBn). Add "addr" attribute.
- (*insvqi_1_mem_rex64): Remove insn pattern and
- corresponding peephole2 pattern.
- (*insvqi_1): Remove (Q,m) alternative. Change (Q,QnBc)
- alternative to (Q,QnBn). Add "addr" attribute.
- (@insv<mode>_1): Ditto.
- (*addqi_ext<mode>_0): Remove (m,0,Q) alternative. Change (QBc,0,Q)
- alternative to (QBn,0,Q). Add "addr" attribute.
- (*subqi_ext<mode>_0): Ditto.
- (*andqi_ext<mode>_0): Ditto.
- (*<any_or:code>qi_ext<mode>_0): Ditto.
- (*addqi_ext<mode>_1): Remove (Q,0,m) alternative. Change (Q,0,QnBc)
- alternative to (Q,0,QnBn). Add "addr" attribute.
- (*andqi_ext<mode>_1): Ditto.
- (*andqi_ext<mode>_1_cc): Ditto.
- (*<any_or:code>qi_ext<mode>_1): Ditto.
- (*xorqi_ext<mode>_1_cc): Ditto.
- * config/i386/predicates.md (nonimm_x64constmem_operand):
- Remove predicate.
- (general_x64constmem_operand): Ditto.
- (norex_memory_operand): Ditto.
-
-2023-11-06 Joseph Myers <joseph@codesourcery.com>
-
- PR c/107954
- * doc/cpp.texi (__STDC_VERSION__): Refer to -std=c23 and
- -std=gnu23 instead of -std=c2x and -std=gnu2x.
- * doc/extend.texi (Attribute Syntax): Refer to C23 and -std=c23
- instead of C2x and -std=c2x.
- * doc/invoke.texi (-Wc11-c23-compat, -std=c23, -std=gnu23)
- (-std=iso9899:2024): Document, with -Wc11-c2x-compat, -std=c2x and
- -std=gnu2x as deprecated aliases. Update descriptions of C23.
- * doc/standards.texi (Standards): Describe C23 with C2X as an old
- name.
-
-2023-11-06 Thomas Schwinge <thomas@codesourcery.com>
-
- * config/nvptx/nvptx.h (MAKE_DECL_ONE_ONLY): Define.
-
-2023-11-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112405
- * tree-vect-stmts.cc (vectorizable_simd_clone_call):
- Properly handle invariant and/or loop mask passing.
-
-2023-11-06 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Remove the size check of lround.
- * config/riscv/riscv-v.cc (expand_vec_lround): Leverage
- emit_vec_rounding_to_integer for round.
-
-2023-11-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/predicates.md: Adapt predicate.
- * config/riscv/riscv-protos.h (can_be_broadcasted_p): New function.
- * config/riscv/riscv-v.cc (can_be_broadcasted_p): Ditto.
- * config/riscv/vector.md (vec_duplicate<mode>): New pattern.
- (*vec_duplicate<mode>): Adapt vec_duplicate insn pattern.
-
-2023-11-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111950
- * tree-vect-loop-manip.cc (slpeel_duplicate_current_defs_from_edges):
- Remove.
- (find_guard_arg): Likewise.
- (slpeel_update_phi_nodes_for_guard2): Likewise.
- (slpeel_tree_duplicate_loop_to_edge_cfg): Remove calls to
- slpeel_duplicate_current_defs_from_edges, do not elide
- LC-PHIs for invariant values.
- (vect_do_peeling): Materialize PHI arguments for the edge
- around the epilog from the PHI defs of the main loop exit.
-
-2023-11-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112404
- * tree-vectorizer.h (get_mask_type_for_scalar_type): Declare
- overload with SLP node argument.
- * tree-vect-stmts.cc (get_mask_type_for_scalar_type): Implement it.
- (vect_check_scalar_mask): Use it.
- * tree-vect-slp.cc (vect_gather_slp_loads): Properly identify
- loads also for nodes with children, like .MASK_LOAD.
- * tree-vect-loop.cc (vect_analyze_loop_2): Look at the
- representative for load nodes and check whether it is a grouped
- access before looking for load-lanes support.
-
-2023-11-06 Robin Dapp <rdapp@ventanamicro.com>
-
- PR tree-optimization/111760
- * config/riscv/autovec.md (vcond_mask_len_<mode><vm>): Add
- expander.
- * config/riscv/riscv-protos.h (enum insn_type): Add.
- * config/riscv/riscv-v.cc (needs_fp_rounding): Add !pred_mov.
- * doc/md.texi: Add vcond_mask_len.
- * gimple-match-exports.cc (maybe_resimplify_conditional_op):
- Create VCOND_MASK_LEN when length masking.
- * gimple-match.h (gimple_match_op::gimple_match_op): Always
- initialize len and bias.
- * internal-fn.cc (vec_cond_mask_len_direct): Add.
- (direct_vec_cond_mask_len_optab_supported_p): Add.
- (internal_fn_len_index): Add VCOND_MASK_LEN.
- (internal_fn_mask_index): Ditto.
- * internal-fn.def (VCOND_MASK_LEN): New internal function.
- * match.pd: Combine unconditional unary, binary and ternary
- operations into the respective COND_LEN operations.
- * optabs.def (OPTAB_D): Add vcond_mask_len optab.
-
-2023-11-06 Richard Sandiford <richard.sandiford@arm.com>
-
- * explow.cc (align_dynamic_address): Do nothing if the required
- alignment is a byte.
-
-2023-11-06 Richard Sandiford <richard.sandiford@arm.com>
-
- * function.h (get_stack_dynamic_offset): Declare.
- * function.cc (get_stack_dynamic_offset): New function,
- split out from...
- (get_stack_dynamic_offset): ...here.
- * explow.cc (allocate_dynamic_stack_space): Handle calls made
- after virtual registers have been instantiated.
-
-2023-11-06 liuhongt <hongtao.liu@intel.com>
-
- PR target/112393
- * config/i386/i386-expand.cc (ix86_expand_vec_perm_vpermt2):
- Avoid generating RTL code when d->testing_p.
-
-2023-11-06 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112369
- * tree.cc (strip_float_extensions): Use element_precision.
-
-2023-11-06 Richard Biener <rguenther@suse.de>
-
- PR middle-end/112296
- * doc/extend.texi (__builtin_constant_p): Clarify that
- side-effects are discarded.
-
-2023-11-06 Kewen Lin <linkw@linux.ibm.com>
-
- PR target/111828
- * config.in: Regenerate.
- * config/rs6000/rs6000.cc (rs6000_update_ipa_fn_target_info): Guard
- inline asm handling under !HAVE_AS_POWER10_HTM.
- * configure: Regenerate.
- * configure.ac: Detect assembler support for HTM insns at power10.
-
-2023-11-06 xuli <xuli1@eswincomputing.com>
- Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): New function for the hook.
- (riscv_register_pragmas): Register the hook.
- * config/riscv/riscv-protos.h (resolve_overloaded_builtin): New decl.
- * config/riscv/riscv-vector-builtins-bases.cc: New function impl.
- * config/riscv/riscv-vector-builtins-shapes.cc (build_one): Register overloaded function.
- * config/riscv/riscv-vector-builtins.cc (struct non_overloaded_registered_function_hasher):
- New hash table.
- (function_builder::add_function): Add overloaded arg.
- (function_builder::add_unique_function): Map overloaded function to non-overloaded function.
- (function_builder::add_overloaded_function): New API impl.
- (registered_function::overloaded_hash): Calculate hash value.
- (has_vxrm_or_frm_p): New function impl.
- (non_overloaded_registered_function_hasher::hash): Ditto.
- (non_overloaded_registered_function_hasher::equal): Ditto.
- (handle_pragma_vector): Allocate space for hash table.
- (resolve_overloaded_builtin): New function impl.
- * config/riscv/riscv-vector-builtins.h (function_base::may_require_frm_p): Ditto.
- (function_base::may_require_vxrm_p): Ditto.
-
-2023-11-06 Haochen Jiang <haochen.jiang@intel.com>
-
- PR target/111889
- * config/i386/avx512bf16intrin.h: Push no-evex512 target.
- * config/i386/avx512bf16vlintrin.h: Ditto.
- * config/i386/avx512bitalgvlintrin.h: Ditto.
- * config/i386/avx512bwintrin.h: Ditto.
- * config/i386/avx512dqintrin.h: Ditto.
- * config/i386/avx512fintrin.h: Ditto.
- * config/i386/avx512fp16intrin.h: Ditto.
- * config/i386/avx512fp16vlintrin.h: Ditto.
- * config/i386/avx512ifmavlintrin.h: Ditto.
- * config/i386/avx512vbmi2vlintrin.h: Ditto.
- * config/i386/avx512vbmivlintrin.h: Ditto.
- * config/i386/avx512vlbwintrin.h: Ditto.
- * config/i386/avx512vldqintrin.h: Ditto.
- * config/i386/avx512vlintrin.h: Ditto.
- * config/i386/avx512vnnivlintrin.h: Ditto.
- * config/i386/avx512vp2intersectvlintrin.h: Ditto.
- * config/i386/avx512vpopcntdqvlintrin.h: Ditto.
-
-2023-11-06 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512bf16vlintrin.h
- (_mm_avx512_castsi128_ps): New.
- (_mm256_avx512_castsi256_ps): Ditto.
- (_mm_avx512_slli_epi32): Ditto.
- (_mm256_avx512_slli_epi32): Ditto.
- (_mm_avx512_cvtepi16_epi32): Ditto.
- (_mm256_avx512_cvtepi16_epi32): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512bwintrin.h
- (_mm_avx512_set_epi32): New.
- (_mm_avx512_set_epi16): Ditto.
- (_mm_avx512_set_epi8): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512fp16intrin.h: Ditto.
- * config/i386/avx512fp16vlintrin.h
- (_mm_avx512_set1_ps): New.
- (_mm256_avx512_set1_ps): Ditto.
- (_mm_avx512_and_si128): Ditto.
- (_mm256_avx512_and_si256): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512vlbwintrin.h
- (_mm_avx512_set1_epi32): New.
- (_mm_avx512_set1_epi16): Ditto.
- (_mm_avx512_set1_epi8): Ditto.
- (_mm256_avx512_set_epi16): Ditto.
- (_mm256_avx512_set_epi8): Ditto.
- (_mm256_avx512_set1_epi16): Ditto.
- (_mm256_avx512_set1_epi32): Ditto.
- (_mm256_avx512_set1_epi8): Ditto.
- (_mm_avx512_max_epi16): Ditto.
- (_mm_avx512_min_epi16): Ditto.
- (_mm_avx512_max_epu16): Ditto.
- (_mm_avx512_min_epu16): Ditto.
- (_mm_avx512_max_epi8): Ditto.
- (_mm_avx512_min_epi8): Ditto.
- (_mm_avx512_max_epu8): Ditto.
- (_mm_avx512_min_epu8): Ditto.
- (_mm256_avx512_max_epi16): Ditto.
- (_mm256_avx512_min_epi16): Ditto.
- (_mm256_avx512_max_epu16): Ditto.
- (_mm256_avx512_min_epu16): Ditto.
- (_mm256_avx512_insertf128_ps): Ditto.
- (_mm256_avx512_extractf128_pd): Ditto.
- (_mm256_avx512_extracti128_si256): Ditto.
- (_MM256_AVX512_REDUCE_OPERATOR_BASIC_EPI16): Ditto.
- (_MM256_AVX512_REDUCE_OPERATOR_MAX_MIN_EP16): Ditto.
- (_MM256_AVX512_REDUCE_OPERATOR_BASIC_EPI8): Ditto.
- (_MM256_AVX512_REDUCE_OPERATOR_MAX_MIN_EP8): Ditto.
- (__attribute__): Change intrin call.
-
-2023-11-06 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512bf16vlintrin.h: Change intrin call.
- * config/i386/avx512fintrin.h
- (_mm_avx512_undefined_ps): New.
- (_mm_avx512_undefined_pd): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512vbmivlintrin.h: Ditto.
- * config/i386/avx512vlbwintrin.h: Ditto.
- * config/i386/avx512vldqintrin.h: Ditto.
- * config/i386/avx512vlintrin.h
- (_mm_avx512_undefined_si128): New.
- (_mm256_avx512_undefined_ps): Ditto.
- (_mm256_avx512_undefined_pd): Ditto.
- (_mm256_avx512_undefined_si256): Ditto.
- (__attribute__): Change intrin call.
-
-2023-11-06 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512bitalgvlintrin.h: Change intrin call.
- * config/i386/avx512dqintrin.h: Ditto.
- * config/i386/avx512fintrin.h:
- (_mm_avx512_setzero_ps): New.
- (_mm_avx512_setzero_pd): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512fp16intrin.h: Ditto.
- * config/i386/avx512fp16vlintrin.h: Ditto.
- * config/i386/avx512vbmi2vlintrin.h: Ditto.
- * config/i386/avx512vbmivlintrin.h: Ditto.
- * config/i386/avx512vlbwintrin.h: Ditto.
- * config/i386/avx512vldqintrin.h: Ditto.
- * config/i386/avx512vlintrin.h
- (_mm_avx512_setzero_si128): New.
- (_mm256_avx512_setzero_pd): Ditto.
- (_mm256_avx512_setzero_ps): Ditto.
- (_mm256_avx512_setzero_si256): Ditto.
- (__attribute__): Change intrin call.
- * config/i386/avx512vpopcntdqvlintrin.h: Ditto.
- * config/i386/gfniintrin.h: Ditto.
-
-2023-11-05 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.h (enum reg_class): Add LEGACY_INDEX_REGS.
- Rename LEGACY_REGS to LEGACY_GENERAL_REGS.
- (REG_CLASS_NAMES): Ditto.
- (REG_CLASS_CONTENTS): Ditto.
- * config/i386/constraints.md ("R"): Update for rename.
-
-2023-11-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * mode-switching.cc: Remove unused forward references.
- (seginfo): Remove bbnum.
- (new_seginfo): Remove associated argument.
- (optimize_mode_switching): Update calls accordingly.
-
-2023-11-05 Richard Sandiford <richard.sandiford@arm.com>
-
- * read-rtl.cc (read_rtx_operand): Avoid spinning endlessly for
- invalid [...] operands.
-
-2023-11-05 Richard Sandiford <richard.sandiford@arm.com>
-
- PR target/112105
- * config/aarch64/aarch64.cc (aarch64_modes_compatible_p): New
- function, with the core logic extracted from...
- (aarch64_can_change_mode_class): ...here. Extend the previous rules
- to allow changes between partial SVE modes and other modes if
- the other mode is no bigger than an element, and if no other rule
- prevents it. Use the aarch64_modes_tieable_p handling of
- partial Advanced SIMD structure modes.
- (aarch64_modes_tieable_p): Use aarch64_modes_compatible_p.
- Allow all vector mode ties that it allows.
-
-2023-11-05 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md: Remove the size check of lrint.
- * config/riscv/riscv-v.cc (emit_vec_narrow_cvt_x_f): New help
- emit func impl.
- (emit_vec_widden_cvt_x_f): New help emit func impl.
- (emit_vec_rounding_to_integer): New func impl to emit the
- rounding from FP to integer.
- (expand_vec_lrint): Leverage emit_vec_rounding_to_integer.
- * config/riscv/vector.md: Take V_VLSF for vfncvt.
-
-2023-11-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix bug.
-
-2023-11-04 Sergei Trofimovich <siarheit@google.com>
-
- PR bootstrap/112379
- * gcc-urlifier.cc (get_url_suffix_for_quoted_text): Mark as
- ATTRIBUTE_UNUSED.
-
-2023-11-04 Pan Li <pan2.li@intel.com>
-
- * config/riscv/vector-iterators.md: Remove HF modes.
-
-2023-11-04 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc: Include "pretty-print-urlifier.h".
- (diagnostic_context::initialize): Initialize m_urlifier.
- (diagnostic_context::finish): Clean up m_urlifier
- (diagnostic_report::diagnostic): m_urlifier to pp_format.
- * diagnostic.h (diagnostic_context::m_urlifier): New field.
- * gcc-urlifier.cc: New file.
- * gcc-urlifier.def: New file.
- * gcc-urlifier.h: New file.
- * gcc.cc: Include "gcc-urlifier.h".
- (driver::global_initializations): Initialize global_dc->m_urlifier.
- * pretty-print-urlifier.h: New file.
- * pretty-print.cc: Include "pretty-print-urlifier.h".
- (obstack_append_string): New.
- (urlify_quoted_string): New.
- (pp_format): Add "urlifier" param and use it to implement optional
- urlification of quoted text strings.
- (pp_output_formatted_text): Make buffer a const pointer.
- (selftest::pp_printf_with_urlifier): New.
- (selftest::test_urlification): New.
- (selftest::pretty_print_cc_tests): Call it.
- * pretty-print.h (class urlifier): New forward declaration.
- (pp_format): Add optional urlifier param.
- * selftest-run-tests.cc (selftest::run_tests): Call
- selftest::gcc_urlifier_cc_tests .
- * selftest.h (selftest::gcc_urlifier_cc_tests): New decl.
- * toplev.cc: Include "gcc-urlifier.h".
- (general_init): Initialize global_dc->m_urlifier.
-
-2023-11-04 David Malcolm <dmalcolm@redhat.com>
-
- * Makefile.in (GCC_OBJS): Add gcc-urlifier.o.
- (OBJS): Likewise.
-
-2023-11-04 David Malcolm <dmalcolm@redhat.com>
-
- * common.opt (fdiagnostics-text-art-charset=): Remove refererence
- to diagnostic-text-art.h.
- * coretypes.h (struct diagnostic_context): Replace forward decl
- with...
- (class diagnostic_context): ...this.
- * diagnostic-format-json.cc: Update for changes to
- diagnostic_context.
- * diagnostic-format-sarif.cc: Likewise.
- * diagnostic-show-locus.cc: Likewise.
- * diagnostic-text-art.h: Deleted file, moving content...
- (enum diagnostic_text_art_charset): ...to diagnostic.h,
- (DIAGNOSTICS_TEXT_ART_CHARSET_DEFAULT): ...deleting,
- (diagnostics_text_art_charset_init): ...deleting in favor of
- diagnostic_context::set_text_art_charset.
- * diagnostic.cc: Remove include of "diagnostic-text-art.h".
- (pedantic_warning_kind): Update for field renaming.
- (permissive_error_kind): Likewise.
- (permissive_error_option): Likewise.
- (diagnostic_initialize): Convert to...
- (diagnostic_context::initialize): ...this, updating for field
- renamings.
- (diagnostic_color_init): Convert to...
- (diagnostic_context::color_init): ...this.
- (diagnostic_urls_init): Convert to...
- (diagnostic_context::urls_init): ...this.
- (diagnostic_initialize_input_context): Convert to...
- (diagnostic_context::initialize_input_context): ...this.
- (diagnostic_finish): Convert to...
- (diagnostic_context::finish): ...this, updating for field
- renamings.
- (diagnostic_context::set_output_format): New.
- (diagnostic_context::set_client_data_hooks): New.
- (diagnostic_context::create_edit_context): New.
- (diagnostic_converted_column): Convert to...
- (diagnostic_context::converted_column): ...this.
- (diagnostic_get_location_text): Update for field renaming.
- (diagnostic_check_max_errors): Convert to...
- (diagnostic_context::check_max_errors): ...this, updating for
- field renamings.
- (diagnostic_action_after_output): Convert to...
- (diagnostic_context::action_after_output): ...this, updating for
- field renamings.
- (last_module_changed_p): Delete.
- (set_last_module): Delete.
- (includes_seen): Convert to...
- (diagnostic_context::includes_seen_p): ...this, updating for field
- renamings.
- (diagnostic_report_current_module): Convert to...
- (diagnostic_context::report_current_module): ...this, updating for
- field renamings, and replacing uses of last_module_changed_p and
- set_last_module to simple field accesses.
- (diagnostic_show_any_path): Convert to...
- (diagnostic_context::show_any_path): ...this.
- (diagnostic_classify_diagnostic): Convert to...
- (diagnostic_context::classify_diagnostic): ...this, updating for
- field renamings.
- (diagnostic_push_diagnostics): Convert to...
- (diagnostic_context::push_diagnostics): ...this, updating for field
- renamings.
- (diagnostic_pop_diagnostics): Convert to...
- (diagnostic_context::pop_diagnostics): ...this, updating for field
- renamings.
- (get_any_inlining_info): Convert to...
- (diagnostic_context::get_any_inlining_info): ...this, updating for
- field renamings.
- (update_effective_level_from_pragmas): Convert to...
- (diagnostic_context::update_effective_level_from_pragmas):
- ...this, updating for field renamings.
- (print_any_cwe): Convert to...
- (diagnostic_context::print_any_cwe): ...this.
- (print_any_rules): Convert to...
- (diagnostic_context::print_any_rules): ...this.
- (print_option_information): Convert to...
- (diagnostic_context::print_option_information): ...this, updating
- for field renamings.
- (diagnostic_enabled): Convert to...
- (diagnostic_context::diagnostic_enabled): ...this, updating for
- field renamings.
- (warning_enabled_at): Convert to...
- (diagnostic_context::warning_enabled_at): ...this.
- (diagnostic_report_diagnostic): Convert to...
- (diagnostic_context::report_diagnostic): ...this, updating for
- field renamings and conversions to member functions.
- (diagnostic_append_note): Update for field renaming.
- (diagnostic_impl): Use diagnostic_context::report_diagnostic
- directly.
- (diagnostic_n_impl): Likewise.
- (diagnostic_emit_diagram): Convert to...
- (diagnostic_context::emit_diagram): ...this, updating for field
- renamings.
- (error_recursion): Convert to...
- (diagnostic_context::error_recursion): ...this.
- (diagnostic_text_output_format::~diagnostic_text_output_format):
- Use accessor.
- (diagnostics_text_art_charset_init): Convert to...
- (diagnostic_context::set_text_art_charset): ...this.
- (assert_location_text): Update for field renamings.
- * diagnostic.h (enum diagnostic_text_art_charset): Move here from
- diagnostic-text-art.h.
- (struct diagnostic_context): Convert to...
- (class diagnostic_context): ...this.
- (diagnostic_context::ice_handler_callback_t): New typedef.
- (diagnostic_context::set_locations_callback_t): New typedef.
- (diagnostic_context::initialize): New decl.
- (diagnostic_context::color_init): New decl.
- (diagnostic_context::urls_init): New decl.
- (diagnostic_context::file_cache_init): New decl.
- (diagnostic_context::finish): New decl.
- (diagnostic_context::set_set_locations_callback): New.
- (diagnostic_context::initialize_input_context): New decl.
- (diagnostic_context::warning_enabled_at): New decl.
- (diagnostic_context::option_unspecified_p): New.
- (diagnostic_context::report_diagnostic): New decl.
- (diagnostic_context::report_current_module): New decl.
- (diagnostic_context::check_max_errors): New decl.
- (diagnostic_context::action_after_output): New decl.
- (diagnostic_context::classify_diagnostic): New decl.
- (diagnostic_context::push_diagnostics): New decl.
- (diagnostic_context::pop_diagnostics): New decl.
- (diagnostic_context::emit_diagram): New decl.
- (diagnostic_context::set_output_format): New decl.
- (diagnostic_context::set_text_art_charset): New decl.
- (diagnostic_context::set_client_data_hooks): New decl.
- (diagnostic_context::create_edit_context): New decl.
- (diagnostic_context::set_warning_as_error_requested): New.
- (diagnostic_context::set_report_bug): New.
- (diagnostic_context::set_extra_output_kind): New.
- (diagnostic_context::set_show_cwe): New.
- (diagnostic_context::set_show_rules): New.
- (diagnostic_context::set_path_format): New.
- (diagnostic_context::set_show_path_depths): New.
- (diagnostic_context::set_show_option_requested): New.
- (diagnostic_context::set_max_errors): New.
- (diagnostic_context::set_escape_format): New.
- (diagnostic_context::set_ice_handler_callback): New.
- (diagnostic_context::warning_as_error_requested_p): New.
- (diagnostic_context::show_path_depths_p): New.
- (diagnostic_context::get_path_format): New.
- (diagnostic_context::get_escape_format): New.
- (diagnostic_context::get_file_cache): New.
- (diagnostic_context::get_edit_context): New.
- (diagnostic_context::get_client_data_hooks): New.
- (diagnostic_context::get_diagram_theme): New.
- (diagnostic_context::converted_column): New decl.
- (diagnostic_context::diagnostic_count): New.
- (diagnostic_context::includes_seen_p): New decl.
- (diagnostic_context::print_any_cwe): New decl.
- (diagnostic_context::print_any_rules): New decl.
- (diagnostic_context::print_option_information): New decl.
- (diagnostic_context::show_any_path): New decl.
- (diagnostic_context::error_recursion): New decl.
- (diagnostic_context::diagnostic_enabled): New decl.
- (diagnostic_context::get_any_inlining_info): New decl.
- (diagnostic_context::update_effective_level_from_pragmas): New
- decl.
- (diagnostic_context::m_file_cache): Make private.
- (diagnostic_context::diagnostic_count): Rename to...
- (diagnostic_context::m_diagnostic_count): ...this and make
- private.
- (diagnostic_context::warning_as_error_requested): Rename to...
- (diagnostic_context::m_warning_as_error_requested): ...this and
- make private.
- (diagnostic_context::n_opts): Rename to...
- (diagnostic_context::m_n_opts): ...this and make private.
- (diagnostic_context::classify_diagnostic): Rename to...
- (diagnostic_context::m_classify_diagnostic): ...this and make
- private.
- (diagnostic_context::classification_history): Rename to...
- (diagnostic_context::m_classification_history): ...this and make
- private.
- (diagnostic_context::n_classification_history): Rename to...
- (diagnostic_context::m_n_classification_history): ...this and make
- private.
- (diagnostic_context::push_list): Rename to...
- (diagnostic_context::m_push_list): ...this and make private.
- (diagnostic_context::n_push): Rename to...
- (diagnostic_context::m_n_push): ...this and make private.
- (diagnostic_context::show_cwe): Rename to...
- (diagnostic_context::m_show_cwe): ...this and make private.
- (diagnostic_context::show_rules): Rename to...
- (diagnostic_context::m_show_rules): ...this and make private.
- (diagnostic_context::path_format): Rename to...
- (diagnostic_context::m_path_format): ...this and make private.
- (diagnostic_context::show_path_depths): Rename to...
- (diagnostic_context::m_show_path_depths): ...this and make
- private.
- (diagnostic_context::show_option_requested): Rename to...
- (diagnostic_context::m_show_option_requested): ...this and make
- private.
- (diagnostic_context::abort_on_error): Rename to...
- (diagnostic_context::m_abort_on_error): ...this.
- (diagnostic_context::show_column): Rename to...
- (diagnostic_context::m_show_column): ...this.
- (diagnostic_context::pedantic_errors): Rename to...
- (diagnostic_context::m_pedantic_errors): ...this.
- (diagnostic_context::permissive): Rename to...
- (diagnostic_context::m_permissive): ...this.
- (diagnostic_context::opt_permissive): Rename to...
- (diagnostic_context::m_opt_permissive): ...this.
- (diagnostic_context::fatal_errors): Rename to...
- (diagnostic_context::m_fatal_errors): ...this.
- (diagnostic_context::dc_inhibit_warnings): Rename to...
- (diagnostic_context::m_inhibit_warnings): ...this.
- (diagnostic_context::dc_warn_system_headers): Rename to...
- (diagnostic_context::m_warn_system_headers): ...this.
- (diagnostic_context::max_errors): Rename to...
- (diagnostic_context::m_max_errors): ...this and make private.
- (diagnostic_context::internal_error): Rename to...
- (diagnostic_context::m_internal_error): ...this.
- (diagnostic_context::option_enabled): Rename to...
- (diagnostic_context::m_option_enabled): ...this.
- (diagnostic_context::option_state): Rename to...
- (diagnostic_context::m_option_state): ...this.
- (diagnostic_context::option_name): Rename to...
- (diagnostic_context::m_option_name): ...this.
- (diagnostic_context::get_option_url): Rename to...
- (diagnostic_context::m_get_option_url): ...this.
- (diagnostic_context::print_path): Rename to...
- (diagnostic_context::m_print_path): ...this.
- (diagnostic_context::make_json_for_path): Rename to...
- (diagnostic_context::m_make_json_for_path): ...this.
- (diagnostic_context::x_data): Rename to...
- (diagnostic_context::m_client_aux_data): ...this.
- (diagnostic_context::last_location): Rename to...
- (diagnostic_context::m_last_location): ...this.
- (diagnostic_context::last_module): Rename to...
- (diagnostic_context::m_last_module): ...this and make private.
- (diagnostic_context::lock): Rename to...
- (diagnostic_context::m_lock): ...this and make private.
- (diagnostic_context::lang_mask): Rename to...
- (diagnostic_context::m_lang_mask): ...this.
- (diagnostic_context::inhibit_notes_p): Rename to...
- (diagnostic_context::m_inhibit_notes_p): ...this.
- (diagnostic_context::report_bug): Rename to...
- (diagnostic_context::m_report_bug): ...this and make private.
- (diagnostic_context::extra_output_kind): Rename to...
- (diagnostic_context::m_extra_output_kind): ...this and make
- private.
- (diagnostic_context::column_unit): Rename to...
- (diagnostic_context::m_column_unit): ...this and make private.
- (diagnostic_context::column_origin): Rename to...
- (diagnostic_context::m_column_origin): ...this and make private.
- (diagnostic_context::tabstop): Rename to...
- (diagnostic_context::m_tabstop): ...this and make private.
- (diagnostic_context::escape_format): Rename to...
- (diagnostic_context::m_escape_format): ...this and make private.
- (diagnostic_context::edit_context_ptr): Rename to...
- (diagnostic_context::m_edit_context_ptr): ...this and make
- private.
- (diagnostic_context::set_locations_cb): Rename to...
- (diagnostic_context::m_set_locations_cb): ...this and make
- private.
- (diagnostic_context::ice_handler_cb): Rename to...
- (diagnostic_context::m_ice_handler_cb): ...this and make private.
- (diagnostic_context::includes_seen): Rename to...
- (diagnostic_context::m_includes_seen): ...this and make private.
- (diagnostic_inhibit_notes): Update for field renaming.
- (diagnostic_context_auxiliary_data): Likewise.
- (diagnostic_abort_on_error): Convert from macro to inline function
- and update for field renaming.
- (diagnostic_kind_count): Convert from macro to inline function and
- use diagnostic_count accessor.
- (diagnostic_report_warnings_p): Update for field renaming.
- (diagnostic_initialize): Convert decl to inline function calling
- into diagnostic_context.
- (diagnostic_color_init): Likewise.
- (diagnostic_urls_init): Likewise.
- (diagnostic_urls_init): Likewise.
- (diagnostic_finish): Likewise.
- (diagnostic_report_current_module): Likewise.
- (diagnostic_show_any_path): Delete decl.
- (diagnostic_initialize_input_context): Convert decl to inline
- function calling into diagnostic_context.
- (diagnostic_classify_diagnostic): Likewise.
- (diagnostic_push_diagnostics): Likewise.
- (diagnostic_pop_diagnostics): Likewise.
- (diagnostic_report_diagnostic): Likewise.
- (diagnostic_action_after_output): Likewise.
- (diagnostic_check_max_errors): Likewise.
- (diagnostic_file_cache_fini): Delete decl.
- (diagnostic_converted_column): Delete decl.
- (warning_enabled_at): Convert decl to inline function calling into
- diagnostic_context.
- (option_unspecified_p): New.
- (diagnostic_emit_diagram): Delete decl.
- * gcc.cc: Remove include of "diagnostic-text-art.h".
- Update for changes to diagnostic_context.
- * input.cc (diagnostic_file_cache_init): Move implementation
- to...
- (diagnostic_context::file_cache_init): ...this new member
- function.
- (diagnostic_file_cache_fini): Delete.
- (diagnostics_file_cache_forcibly_evict_file): Update for
- m_file_cache becoming private.
- (location_get_source_line): Likewise.
- (get_source_file_content): Likewise.
- (location_missing_trailing_newline): Likewise.
- * input.h (diagnostics_file_cache_fini): Delete.
- * langhooks.cc: Update for changes to diagnostic_context.
- * lto-wrapper.cc: Likewise.
- * opts.cc: Remove include of "diagnostic-text-art.h".
- Update for changes to diagnostic_context.
- * selftest-diagnostic.cc: Update for changes to
- diagnostic_context.
- * toplev.cc: Likewise.
- * tree-diagnostic-path.cc: Likewise.
- * tree-diagnostic.cc: Likewise.
-
-2023-11-03 Martin Uecker <uecker@tugraz.at>
-
- PR c/98541
- * gimple-ssa-warn-access.cc
- (pass_waccess::maybe_check_access_sizes): For VLA bounds
- in parameters, only warn about null pointers with 'static'.
-
-2023-11-03 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Allow unmasked
- calls to use masked simdclones.
-
-2023-11-03 David Malcolm <dmalcolm@redhat.com>
-
- * diagnostic.cc (diagnostic_initialize): Update for consolidation
- of group-based fields.
- (diagnostic_report_diagnostic): Likewise.
- (diagnostic_context::begin_group): New, based on body of
- auto_diagnostic_group's ctor.
- (diagnostic_context::end_group): New, based on body of
- auto_diagnostic_group's dtor.
- (auto_diagnostic_group::auto_diagnostic_group): Convert to a call
- to begin_group.
- (auto_diagnostic_group::~auto_diagnostic_group): Convert to a call
- to end_group.
- * diagnostic.h (diagnostic_context::begin_group): New decl.
- (diagnostic_context::end_group): New decl.
- (diagnostic_context::diagnostic_group_nesting_depth): Rename to...
- (diagnostic_context::m_diagnostic_groups.m_nesting_depth):
- ...this.
- (diagnostic_context::diagnostic_group_emission_count): Rename
- to...
- (diagnostic_context::m_diagnostic_groups::m_emission_count):
- ...this.
-
-2023-11-03 Andrew MacLeod <amacleod@redhat.com>
-
- PR tree-optimization/111766
- * range-op.cc (operator_equal::fold_range): Check constants
- against the bitmask.
- (operator_not_equal::fold_range): Ditto.
- * value-range.h (irange_bitmask::member_p): New.
-
-2023-11-03 Andrew MacLeod <amacleod@redhat.com>
-
- * value-range.cc (irange_bitmask::adjust_range): New.
- (irange::intersect_bitmask): Call adjust_range.
- * value-range.h (irange_bitmask::adjust_range): New prototype.
-
-2023-11-03 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
- Rename to ...
- (ix86_memory_address_reg_class): ... this. Generalize address
- register class handling to allow multiple address register classes.
- Return maximal class for unrecognized instructions. Improve comments.
- (ix86_insn_base_reg_class): Rewrite to handle
- multiple address register classes.
- (ix86_regno_ok_for_insn_base_p): Ditto.
- (ix86_insn_index_reg_class): Ditto.
- * config/i386/i386.md: Rename "gpr32" attribute to "addr"
- and substitute its values with "0" -> "gpr16", "1" -> "*".
- (addr): New attribute to limit allowed address register set.
- (gpr32): Remove.
- * config/i386/mmx.md: Rename "gpr32" attribute to "addr"
- and substitute its values with "0" -> "gpr16", "1" -> "*".
- * config/i386/sse.md: Ditto.
-
-2023-11-03 Richard Biener <rguenther@suse.de>
-
- * tree-vect-loop.cc (vectorizable_live_operation): Simplify
- LC PHI replacement.
-
-2023-11-03 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.md (addsi3): Fix GNU-style code formatting.
- (adddi3): Change define_expand to generate a *adddi3.
- (*adddi3): New define_insn_and_split to lower DImode additions
- during the split1 pass (after combine and before reload).
- (ashldi3): New define_expand to (only) generate *ashldi3_cnt1
- for DImode left shifts by a single bit.
- (*ashldi3_cnt1): New define_insn_and_split to lower DImode
- left shifts by one bit to an *adddi3.
-
-2023-11-03 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.md (*cmov_uxtw_insn_insv): Remove
- can_create_pseudo_p condition.
-
-2023-11-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-slp.cc (vect_get_and_check_slp_defs): Support SLP for dummy mask -1.
- * tree-vect-stmts.cc (vectorizable_load): Ditto.
-
-2023-11-03 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112366
- * tree-vect-loop.cc (vectorizable_live_operation): Remove
- assert.
-
-2023-11-03 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112310
- * tree-ssa-pre.cc (do_hoist_insertion): Keep the union
- of expressions, validate dependences are contained within
- the hoistable set before hoisting.
-
-2023-11-03 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (lrint<mode><v_i_l_ll_convert>2): Remove.
- (lround<mode><v_i_l_ll_convert>2): Ditto.
- (lceil<mode><v_i_l_ll_convert>2): Ditto.
- (lfloor<mode><v_i_l_ll_convert>2): Ditto.
- (lrint<mode><v_f2si_convert>2): New pattern for cvt from
- FP to SI.
- (lround<mode><v_f2si_convert>2): Ditto.
- (lceil<mode><v_f2si_convert>2): Ditto.
- (lfloor<mode><v_f2si_convert>2): Ditto.
- (lrint<mode><v_f2di_convert>2): New pattern for cvt from
- FP to DI.
- (lround<mode><v_f2di_convert>2): Ditto.
- (lceil<mode><v_f2di_convert>2): Ditto.
- (lfloor<mode><v_f2di_convert>2): Ditto.
- * config/riscv/vector-iterators.md: Renew iterators for both
- the SI and DI.
-
-2023-11-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112326
- * config/riscv/riscv-avlprop.cc (get_insn_vtype_mode): New function.
- (simplify_replace_vlmax_avl): Ditto.
- (pass_avlprop::execute): Add immediate AVL simplification.
- * config/riscv/riscv-protos.h (imm_avl_p): Rename.
- * config/riscv/riscv-v.cc (const_vlmax_p): Ditto.
- (imm_avl_p): Ditto.
- (emit_vlmax_insn): Adapt for new interface name.
- * config/riscv/vector.md (mode_idx): New attribute.
-
-2023-11-03 Pan Li <pan2.li@intel.com>
-
- Revert:
- 2023-11-02 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (lrint<mode><v_i_l_ll_convert>2): Remove.
- (lround<mode><v_i_l_ll_convert>2): Ditto.
- (lceil<mode><v_i_l_ll_convert>2): Ditto.
- (lfloor<mode><v_i_l_ll_convert>2): Ditto.
- (lrint<mode><v_f2si_convert>2): New pattern for cvt from
- FP to SI.
- (lround<mode><v_f2si_convert>2): Ditto.
- (lceil<mode><v_f2si_convert>2): Ditto.
- (lfloor<mode><v_f2si_convert>2): Ditto.
- (lrint<mode><v_f2di_convert>2): New pattern for cvt from
- FP to DI.
- (lround<mode><v_f2di_convert>2): Ditto.
- (lceil<mode><v_f2di_convert>2): Ditto.
- (lfloor<mode><v_f2di_convert>2): Ditto.
- * config/riscv/vector-iterators.md: Renew iterators for both
- the SI and DI.
-
-2023-11-02 Edwin Lu <ewlu@rivosinc.com>
-
- * config/riscv/riscv.cc (riscv_sched_variable_issue): add disabled assert
-
-2023-11-02 Jeff Law <jlaw@ventanamicro.com>
-
- * config/h8300/combiner.md: Add new patterns for single bit
- sign extractions.
-
-2023-11-02 Pan Li <pan2.li@intel.com>
-
- * config/riscv/autovec.md (lrint<mode><v_i_l_ll_convert>2): Remove.
- (lround<mode><v_i_l_ll_convert>2): Ditto.
- (lceil<mode><v_i_l_ll_convert>2): Ditto.
- (lfloor<mode><v_i_l_ll_convert>2): Ditto.
- (lrint<mode><v_f2si_convert>2): New pattern for cvt from
- FP to SI.
- (lround<mode><v_f2si_convert>2): Ditto.
- (lceil<mode><v_f2si_convert>2): Ditto.
- (lfloor<mode><v_f2si_convert>2): Ditto.
- (lrint<mode><v_f2di_convert>2): New pattern for cvt from
- FP to DI.
- (lround<mode><v_f2di_convert>2): Ditto.
- (lceil<mode><v_f2di_convert>2): Ditto.
- (lfloor<mode><v_f2di_convert>2): Ditto.
- * config/riscv/vector-iterators.md: Renew iterators for both
- the SI and DI.
-
-2023-11-02 Sam James <sam@gentoo.org>
-
- * doc/passes.texi (Dead code elimination): Explicitly say 'lifetime'
- as this has become the standard term for what we're doing here.
-
-2023-11-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-avlprop.cc
- (pass_avlprop::get_vlmax_ta_preferred_avl): Don't allow
- non-real insn AVL propation.
-
-2023-11-02 Robin Dapp <rdapp@ventanamicro.com>
-
- PR middle-end/111401
- * internal-fn.cc (internal_fn_else_index): New function.
- * internal-fn.h (internal_fn_else_index): Define.
- * tree-if-conv.cc (convert_scalar_cond_reduction): Emit COND_OP
- if supported.
- (predicate_scalar_phi): Add whitespace.
- * tree-vect-loop.cc (fold_left_reduction_fn): Add IFN_COND_OP.
- (neutral_op_for_reduction): Return -0 for PLUS.
- (check_reduction_path): Don't count else operand in COND_OP.
- (vect_is_simple_reduction): Ditto.
- (vect_create_epilog_for_reduction): Fix whitespace.
- (vectorize_fold_left_reduction): Add COND_OP handling.
- (vectorizable_reduction): Don't count else operand in COND_OP.
- (vect_transform_reduction): Add COND_OP handling.
- * tree-vectorizer.h (neutral_op_for_reduction): Add default
- parameter.
-
-2023-11-02 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112320
- * gimple-fold.h (rewrite_to_defined_overflow): New overload
- for in-place operation.
- * gimple-fold.cc (rewrite_to_defined_overflow): Add stmt
- iterator argument to worker, define separate API for
- in-place and not in-place operation.
- * tree-if-conv.cc (predicate_statements): Simplify.
- * tree-scalar-evolution.cc (final_value_replacement_loop):
- Likewise.
- * tree-ssa-ifcombine.cc (pass_tree_ifcombine::execute): Adjust.
- * tree-ssa-reassoc.cc (update_range_test): Likewise.
-
-2023-11-02 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md: Move stack protector patterns
- above mov $0,%reg -> xor %reg,%reg peephole2 pattern.
-
-2023-11-02 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/mmx.md (cmlav4hf4): New expander.
- (cmla_conjv4hf4): Ditto.
- (cmulv4hf3): Ditto.
- (cmul_conjv4hf3): Ditto.
-
-2023-11-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix redundant codes in attributes.
-
-2023-11-02 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-bases.cc: Expand non-tuple intrinsics.
- * config/riscv/riscv-vector-builtins-functions.def (vcreate): Define non-tuple intrinsics.
- * config/riscv/riscv-vector-builtins-shapes.cc (struct vcreate_def): Ditto.
- * config/riscv/riscv-vector-builtins.cc: Add arg types.
-
-2023-11-02 Pan Li <pan2.li@intel.com>
-
- * tree-vect-stmts.cc (vectorizable_internal_function): Add type
- size check for vectype_out doesn't participating for optab query.
- (vectorizable_call): Remove the type size check.
-
-2023-11-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/112327
- * config/riscv/vector.md: Add '0'.
-
-2023-11-01 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/110551
- * config/i386/i386.md (*bmi2_umul<mode><dwi>3_1): Tidy condition
- as operands[2] with predicate register_operand must be !MEM_P.
- (peephole2): Optimize a mulx followed by a register-to-register
- move, to place result in the correct destination if possible.
-
-2023-11-01 Patrick O'Neill <patrick@rivosinc.com>
-
- * config/riscv/sync.md: Use riscv_subword_address function to
- calculate the address and shift in atomic_test_and_set.
-
-2023-11-01 Vineet Gupta <vineetg@rivosinc.com>
-
- * config/riscv/riscv.cc (riscv_promote_function_mode): Fix mode
- returned for libcall case.
-
-2023-11-01 Martin Uecker <uecker@tugraz.at>
-
- PR c/71219
- * doc/invoke.texi: Document -Walloc-size option.
-
-2023-11-01 Edwin Lu <ewlu@rivosinc.com>
-
- * genautomata.cc (write_automata): move endif
-
-2023-11-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * omp-simd-clone.cc (simd_clone_adjust_return_type): Hoist out code to
- create return array and don't return new type.
- (simd_clone_adjust_argument_types): Hoist out code that creates
- ipa_param_body_adjustments and don't return them.
- (simd_clone_adjust): Call TARGET_SIMD_CLONE_ADJUST after return and
- argument types have been vectorized, create adjustments and return array
- after the hook.
- (expand_simd_clones): Call TARGET_SIMD_CLONE_ADJUST after return and
- argument types have been vectorized.
-
-2023-11-01 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/112332
- * config/i386/i386.md (stack_protexct_set_2 peephole2):
- Use general_gr_operand as operand 4 predicate.
-
-2023-11-01 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/i386.md (stack_protect_set): Explicitly
- generate scratch register in word mode.
- (@stack_protect_set_1_<mode>): Rename to ...
- (@stack_protect_set_1_<PTR:mode>_<SWI48:mode>): ... this.
- Use SWI48 mode iterator to match scratch register.
- (stack_protexct_set_1 peephole2): Use PTR, W and SWI48 mode
- iterators to match peephole sequence. Use general_operand
- predicate for operand 4. Allow different operand 2 and operand 3
- registers and use peep2_reg_dead_p to ensure new scratch
- register is dead before peephole seqeunce. Use peep2_reg_dead_p
- to ensure old scratch register is dead after peephole sequence.
- (*stack_protect_set_2_<mode>): Rename to ...
- (*stack_protect_set_2_<mode>_si): .. this.
- (*stack_protect_set_3): Rename to ...
- (*stack_protect_set_2_<mode>_di): ... this.
- Use PTR mode iterator to match stack protector memory move.
- Use earlyclobber for all alternatives of operand 1.
- (stack_protexct_set_2 peephole2): Use PTR, W and SWI48 mode
- iterators to match peephole sequence. Use general_operand
- predicate for operand 4. Allow different operand 2 and operand 3
- registers and use peep2_reg_dead_p to ensure new scratch
- register is dead before peephole seqeunce. Use peep2_reg_dead_p
- to ensure old scratch register is dead after peephole sequence.
-
-2023-11-01 xuli <xuli1@eswincomputing.com>
-
- * config/riscv/riscv-vector-builtins-functions.def (vundefined): Add vundefine
- intrinsics for tuple types.
- * config/riscv/riscv-vector-builtins.cc: Ditto.
- * config/riscv/vector.md (@vundefined<mode>): Ditto.
-
-2023-11-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-slp.cc (vect_build_slp_tree_1): Fix whitespace.
-
-2023-10-31 David Malcolm <dmalcolm@redhat.com>
-
- * Makefile.in (ANALYZER_OBJS): Add analyzer/record-layout.o.
-
-2023-10-31 David Malcolm <dmalcolm@redhat.com>
-
- * input.cc (dump_location_info): Update for removal of
- MACRO_MAP_EXPANSION_POINT_LOCATION.
- * tree-diagnostic.cc (maybe_unwind_expanded_macro_loc):
- Likewise.
-
-2023-10-31 David Malcolm <dmalcolm@redhat.com>
-
- * opts.cc (get_option_url): Update comment; the requirement to
- pass DOCUMENTATION_ROOT_URL's value via -D was removed in
- r10-8065-ge33a1eae25b8a8.
-
-2023-10-31 David Malcolm <dmalcolm@redhat.com>
-
- * pretty-print.cc (pretty_printer::pretty_printer): Initialize
- m_skipping_null_url.
- (pp_begin_url): Handle URL being null.
- (pp_end_url): Likewise.
- (selftest::test_null_urls): New.
- (selftest::pretty_print_cc_tests): Call it.
- * pretty-print.h (pretty_printer::m_skipping_null_url): New.
-
-2023-10-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * tree-vect-slp.cc (vect_get_operand_map): Add MASK_LEN_GATHER_LOAD.
- (vect_build_slp_tree_1): Ditto.
- (vect_build_slp_tree_2): Ditto.
-
-2023-10-31 Cupertino Miranda <cupertino.miranda@oracle.com>
-
- * config/bpf/bpf-passes.def (pass_lower_bpf_core): Added pass.
- * config/bpf/bpf-protos.h: Added prototype for new pass.
- * config/bpf/bpf.cc (bpf_delegitimize_address): New function.
- * config/bpf/bpf.md (mov_reloc_core<MM:mode>): Prefixed
- name with '*'.
- * config/bpf/core-builtins.cc (cr_builtins) Added access_node to
- struct.
- (is_attr_preserve_access): Improved check.
- (core_field_info): Make use of root_for_core_field_info
- function.
- (process_field_expr): Adapted to new functions.
- (pack_type): Small improvement.
- (bpf_handle_plugin_finish_type): Adapted to GTY(()).
- (bpf_init_core_builtins): Changed to new function names.
- (construct_builtin_core_reloc): Improved implementation.
- (bpf_resolve_overloaded_core_builtin): Changed how
- __builtin_preserve_access_index is converted.
- (compute_field_expr): Corrected implementation. Added
- access_node argument.
- (bpf_core_get_index): Added valid argument.
- (root_for_core_field_info, pack_field_expr)
- (core_expr_with_field_expr_plus_base, make_core_safe_access_index)
- (replace_core_access_index_comp_expr, maybe_get_base_for_field_expr)
- (core_access_clean, core_is_access_index, core_mark_as_access_index)
- (make_gimple_core_safe_access_index, execute_lower_bpf_core)
- (make_pass_lower_bpf_core): Added functions.
- (pass_data_lower_bpf_core): New pass struct.
- (pass_lower_bpf_core): New gimple_opt_pass class.
- (pack_field_expr_for_preserve_field)
- (bpf_replace_core_move_operands): Removed function.
- (bpf_enum_value_kind): Added GTY(()).
- * config/bpf/core-builtins.h (bpf_field_info_kind, bpf_type_id_kind)
- (bpf_type_info_kind, bpf_enum_value_kind): New enum.
- * config/bpf/t-bpf: Added pass bpf-passes.def to PASSES_EXTRA.
-
-2023-10-31 Neal Frager <neal.frager@amd.com>
-
- * config/microblaze/microblaze.cc: Fix mcpu version check.
-
-2023-10-31 Patrick O'Neill <patrick@rivosinc.com>
-
- * config/riscv/sync-rvwmo.md (atomic_load_rvwmo<mode>): Remove
- TARGET_ATOMIC constraint
- (atomic_store_rvwmo<mode>): Ditto.
- * config/riscv/sync-ztso.md (atomic_load_ztso<mode>): Ditto.
- (atomic_store_ztso<mode>): Ditto.
- * config/riscv/sync.md (atomic_load<mode>): Ditto.
- (atomic_store<mode>): Ditto.
-
-2023-10-31 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/riscv.cc (riscv_index_reg_class):
- Return GR_REGS for XTheadFMemIdx.
- (riscv_regno_ok_for_index_p): Add support for XTheadFMemIdx.
- * config/riscv/riscv.h (HARDFP_REG_P): New macro.
- * config/riscv/thead.cc (is_fmemidx_mode): New function.
- (th_memidx_classify_address_index): Add support for XTheadFMemIdx.
- (th_fmemidx_output_index): New function.
- (th_output_move): Add support for XTheadFMemIdx.
- * config/riscv/thead.md (TH_M_ANYF): New mode iterator.
- (TH_M_NOEXTF): Likewise.
- (*th_fmemidx_movsf_hardfloat): New INSN.
- (*th_fmemidx_movdf_hardfloat_rv64): Likewise.
- (*th_fmemidx_I_a): Likewise.
- (*th_fmemidx_I_c): Likewise.
- (*th_fmemidx_US_a): Likewise.
- (*th_fmemidx_US_c): Likewise.
- (*th_fmemidx_UZ_a): Likewise.
- (*th_fmemidx_UZ_c): Likewise.
-
-2023-10-31 Christoph Müllner <christoph.muellner@vrull.eu>
-
- * config/riscv/constraints.md (th_m_mia): New constraint.
- (th_m_mib): Likewise.
- (th_m_mir): Likewise.
- (th_m_miu): Likewise.
- * config/riscv/riscv-protos.h (enum riscv_address_type):
- Add new address types ADDRESS_REG_REG, ADDRESS_REG_UREG,
- and ADDRESS_REG_WB and their documentation.
- (struct riscv_address_info): Add new field 'shift' and
- document the field usage for the new address types.
- (riscv_valid_base_register_p): New prototype.
- (th_memidx_legitimate_modify_p): Likewise.
- (th_memidx_legitimate_index_p): Likewise.
- (th_classify_address): Likewise.
- (th_output_move): Likewise.
- (th_print_operand_address): Likewise.
- * config/riscv/riscv.cc (riscv_index_reg_class):
- Return GR_REGS for XTheadMemIdx.
- (riscv_regno_ok_for_index_p): Add support for XTheadMemIdx.
- (riscv_classify_address): Call th_classify_address() on top.
- (riscv_output_move): Call th_output_move() on top.
- (riscv_print_operand_address): Call th_print_operand_address()
- on top.
- * config/riscv/riscv.h (HAVE_POST_MODIFY_DISP): New macro.
- (HAVE_PRE_MODIFY_DISP): Likewise.
- * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2): Disable
- for XTheadMemIdx.
- (*zero_extendqi<SUPERQI:mode>2_internal): Convert to expand,
- create INSN with same name and disable it for XTheadMemIdx.
- (extendsidi2): Likewise.
- (*extendsidi2_internal): Disable for XTheadMemIdx.
- * config/riscv/thead.cc (valid_signed_immediate): New helper
- function.
- (th_memidx_classify_address_modify): New function.
- (th_memidx_legitimate_modify_p): Likewise.
- (th_memidx_output_modify): Likewise.
- (is_memidx_mode): Likewise.
- (th_memidx_classify_address_index): Likewise.
- (th_memidx_legitimate_index_p): Likewise.
- (th_memidx_output_index): Likewise.
- (th_classify_address): Likewise.
- (th_output_move): Likewise.
- (th_print_operand_address): Likewise.
- * config/riscv/thead.md (*th_memidx_operand): New splitter.
- (*th_memidx_zero_extendqi<SUPERQI:mode>2): New INSN.
- (*th_memidx_extendsidi2): Likewise.
- (*th_memidx_zero_extendsidi2): Likewise.
- (*th_memidx_zero_extendhi<GPR:mode>2): Likewise.
- (*th_memidx_extend<SHORT:mode><SUPERQI:mode>2): Likewise.
- (*th_memidx_bb_zero_extendsidi2): Likewise.
- (*th_memidx_bb_zero_extendhi<GPR:mode>2): Likewise.
- (*th_memidx_bb_extendhi<GPR:mode>2): Likewise.
- (*th_memidx_bb_extendqi<SUPERQI:mode>2): Likewise.
- (TH_M_ANYI): New mode iterator.
- (TH_M_NOEXTI): Likewise.
- (*th_memidx_I_a): New combiner optimization.
- (*th_memidx_I_b): Likewise.
- (*th_memidx_I_c): Likewise.
- (*th_memidx_US_a): Likewise.
- (*th_memidx_US_b): Likewise.
- (*th_memidx_US_c): Likewise.
- (*th_memidx_UZ_a): Likewise.
- (*th_memidx_UZ_b): Likewise.
- (*th_memidx_UZ_c): Likewise.
-
-2023-10-31 Carl Love <cel@us.ibm.com>
-
- * doc/extend.texi (__builtin_bcdsub_le, __builtin_bcdsub_ge): Add
- documentation for the builti-ins.
-
-2023-10-31 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/111971
- * lra-constraints.cc: (process_alt_operands): Don't check start
- hard regs for regs originated from register variables.
-
-2023-10-31 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (<ieee_fmaxmin_op><mode>3): fmax/fmin
- expanders.
- (cond_<ieee_fmaxmin_op><mode>): Ditto.
- (cond_len_<ieee_fmaxmin_op><mode>): Ditto.
- (reduc_fmax_scal_<mode>): Ditto.
- (reduc_fmin_scal_<mode>): Ditto.
- * config/riscv/riscv-v.cc (needs_fp_rounding): Add fmin/fmax.
- * config/riscv/vector-iterators.md (fmin): New UNSPEC.
- (UNSPEC_VFMIN): Ditto.
- * config/riscv/vector.md (@pred_<ieee_fmaxmin_op><mode>): Add
- UNSPEC insn patterns.
- (@pred_<ieee_fmaxmin_op><mode>_scalar): Ditto.
-
-2023-10-31 Robin Dapp <rdapp@ventanamicro.com>
-
- PR bootstrap/84402
- PR target/111600
- * Makefile.in: Handle split insn-emit.cc.
- * configure: Regenerate.
- * configure.ac: Add --with-insnemit-partitions.
- * genemit.cc (output_peephole2_scratches): Print to file instead
- of stdout.
- (print_code): Ditto.
- (gen_rtx_scratch): Ditto.
- (gen_exp): Ditto.
- (gen_emit_seq): Ditto.
- (emit_c_code): Ditto.
- (gen_insn): Ditto.
- (gen_expand): Ditto.
- (gen_split): Ditto.
- (output_add_clobbers): Ditto.
- (output_added_clobbers_hard_reg_p): Ditto.
- (print_overload_arguments): Ditto.
- (print_overload_test): Ditto.
- (handle_overloaded_code_for): Ditto.
- (handle_overloaded_gen): Ditto.
- (print_header): New function.
- (handle_arg): New function.
- (main): Split output into 10 files.
- * gensupport.cc (count_patterns): New function.
- * gensupport.h (count_patterns): Define.
- * read-md.cc (md_reader::print_md_ptr_loc): Add file argument.
- * read-md.h (class md_reader): Change definition.
-
-2023-10-31 Alexandre Oliva <oliva@adacore.com>
-
- PR tree-optimization/111943
- * gimple-harden-control-flow.cc: Adjust copyright year.
- (rt_bb_visited): Add vfalse and vtrue data members.
- Zero-initialize them in the ctor.
- (rt_bb_visited::insert_exit_check_on_edge): Upon encountering
- abnormal edges, insert initializers for vfalse and vtrue on
- entry, and insert the check sequence guarded by a conditional
- in the dest block.
-
-2023-10-31 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/112305
- * tree-scalar-evolution.h (expression_expensive): Adjust.
- * tree-scalar-evolution.cc (expression_expensive): Record
- when we see a COND_EXPR.
- (final_value_replacement_loop): When the replacement contains
- a COND_EXPR, rewrite it to defined overflow.
- * tree-ssa-loop-ivopts.cc (may_eliminate_iv): Adjust.
-
-2023-10-31 Xi Ruoyao <xry111@xry111.site>
-
- PR target/112299
- * config/loongarch/loongarch-opts.h (HAVE_AS_TLS): Define to 0
- if not defined yet.
-
-2023-10-31 Lehua Ding <lehua.ding@rivai.ai>
-
- * gimple-match.h (gimple_match_op::gimple_match_op):
- Add interfaces for more arguments.
- (gimple_match_op::set_op): Add interfaces for more arguments.
- * match.pd: Add support of combining cond_len_op + vec_cond
-
-2023-10-31 Haochen Jiang <haochen.jiang@intel.com>
-
- * config/i386/avx512cdintrin.h (target): Push evex512 for
- avx512cd.
- * config/i386/avx512vlintrin.h (target): Split avx512cdvl part
- out from avx512vl.
- * config/i386/i386-builtin.def (BDESC): Do not check evex512
- for builtins not needed.
-
-2023-10-31 Lehua Ding <lehua.ding@rivai.ai>
-
- * config/riscv/autovec.md (<float_cvt><mode><vnnconvert>2):
- Change to define_expand.
-
-2023-10-31 liuhongt <hongtao.liu@intel.com>
-
- PR target/112276
- * config/i386/mmx.md (*mmx_pblendvb_v8qi_1): Change
- define_split to define_insn_and_split to handle
- immediate_operand for comparison.
- (*mmx_pblendvb_v8qi_2): Ditto.
- (*mmx_pblendvb_<mode>_1): Ditto.
- (*mmx_pblendvb_v4qi_2): Ditto.
- (<code><mode>3): Remove define_split after it.
- (<code>v8qi3): Ditto.
- (<code><mode>3): Ditto.
- (<ode>v2hi3): Ditto.
-
-2023-10-31 Andrew Pinski <pinskia@gmail.com>
-
- * match.pd (`a == 1 ? b : a OP b`): New pattern.
- (`a == -1 ? b : a & b`): New pattern.
-
-2023-10-31 Andrew Pinski <pinskia@gmail.com>
-
- * match.pd: (`a == 0 ? b : b + a`,
- `a == 0 ? b : b - a`): New patterns.
-
-2023-10-31 Neal Frager <neal.frager@amd.com>
-
- * config/microblaze/microblaze.cc: Fix mcpu version check.
-
-2023-10-30 Mayshao <mayshao-oc@zhaoxin.com>
-
- * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Recognize yongfeng.
- * common/config/i386/i386-common.cc: Add yongfeng.
- * common/config/i386/i386-cpuinfo.h (enum processor_subtypes):
- Add ZHAOXIN_FAM7H_YONGFENG.
- * config.gcc: Add yongfeng.
- * config/i386/driver-i386.cc (host_detect_local_cpu):
- Let -march=native recognize yongfeng processors.
- * config/i386/i386-c.cc (ix86_target_macros_internal): Add yongfeng.
- * config/i386/i386-options.cc (m_YONGFENG): New definition.
- (m_ZHAOXIN): Ditto.
- * config/i386/i386.h (enum processor_type): Add PROCESSOR_YONGFENG.
- * config/i386/i386.md: Add yongfeng.
- * config/i386/lujiazui.md: Fix typo.
- * config/i386/x86-tune-costs.h (struct processor_costs):
- Add yongfeng costs.
- * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add yongfeng.
- (ix86_adjust_cost): Ditto.
- * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Replace
- m_LUJIAZUI with m_ZHAOXIN.
- (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto.
- (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto.
- (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto.
- (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto.
- (X86_TUNE_MOVX): Ditto.
- (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto.
- (X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto.
- (X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto.
- (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto.
- (X86_TUNE_FUSE_ALU_AND_BRANCH): Ditto.
- (X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Ditto.
- (X86_TUNE_USE_LEAVE): Ditto.
- (X86_TUNE_PUSH_MEMORY): Ditto.
- (X86_TUNE_LCP_STALL): Ditto.
- (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto.
- (X86_TUNE_OPT_AGU): Ditto.
- (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto.
- (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto.
- (X86_TUNE_USE_SAHF): Ditto.
- (X86_TUNE_USE_BT): Ditto.
- (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto.
- (X86_TUNE_ONE_IF_CONV_INSN): Ditto.
- (X86_TUNE_AVOID_MFENCE): Ditto.
- (X86_TUNE_EXPAND_ABS): Ditto.
- (X86_TUNE_USE_SIMODE_FIOP): Ditto.
- (X86_TUNE_USE_FFREEP): Ditto.
- (X86_TUNE_EXT_80387_CONSTANTS): Ditto.
- (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto.
- (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto.
- (X86_TUNE_SSE_TYPELESS_STORES): Ditto.
- (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto.
- (X86_TUNE_USE_GATHER_2PARTS): Add m_YONGFENG.
- (X86_TUNE_USE_GATHER_4PARTS): Ditto.
- (X86_TUNE_USE_GATHER_8PARTS): Ditto.
- (X86_TUNE_AVOID_128FMA_CHAINS): Ditto.
- * doc/extend.texi: Add details about yongfeng.
- * doc/invoke.texi: Ditto.
- * config/i386/yongfeng.md: New file to describe yongfeng processor.
-
-2023-10-30 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/111157
- * ipa-prop.h (struct ipa_argagg_value): Newf flag killed.
- * ipa-modref.cc (ipcp_argagg_and_kill_overlap_p): New function.
- (update_signature): Mark any any IPA-CP aggregate constants at
- positions known to be killed as killed. Move check that there is
- clone_info after this pruning.
- * ipa-cp.cc (ipa_argagg_value_list::dump): Dump the killed flag.
- (ipa_argagg_value_list::push_adjusted_values): Clear the new flag.
- (push_agg_values_from_plats): Likewise.
- (ipa_push_agg_values_from_jfunc): Likewise.
- (estimate_local_effects): Likewise.
- (push_agg_values_for_index_from_edge): Likewise.
- * ipa-prop.cc (write_ipcp_transformation_info): Stream the killed
- flag.
- (read_ipcp_transformation_info): Likewise.
- (ipcp_get_aggregate_const): Update comment, assert that encountered
- record does not have killed flag set.
- (ipcp_transform_function): Prune all aggregate constants with killed
- set.
-
-2023-10-30 Martin Jambor <mjambor@suse.cz>
-
- PR ipa/111157
- * ipa-prop.h (ipcp_transformation): New member function template
- remove_argaggs_if.
- * ipa-sra.cc (zap_useless_ipcp_results): Use remove_argaggs_if to
- filter aggreagate constants.
-
-2023-10-30 Roger Sayle <roger@nextmovesoftware.com>
-
- PR middle-end/101955
- * config/arc/arc.md (*extvsi_1_0): New define_insn_and_split
- to convert sign extract of the least significant bit into an
- AND $1 then a NEG when !TARGET_BARREL_SHIFTER.
-
-2023-10-30 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.cc (arc_rtx_costs): Improve cost estimates.
- Provide reasonable values for SHIFTS and ROTATES by constant
- bit counts depending upon TARGET_BARREL_SHIFTER.
- (arc_insn_cost): Use insn attributes if the instruction is
- recognized. Avoid calling get_attr_length for type "multi",
- i.e. define_insn_and_split patterns without explicit type.
- Fall-back to set_rtx_cost for single_set and pattern_cost
- otherwise.
- * config/arc/arc.h (COSTS_N_BYTES): Define helper macro.
- (BRANCH_COST): Improve/correct definition.
- (LOGICAL_OP_NON_SHORT_CIRCUIT): Preserve previous behavior.
-
-2023-10-30 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/arc/arc.cc (arc_split_ashl): Use lsl16 on TARGET_SWAP.
- (arc_split_ashr): Use swap and sign-extend on TARGET_SWAP.
- (arc_split_lshr): Use lsr16 on TARGET_SWAP.
- (arc_split_rotl): Use swap on TARGET_SWAP.
- (arc_split_rotr): Likewise.
- * config/arc/arc.md (ANY_ROTATE): New code iterator.
- (<ANY_ROTATE>si2_cnt16): New define_insn for alternate form of
- swap instruction on TARGET_SWAP.
- (ashlsi2_cnt16): Rename from *ashlsi16_cnt16 and move earlier.
- (lshrsi2_cnt16): New define_insn for LSR16 instruction.
- (*ashlsi2_cnt16): See above.
-
-2023-10-30 Richard Ball <richard.ball@arm.com>
-
- * config/arm/aout.h: Change to use the Lrtx label.
- * config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Remove arm targets
- from (!target_pure_code) condition.
- (ADDR_VEC_ALIGN): Add align for tables in rodata section.
- * config/arm/arm.cc (arm_output_casesi): Alter the function to include
- .Lrtx label and remove adr instructions.
- * config/arm/arm.md
- (arm_casesi_internal): Use force_reg to generate ldr instructions that
- would otherwise be out of range, and change rtl to accommodate force reg.
- Additionally remove unnecessary register temp.
- (casesi): Remove pure code check for Arm.
- * config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Remove arm
- targets from JUMP_TABLES_IN_TEXT_SECTION definition.
-
-2023-10-30 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
-
- PR target/106907
- * config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Change bitwise
- xor to an equality and fix comment indentation.
-
-2023-10-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (sew64_scalar_helper): Fix bug.
- * config/riscv/riscv-v.cc (sew64_scalar_helper): Ditto.
- * config/riscv/vector.md: Ditto.
-
-2023-10-30 liuhongt <hongtao.liu@intel.com>
-
- PR target/104610
- * config/i386/i386-expand.cc (ix86_expand_branch): Handle
- 512-bit vector with vpcmpeq + kortest.
- * config/i386/i386.md (cbranchxi4): New expander.
- * config/i386/sse.md: (cbranch<mode>4): Extend to V16SImode
- and V8DImode.
-
-2023-10-30 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/111449
- * expr.cc (qi_vector_mode_supported_p): Rename to...
- (by_pieces_mode_supported_p): ...this, and extends it to do
- the checking for both scalar and vector mode.
- (widest_fixed_size_mode_for_size): Call
- by_pieces_mode_supported_p to examine the mode.
- (op_by_pieces_d::smallest_fixed_size_mode_for_size): Likewise.
-
-2023-10-29 Martin Uecker <uecker@tugraz.at>
-
- PR tree-optimization/109334
- * tree-object-size.cc (parm_object_size): Allow size
- computation for implicit access attributes.
-
-2023-10-29 Max Filippov <jcmvbkbc@gmail.com>
-
- * config/xtensa/xtensa.h (TARGET_SALT): Change HW version from
- 260000 (which corresponds to RF-2014.0) to 270000 (which
- corresponds to RG-2015.0, the release where salt/saltu opcodes
- were introduced).
-
-2023-10-29 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Use
- reference type to prevent copying.
-
-2023-10-27 Vladimir N. Makarov <vmakarov@redhat.com>
-
- PR rtl-optimization/112107
- * ira-costs.cc: (calculate_equiv_gains): Use NONDEBUG_INSN_P
- instead of INSN_P.
-
-2023-10-27 Andrew Stubbs <ams@codesourcery.com>
-
- PR target/112088
- * config/gcn/gcn.cc (gcn_expand_epilogue): Fix kernel epilogue register
- conflict.
-
-2023-10-27 Andrew Stubbs <ams@codesourcery.com>
-
- * config/gcn/gcn-valu.md
- (vec_extract<V_1REG:mode><V_1REG_ALT:mode>_nop): Mention "operands" in
- condition to silence the warnings.
- (vec_extract<V_2REG:mode><V_2REG_ALT:mode>_nop): Likewise.
- * config/gcn/gcn.md (*movti_insn): Likewise.
-
-2023-10-27 Richard Sandiford <richard.sandiford@arm.com>
-
- * recog.cc (insn_propagation::apply_to_pattern_1): Handle shared
- ASM_OPERANDS.
-
-2023-10-27 Yangyu Chen <chenyangyu@isrc.iscas.ac.cn>
-
- * config/riscv/riscv.cc (rocket_tune_info): Fix int_div cost.
- (sifive_7_tune_info, thead_c906_tune_info): Likewise.
-
-2023-10-27 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (rawmemchr<ANYI:mode>): New expander.
- * config/riscv/riscv-protos.h (gen_no_side_effects_vsetvl_rtx):
- Define.
- (expand_rawmemchr): Define.
- * config/riscv/riscv-v.cc (force_vector_length_operand): Remove
- static.
- (expand_block_move): Move from here...
- * config/riscv/riscv-string.cc (expand_block_move): ...to here.
- (expand_rawmemchr): Add vectorized expander.
- * internal-fn.cc (expand_RAWMEMCHR): Fix typo.
-
-2023-10-27 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * ira-costs.cc: (get_equiv_regno, calculate_equiv_gains):
- Process reg equivalence invariants.
-
-2023-10-27 Uros Bizjak <ubizjak@gmail.com>
-
- * config/i386/x86-tune.def (X86_TUNE_PARTIAL_MEMORY_READ_STALL):
- i386: Fiy typo in "partial_memory_read_stall" tune option.
-
-2023-10-27 Victor Do Nascimento <victor.donascimento@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_print_operand): Add
- support for CONST_STRING.
-
-2023-10-27 Roger Sayle <roger@nextmovesoftware.com>
-
- PR target/110551
- * config/i386/i386.md (<u>mul<mode><dwi>3): Make operands 1 and
- 2 take "regiser_operand" and "nonimmediate_operand" respectively.
- (<u>mulqihi3): Likewise.
- (*bmi2_umul<mode><dwi>3_1): Operand 2 needs to be register_operand
- matching the %d constraint. Use umul_highpart RTX to represent
- the highpart multiplication.
- (*umul<mode><dwi>3_1): Operand 2 should use regiser_operand
- predicate, and "a" rather than "0" as operands 0 and 2 have
- different modes.
- (define_split): For mul to mulx conversion, use the new
- umul_highpart RTX representation.
- (*mul<mode><dwi>3_1): Operand 1 should be register_operand
- and the constraint %a as operands 0 and 1 have different modes.
- (*<u>mulqihi3_1): Operand 1 should be register_operand matching
- the constraint %0.
- (define_peephole2): Providing widening multiplication variants
- of the peephole2s that tweak highpart multiplication register
- allocation.
-
-2023-10-27 Lewis Hyatt <lhyatt@gmail.com>
-
- PR preprocessor/87299
- * toplev.cc (no_backend): New static global.
- (finalize): Remove argument no_backend, which is now a
- static global.
- (process_options): Likewise.
- (do_compile): Likewise.
- (target_reinit): Don't do anything in preprocess-only mode.
- (toplev::main): Adapt to no_backend change.
- (toplev::finalize): Likewise.
-
-2023-10-27 Andrew Pinski <apinski@marvell.com>
-
- PR tree-optimization/101590
- PR tree-optimization/94884
- * match.pd (`(X BIT_OP Y) CMP X`): New pattern.
-
-2023-10-27 liuhongt <hongtao.liu@intel.com>
-
- PR target/103861
- * config/i386/i386-expand.cc (ix86_expand_sse_movcc): Handle
- V2HF/V2BF/V4HF/V4BFmode.
- * config/i386/i386.cc (ix86_get_mask_mode): Return QImode when
- data_mode is V4HF/V2HFmode.
- * config/i386/mmx.md (vec_cmpv4hfqi): New expander.
- (vcond_mask_<mode>v4hi): Ditto.
- (vcond_mask_<mode>qi): Ditto.
- (vec_cmpv2hfqi): Ditto.
- (vcond_mask_<mode>v2hi): Ditto.
- (mmx_plendvb_<mode>): Add 2 combine splitters after the
- patterns.
- (mmx_pblendvb_v8qi): Ditto.
- (<code>v2hi3): Add a combine splitter after the pattern.
- (<code><mode>3): Ditto.
- (<code>v8qi3): Ditto.
- (<code><mode>3): Ditto.
- * config/i386/sse.md (vcond<mode><mode>): Merge this with ..
- (vcond<sseintvecmodelower><mode>): .. this into ..
- (vcond<VI2HFBF_AVX512VL:mode><VHF_AVX512VL:mode>): .. this,
- and extend to V8BF/V16BF/V32BFmode.
-
-2023-10-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-opts.h (TARGET_MAX_LMUL): New macro.
- * config/riscv/riscv-v.cc (preferred_simd_mode): Adapt macro.
- (autovectorize_vector_modes): Ditto.
- (can_find_related_mode_p): Ditto.
-
-2023-10-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111318
- PR target/111888
- * config.gcc: Add AVL propagation pass.
- * config/riscv/riscv-passes.def (INSERT_PASS_AFTER): Ditto.
- * config/riscv/riscv-protos.h (make_pass_avlprop): Ditto.
- * config/riscv/t-riscv: Ditto.
- * config/riscv/riscv-avlprop.cc: New file.
-
-2023-10-26 David Malcolm <dmalcolm@redhat.com>
-
- * doc/extend.texi (Common Function Attributes): Add
- null_terminated_string_arg.
-
-2023-10-26 Andrew Pinski <pinskia@gmail.com>
-
- PR tree-optimization/111957
- * match.pd (`a != C1 ? abs(a) : C2`): New pattern.
-
-2023-10-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (range_operator::fold_range): Delete unused
- variable.
-
-2023-10-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (range_operator::fold_range): Remove
- superfluous code.
- (range_operator::rv_fold): Remove unneeded arguments.
- (operator_plus::rv_fold): Same.
- (operator_minus::rv_fold): Same.
- (operator_mult::rv_fold): Same.
- (operator_div::rv_fold): Same.
- * range-op-mixed.h: Remove lb, ub, and maybe_nan arguments from
- rv_fold methods.
- * range-op.h: Same.
-
-2023-10-26 Aldy Hernandez <aldyh@redhat.com>
-
- * range-op-float.cc (range_operator::fold_range): Pass frange
- argument to rv_fold.
- (range_operator::rv_fold): Add frange argument.
- (operator_plus::rv_fold): Same.
- (operator_minus::rv_fold): Same.
- (operator_mult::rv_fold): Same.
- (operator_div::rv_fold): Same.
- * range-op-mixed.h: Add frange argument to rv_fold methods.
- * range-op.h: Same.
-
-2023-10-26 Richard Ball <richard.ball@arm.com>
-
- * config/arm/aout.h (ASM_OUTPUT_ADDR_DIFF_ELT): Add table output
- for different machine modes for arm.
- * config/arm/arm-protos.h (arm_output_casesi): New prototype.
- * config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Make arm use
- ASM_OUTPUT_ADDR_DIFF_ELT.
- (CASE_VECTOR_SHORTEN_MODE): Change table size calculation for
- TARGET_ARM.
- (LABEL_ALIGN_AFTER_BARRIER): Change to accommodate .p2align 2
- for TARGET_ARM.
- * config/arm/arm.cc (arm_output_casesi): New function.
- * config/arm/arm.md (arm_casesi_internal): Change casesi expand
- and insn.
- for arm to use new function arm_output_casesi.
-
-2023-10-26 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin.h
- (darwin_label_is_anonymous_local_objc_name): Make metadata names
- linker-visibile for GNU objective C.
-
-2023-10-26 Vladimir N. Makarov <vmakarov@redhat.com>
-
- * dwarf2out.cc (reg_loc_descriptor): Use lra_eliminate_regs when
- LRA is used.
- * ira-costs.cc: Include regset.h.
- (equiv_can_be_consumed_p, get_equiv_regno, calculate_equiv_gains):
- New functions.
- (find_costs_and_classes): Call calculate_equiv_gains and redefine
- mem_cost of pseudos with equivs when LRA is used.
- * var-tracking.cc: Include ira.h and lra.h.
- (vt_initialize): Use lra_eliminate_regs when LRA is used.
-
-2023-10-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * doc/md.texi: Adapt COND_LEN pseudo code.
-
-2023-10-26 Roger Sayle <roger@nextmovesoftware.com>
- Richard Biener <rguenther@suse.de>
-
- PR rtl-optimization/91865
- * combine.cc (make_compound_operation): Avoid creating a
- ZERO_EXTEND of a ZERO_EXTEND.
-
-2023-10-26 Jiahao Xu <xujiahao@loongson.cn>
-
- * config/loongarch/lasx.md (vcond_mask_<ILASX:mode><ILASX:mode>): Change to
- (vcond_mask_<mode><mode256_i>): this.
- * config/loongarch/lsx.md (vcond_mask_<ILSX:mode><ILSX:mode>): Change to
- (vcond_mask_<mode><mode_i>): this.
-
-2023-10-26 Thomas Schwinge <thomas@codesourcery.com>
-
- * ipa-icf.cc (sem_item::target_supports_symbol_aliases_p):
- 'gcc_checking_assert (TARGET_SUPPORTS_ALIASES);' before
- 'return true;'.
- * ipa-visibility.cc (function_and_variable_visibility): Change
- '#ifdef ASM_OUTPUT_DEF' to 'if (TARGET_SUPPORTS_ALIASES)'.
- * varasm.cc (output_constant_pool_contents)
- [#ifdef ASM_OUTPUT_DEF]:
- 'gcc_checking_assert (TARGET_SUPPORTS_ALIASES);'.
- (do_assemble_alias) [#ifdef ASM_OUTPUT_DEF]:
- 'if (!TARGET_SUPPORTS_ALIASES)',
- 'gcc_checking_assert (seen_error ());'.
- (assemble_alias): Change '#if !defined (ASM_OUTPUT_DEF)' to
- 'if (!TARGET_SUPPORTS_ALIASES)'.
- (default_asm_output_anchor):
- 'gcc_checking_assert (TARGET_SUPPORTS_ALIASES);'.
-
-2023-10-26 Alexandre Oliva <oliva@adacore.com>
-
- PR tree-optimization/111520
- * gimple-harden-conditionals.cc
- (pass_harden_compares::execute): Set EH edge probability and
- EH block execution count.
-
-2023-10-26 Alexandre Oliva <oliva@adacore.com>
-
- * tree-eh.h (make_eh_edges): Rename to...
- (make_eh_edge): ... this.
- * tree-eh.cc: Likewise. Adjust all callers...
- * gimple-harden-conditionals.cc: ... here, ...
- * gimple-harden-control-flow.cc: ... here, ...
- * tree-cfg.cc: ... here, ...
- * tree-inline.cc: ... and here.
-
-2023-10-25 Iain Sandoe <iain@sandoe.co.uk>
-
- * config/darwin.cc (darwin_override_options): Handle fPIE.
-
-2023-10-25 Iain Sandoe <iain@sandoe.co.uk>
-
- * config.gcc: Use -E to to sed to indicate that we are using
- extended REs.
-
-2023-10-25 Jason Merrill <jason@redhat.com>
-
- * tree-core.h (struct tree_base): Update address_space comment.
-
-2023-10-25 Wilco Dijkstra <wilco.dijkstra@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_internal_mov_immediate)
- Add support for immediates using MOV/EOR bitmask.
-
-2023-10-25 Uros Bizjak <ubizjak@gmail.com>
-
- PR target/111698
- * config/i386/x86-tune.def (X86_TUNE_PARTIAL_MEMORY_READ_STALL):
- New tune.
- * config/i386/i386.h (TARGET_PARTIAL_MEMORY_READ_STALL): New macro.
- * config/i386/i386.md: New peephole pattern to narrow test
- instructions with immediate operands that test memory locations
- for zero.
-
-2023-10-25 Andrew MacLeod <amacleod@redhat.com>
-
- * value-range.cc (irange::union_append): New.
- (irange::union_): Call union_append when appropriate.
- * value-range.h (irange::union_append): New prototype.
-
-2023-10-25 Chenghui Pan <panchenghui@loongson.cn>
-
- * config/loongarch/lasxintrin.h (__lasx_xvftintrnel_l_s): Fix comments.
- (__lasx_xvfrintrne_s): Ditto.
- (__lasx_xvfrintrne_d): Ditto.
- (__lasx_xvfrintrz_s): Ditto.
- (__lasx_xvfrintrz_d): Ditto.
- (__lasx_xvfrintrp_s): Ditto.
- (__lasx_xvfrintrp_d): Ditto.
- (__lasx_xvfrintrm_s): Ditto.
- (__lasx_xvfrintrm_d): Ditto.
- * config/loongarch/lsxintrin.h (__lsx_vftintrneh_l_s): Ditto.
- (__lsx_vfrintrne_s): Ditto.
- (__lsx_vfrintrne_d): Ditto.
- (__lsx_vfrintrz_s): Ditto.
- (__lsx_vfrintrz_d): Ditto.
- (__lsx_vfrintrp_s): Ditto.
- (__lsx_vfrintrp_d): Ditto.
- (__lsx_vfrintrm_s): Ditto.
- (__lsx_vfrintrm_d): Ditto.
-
-2023-10-25 chenxiaolong <chenxiaolong@loongson.cn>
-
- * config/loongarch/loongarch.md (get_thread_pointer<mode>):Adds the
- instruction template corresponding to the __builtin_thread_pointer
- function.
- * doc/extend.texi:Add the __builtin_thread_pointer function support
- description to the documentation.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * Makefile.in (OBJS): Add rtl-ssa/movement.o.
- * rtl-ssa/access-utils.h (accesses_include_nonfixed_hard_registers)
- (single_set_info): New functions.
- (remove_uses_of_def, accesses_reference_same_resource): Declare.
- (insn_clobbers_resources): Likewise.
- * rtl-ssa/accesses.cc (rtl_ssa::remove_uses_of_def): New function.
- (rtl_ssa::accesses_reference_same_resource): Likewise.
- (rtl_ssa::insn_clobbers_resources): Likewise.
- * rtl-ssa/movement.h (can_move_insn_p): Declare.
- * rtl-ssa/movement.cc: New file.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/functions.h (function_info::remains_available_at_insn):
- New member function.
- * rtl-ssa/accesses.cc (function_info::remains_available_at_insn):
- Likewise.
- (function_info::make_use_available): Avoid false negatives for
- queries within an EBB.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/changes.cc: Include sreal.h.
- (rtl_ssa::changes_are_worthwhile): When optimizing for speed,
- scale the cost of each instruction by its execution frequency.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/access-utils.h (next_call_clobbers): New function.
- (is_single_dominating_def, remains_available_on_exit): Replace with...
- * rtl-ssa/functions.h (function_info::is_single_dominating_def)
- (function_info::remains_available_on_exit): ...these new member
- functions.
- (function_info::m_clobbered_by_calls): New member variable.
- * rtl-ssa/functions.cc (function_info::function_info): Explicitly
- initialize m_clobbered_by_calls.
- * rtl-ssa/insns.cc (function_info::record_call_clobbers): Update
- m_clobbered_by_calls for each call-clobber note.
- * rtl-ssa/member-fns.inl (function_info::is_single_dominating_def):
- New function. Check for call clobbers.
- * rtl-ssa/accesses.cc (function_info::remains_available_on_exit):
- Likewise.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/internals.h (build_info::exit_block_dominator): New
- member variable.
- * rtl-ssa/blocks.cc (build_info::build_info): Initialize it.
- (bb_walker::bb_walker): Use it, moving the computation of the
- dominator to...
- (function_info::process_all_blocks): ...here.
- (function_info::place_phis): Add dominance frontiers for the
- exit block.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/functions.h (function_info::process_uses_of_deleted_def):
- New member function.
- * rtl-ssa/changes.cc (function_info::process_uses_of_deleted_def):
- Likewise.
- (function_info::change_insns): Use it.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
- If a change describes a set of memory, ensure that that set
- is kept, regardless of the insn pattern.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/changes.cc (function_info::apply_changes_to_insn): Remove
- call to add_reg_unused_notes and instead...
- (function_info::change_insns): ...use a separate loop here.
-
-2023-10-25 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/blocks.cc (function_info::add_artificial_accesses): Force
- global registers to be live on exit. Handle any block with zero
- successors like an exit block.
-
-2023-10-25 Thomas Schwinge <thomas@codesourcery.com>
-
- * omp-oacc-kernels-decompose.cc (omp_oacc_kernels_decompose_1):
- Handle 'OMP_CLAUSE_SELF' like 'OMP_CLAUSE_IF'.
- * omp-expand.cc (expand_omp_target): Handle 'OMP_CLAUSE_SELF' for
- 'GF_OMP_TARGET_KIND_OACC_DATA_KERNELS'.
-
-2023-10-25 Thomas Schwinge <thomas@codesourcery.com>
-
- * tree-core.h (omp_clause_code): Move 'OMP_CLAUSE_SELF' after
- 'OMP_CLAUSE_IF'.
- * tree-pretty-print.cc (dump_omp_clause): Adjust.
- * tree.cc (omp_clause_num_ops, omp_clause_code_name): Likewise.
- * tree.h: Likewise.
-
-2023-10-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (has_vl_op): Export from riscv-vsetvl to riscv-v
- (tail_agnostic_p): Ditto.
- (validate_change_or_fail): Ditto.
- (nonvlmax_avl_type_p): Ditto.
- (vlmax_avl_p): Ditto.
- (get_sew): Ditto.
- (enum vlmul_type): Ditto.
- (count_regno_occurrences): Ditto.
- * config/riscv/riscv-v.cc (has_vl_op): Ditto.
- (get_default_ta): Ditto.
- (tail_agnostic_p): Ditto.
- (validate_change_or_fail): Ditto.
- (nonvlmax_avl_type_p): Ditto.
- (vlmax_avl_p): Ditto.
- (get_sew): Ditto.
- (enum vlmul_type): Ditto.
- (get_vlmul): Ditto.
- (count_regno_occurrences): Ditto.
- * config/riscv/riscv-vsetvl.cc (vlmax_avl_p): Ditto.
- (has_vl_op): Ditto.
- (get_sew): Ditto.
- (get_vlmul): Ditto.
- (get_default_ta): Ditto.
- (tail_agnostic_p): Ditto.
- (count_regno_occurrences): Ditto.
- (validate_change_or_fail): Ditto.
-
-2023-10-25 Chung-Lin Tang <cltang@codesourcery.com>
-
- * gimplify.cc (gimplify_scan_omp_clauses): Add OMP_CLAUSE_SELF case.
- (gimplify_adjust_omp_clauses): Likewise.
- * omp-expand.cc (expand_omp_target): Add OMP_CLAUSE_SELF expansion code,
- * omp-low.cc (scan_sharing_clauses): Add OMP_CLAUSE_SELF case.
- * tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_SELF enum.
- * tree-nested.cc (convert_nonlocal_omp_clauses): Add OMP_CLAUSE_SELF
- case.
- (convert_local_omp_clauses): Likewise.
- * tree-pretty-print.cc (dump_omp_clause): Add OMP_CLAUSE_SELF case.
- * tree.cc (omp_clause_num_ops): Add OMP_CLAUSE_SELF entry.
- (omp_clause_code_name): Likewise.
- * tree.h (OMP_CLAUSE_SELF_EXPR): New macro.
-
-2023-10-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-protos.h (vlmax_avl_type_p): New function.
- * config/riscv/riscv-v.cc (vlmax_avl_type_p): Ditto.
- * config/riscv/riscv-vsetvl.cc (get_avl): Adapt function.
- * config/riscv/vector.md: Change avl_type into avl_type_idx.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * recog.cc (constrain_operands): Remove UNARY_P handling.
- * reload.cc (find_reloads): Likewise.
-
-2023-10-24 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * gcov-io.h: Fix record length encoding in comment.
-
-2023-10-24 Roger Sayle <roger@nextmovesoftware.com>
-
- * config/i386/i386-features.cc (compute_convert_gain): Provide
- more accurate values (sizes) for inter-unit moves with -Os.
-
-2023-10-24 Roger Sayle <roger@nextmovesoftware.com>
- Claudiu Zissulescu <claziss@gmail.com>
-
- * config/arc/arc-protos.h (output_shift): Rename to...
- (output_shift_loop): Tweak API to take an explicit rtx_code.
- (arc_split_ashl): Prototype new function here.
- (arc_split_ashr): Likewise.
- (arc_split_lshr): Likewise.
- (arc_split_rotl): Likewise.
- (arc_split_rotr): Likewise.
- * config/arc/arc.cc (output_shift): Delete local prototype. Rename.
- (output_shift_loop): New function replacing output_shift to output
- a zero overheap loop for SImode shifts and rotates on ARC targets
- without barrel shifter (i.e. no hardware support for these insns).
- (arc_split_ashl): New helper function to split *ashlsi3_nobs.
- (arc_split_ashr): New helper function to split *ashrsi3_nobs.
- (arc_split_lshr): New helper function to split *lshrsi3_nobs.
- (arc_split_rotl): New helper function to split *rotlsi3_nobs.
- (arc_split_rotr): New helper function to split *rotrsi3_nobs.
- (arc_print_operand): Correct whitespace.
- (arc_rtx_costs): Likewise.
- (hwloop_optimize): Likewise.
- * config/arc/arc.md (ANY_SHIFT_ROTATE): New define_code_iterator.
- (define_code_attr insn): New code attribute to map to pattern name.
- (<ANY_SHIFT_ROTATE>si3): New expander unifying previous ashlsi3,
- ashrsi3 and lshrsi3 define_expands. Adds rotlsi3 and rotrsi3.
- (*<ANY_SHIFT_ROTATE>si3_nobs): New define_insn_and_split that
- unifies the previous *ashlsi3_nobs, *ashrsi3_nobs and *lshrsi3_nobs.
- We now call arc_split_<insn> in arc.cc to implement each split.
- (shift_si3): Delete define_insn, all shifts/rotates are now split.
- (shift_si3_loop): Rename to...
- (<insn>si3_loop): define_insn to handle loop implementations of
- SImode shifts and rotates, calling ouput_shift_loop for template.
- (rotrsi3): Rename to...
- (*rotrsi3_insn): define_insn for TARGET_BARREL_SHIFTER's ror.
- (*rotlsi3): New define_insn_and_split to transform left rotates
- into right rotates before reload.
- (rotlsi3_cnt1): New define_insn_and_split to implement a left
- rotate by one bit using an add.f followed by an adc.
- * config/arc/predicates.md (shiftr4_operator): Delete.
-
-2023-10-24 Claudiu Zissulescu <claziss@gmail.com>
-
- * config/arc/arc.md (mulsi3_700): Update pattern.
- (mulsi3_v2): Likewise.
- * config/arc/predicates.md (mpy_dest_reg_operand): Remove it.
-
-2023-10-24 Andrew Pinski <pinskia@gmail.com>
-
- PR tree-optimization/104376
- PR tree-optimization/101541
- * tree-ssa-phiopt.cc (factor_out_conditional_operation):
- Allow nop conversions even if it is defined by a statement
- inside the conditional.
-
-2023-10-24 Andrew Pinski <pinskia@gmail.com>
-
- PR tree-optimization/111913
- * match.pd (`popcount(X&Y) + popcount(X|Y)`): Add the resulting
- type for popcount.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/blocks.cc (function_info::create_degenerate_phi): Check
- whether the requested phi already exists.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa.h: Include cfgbuild.h.
- * rtl-ssa/movement.h (can_insert_after): Replace is_jump with the
- more comprehensive control_flow_insn_p.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/changes.cc (function_info::perform_pending_updates): Check
- whether an insn has been replaced by a note.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * rtl-ssa/member-fns.inl (first_any_insn_use): Handle null
- m_first_use.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/i386/i386-expand.cc (ix86_split_mmx_punpck): Allow the
- destination to be wider than the sources. Take the mode from the
- first source.
- (ix86_expand_sse_extend): Pass the destination directly to
- ix86_split_mmx_punpck, rather than using a fresh register that
- is half the size.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/i386/predicates.md (aeswidekl_operation): Protect
- REGNO check with REG_P.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/aarch64.cc (aarch64_insn_cost): New function.
- (TARGET_INSN_COST): Define.
-
-2023-10-24 Richard Sandiford <richard.sandiford@arm.com>
-
- * config/aarch64/atomics.md (aarch64_atomic_exchange<mode>): Require
- !TARGET_LSE.
-
-2023-10-24 xuli <xuli1@eswincomputing.com>
-
- PR target/111935
- * config/riscv/riscv-vector-builtins-bases.cc: fix bug.
-
-2023-10-24 Mark Harmstone <mark@harmstone.com>
-
- * opts.cc (debug_type_names): Remove stabs and xcoff.
- (df_set_names): Adjust.
-
-2023-10-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111947
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Add REGNO check.
-
-2023-10-23 Lewis Hyatt <lhyatt@gmail.com>
-
- PR preprocessor/36887
- * toplev.h (ident_hash_extra): Declare...
- * stringpool.cc (ident_hash_extra): ...this new global variable.
- (init_stringpool): Handle ident_hash_extra as well as ident_hash.
- (ggc_mark_stringpool): Likewise.
- (ggc_purge_stringpool): Likewise.
- (struct string_pool_data_extra): New struct.
- (spd2): New GC root variable.
- (gt_pch_save_stringpool): Use spd2 to handle ident_hash_extra,
- analogous to how spd is used to handle ident_hash.
- (gt_pch_restore_stringpool): Likewise.
-
-2023-10-23 Robin Dapp <rdapp@ventanamicro.com>
-
- PR tree-optimization/111794
- * tree-vect-stmts.cc (vectorizable_assignment): Add
- same-precision exception for dest and source.
-
-2023-10-23 Robin Dapp <rdapp@ventanamicro.com>
-
- * config/riscv/autovec.md (popcount<mode>2): New expander.
- * config/riscv/riscv-protos.h (expand_popcount): Define.
- * config/riscv/riscv-v.cc (expand_popcount): Vectorize popcount
- with the WWG algorithm.
-
-2023-10-23 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111916
- * tree-sra.cc (sra_modify_assign): Do not lower all
- BIT_FIELD_REF reads that are sra_handled_bf_read_p.
-
-2023-10-23 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111915
- * tree-vect-slp.cc (vect_build_slp_tree_1): Check all
- accesses are either grouped or not.
-
-2023-10-23 Richard Biener <rguenther@suse.de>
-
- PR ipa/111914
- * tree-inline.cc (setup_one_parameter): Move code emitting
- a dummy load when not optimizing ...
- (initialize_inlined_parameters): ... here to after when
- we remapped the parameter type.
-
-2023-10-23 Oleg Endo <olegendo@gcc.gnu.org>
-
- PR target/111001
- * config/sh/sh_treg_combine.cc (sh_treg_combine::record_set_of_reg):
- Skip over nop move insns.
-
-2023-10-23 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/111860
- * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
- Drop .MEM nodes only.
-
-2023-10-23 Andrew Pinski <apinski@marvell.com>
-
- * match.pd (`(A - B) CMP 0 ? (A - B) : (B - A)`):
- New patterns.
-
-2023-10-23 Andrew Pinski <pinskia@gmail.com>
-
- * convert.cc (convert_to_pointer_1): Return error_mark_node
- after an error.
- (convert_to_real_1): Likewise.
- (convert_to_integer_1): Likewise.
- (convert_to_complex_1): Likewise.
-
-2023-10-23 Andrew Pinski <pinskia@gmail.com>
-
- PR c/111903
- * convert.cc (convert_to_complex_1): Return
- error_mark_node if either convert was an error
- when converting from a scalar.
-
-2023-10-23 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111917
- * tree-ssa-loop-unswitch.cc (hoist_guard): Always insert
- new conditional after last stmt.
-
-2023-10-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111927
- * config/riscv/riscv-vsetvl.cc: Fix bug.
-
-2023-10-23 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-v.cc (emit_vec_cvt_x_f_rtz): Add insn type
- arg.
- (expand_vec_trunc): Take MA instead of MU for cvt_x_f_rtz.
-
-2023-10-23 Xi Ruoyao <xry111@xry111.site>
-
- * doc/invoke.texi (-mexplicit-relocs=style): Document.
- (-mexplicit-relocs): Document as an alias of
- -mexplicit-relocs=always.
- (-mno-explicit-relocs): Document as an alias of
- -mexplicit-relocs=none.
- (-mcmodel=extreme): Mention -mexplicit-relocs=always instead of
- -mexplicit-relocs.
-
-2023-10-23 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/predicates.md (symbolic_pcrel_operand): New
- predicate.
- * config/loongarch/loongarch.md (define_peephole2): Optimize
- la.local + ld/st to pcalau12i + ld/st if the address is only used
- once if -mexplicit-relocs=auto and -mcmodel=normal or medium.
-
-2023-10-23 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
- Return true for TLS symbol types if -mexplicit-relocs=auto.
- (loongarch_call_tls_get_addr): Replace TARGET_EXPLICIT_RELOCS
- with la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE.
- (loongarch_legitimize_tls_address): Likewise.
- * config/loongarch/loongarch.md (@tls_low<mode>): Remove
- TARGET_EXPLICIT_RELOCS from insn condition.
-
-2023-10-23 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/loongarch-protos.h
- (loongarch_explicit_relocs_p): Declare new function.
- * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
- Implement.
- (loongarch_symbol_insns): Call loongarch_explicit_relocs_p for
- SYMBOL_GOT_DISP, instead of using TARGET_EXPLICIT_RELOCS.
- (loongarch_split_symbol): Call loongarch_explicit_relocs_p for
- deciding if return early, instead of using
- TARGET_EXPLICIT_RELOCS.
- (loongarch_output_move): CAll loongarch_explicit_relocs_p
- instead of using TARGET_EXPLICIT_RELOCS.
- * config/loongarch/loongarch.md (*low<mode>): Remove
- TARGET_EXPLICIT_RELOCS from insn condition.
- (@ld_from_got<mode>): Likewise.
- * config/loongarch/predicates.md (move_operand): Call
- loongarch_explicit_relocs_p instead of using
- TARGET_EXPLICIT_RELOCS.
-
-2023-10-23 Xi Ruoyao <xry111@xry111.site>
-
- * config/loongarch/genopts/loongarch-strings: Add strings for
- -mexplicit-relocs={auto,none,always}.
- * config/loongarch/genopts/loongarch.opt.in: Add options for
- -mexplicit-relocs={auto,none,always}.
- * config/loongarch/loongarch-str.h: Regenerate.
- * config/loongarch/loongarch.opt: Regenerate.
- * config/loongarch/loongarch-def.h
- (EXPLICIT_RELOCS_AUTO): Define.
- (EXPLICIT_RELOCS_NONE): Define.
- (EXPLICIT_RELOCS_ALWAYS): Define.
- (N_EXPLICIT_RELOCS_TYPES): Define.
- * config/loongarch/loongarch.cc
- (loongarch_option_override_internal): Error out if the old-style
- -m[no-]explicit-relocs option is used with
- -mexplicit-relocs={auto,none,always} together. Map
- -mno-explicit-relocs to -mexplicit-relocs=none and
- -mexplicit-relocs to -mexplicit-relocs=always for backward
- compatibility. Set a proper default for -mexplicit-relocs=
- based on configure-time probed linker capability. Update a
- diagnostic message to mention -mexplicit-relocs=always instead
- of the old-style -mexplicit-relocs.
- (loongarch_handle_model_attribute): Update a diagnostic message
- to mention -mexplicit-relocs=always instead of the old-style
- -mexplicit-relocs.
- * config/loongarch/loongarch.h (TARGET_EXPLICIT_RELOCS): Define.
-
-2023-10-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info): Fix typo.
- (pre_vsetvl::pre_global_vsetvl_info): Ditto.
-
-2023-10-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/vector.md: Fix avl_type attribute of tuple mov<mode>.
-
-2023-10-23 Kewen Lin <linkw@linux.ibm.com>
-
- PR tree-optimization/111784
- * tree-vect-stmts.cc (vectorizable_store): Adjust costing way for
- adjacent vector stores, by costing them with the total number
- rather than costing them one by one.
- (vectorizable_load): Adjust costing way for adjacent vector
- loads, by costing them with the total number rather than costing
- them one by one.
-
-2023-10-23 Haochen Jiang <haochen.jiang@intel.com>
-
- PR target/111753
- * config/i386/i386.cc (ix86_standard_x87sse_constant_load_p):
- Do not split to xmm16+ when !TARGET_AVX512VL.
-
-2023-10-23 Pan Li <pan2.li@intel.com>
-
- * config/riscv/riscv-protos.h (enum insn_type): Add new type
- values.
- * config/riscv/riscv-v.cc (emit_vec_cvt_x_f): Add undef merge
- operand handling.
- (expand_vec_ceil): Take MA instead of MU for tmp register.
- (expand_vec_floor): Ditto.
- (expand_vec_nearbyint): Ditto.
- (expand_vec_rint): Ditto.
- (expand_vec_round): Ditto.
- (expand_vec_roundeven): Ditto.
-
-2023-10-23 Lulu Cheng <chenglulu@loongson.cn>
-
- * config/loongarch/loongarch.h (CLEAR_INSN_CACHE): New definition.
-
-2023-10-23 Haochen Gui <guihaoc@gcc.gnu.org>
-
- PR target/111449
- * expr.cc (can_use_qi_vectors): New function to return true if
- we know how to implement OP using vectors of bytes.
- (qi_vector_mode_supported_p): New function to check if optabs
- exists for the mode and certain by pieces operations.
- (widest_fixed_size_mode_for_size): Replace the second argument
- with the type of by pieces operations. Call can_use_qi_vectors
- and qi_vector_mode_supported_p to do the check. Call
- scalar_mode_supported_p to check if the scalar mode is supported.
- (by_pieces_ninsns): Pass the type of by pieces operation to
- widest_fixed_size_mode_for_size.
- (class op_by_pieces_d): Remove m_qi_vector_mode. Add m_op to
- record the type of by pieces operations.
- (op_by_pieces_d::op_by_pieces_d): Change last argument to the
- type of by pieces operations, initialize m_op with it. Pass
- m_op to function widest_fixed_size_mode_for_size.
- (op_by_pieces_d::get_usable_mode): Pass m_op to function
- widest_fixed_size_mode_for_size.
- (op_by_pieces_d::smallest_fixed_size_mode_for_size): Call
- can_use_qi_vectors and qi_vector_mode_supported_p to do the
- check.
- (op_by_pieces_d::run): Pass m_op to function
- widest_fixed_size_mode_for_size.
- (move_by_pieces_d::move_by_pieces_d): Set m_op to MOVE_BY_PIECES.
- (store_by_pieces_d::store_by_pieces_d): Set m_op with the op.
- (can_store_by_pieces): Pass the type of by pieces operations to
- widest_fixed_size_mode_for_size.
- (clear_by_pieces): Initialize class store_by_pieces_d with
- CLEAR_BY_PIECES.
- (compare_by_pieces_d::compare_by_pieces_d): Set m_op to
- COMPARE_BY_PIECES.
-
-2023-10-23 liuhongt <hongtao.liu@intel.com>
-
- PR tree-optimization/111820
- PR tree-optimization/111833
- * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Give
- up vectorization for nonlinear iv vect_step_op_mul when
- step_expr is not exact_log2 and niters is greater than
- TYPE_PRECISION (TREE_TYPE (step_expr)). Also don't vectorize
- for nagative niters_skip which will be used by fully masked
- loop.
- (vect_can_advance_ivs_p): Pass whole phi_info to
- vect_can_peel_nonlinear_iv_p.
- * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Optimize
- init_expr * pow (step_expr, skipn) to init_expr
- << (log2 (step_expr) * skipn) when step_expr is exact_log2.
-
-2023-10-23 liuhongt <hongtao.liu@intel.com>
-
- * config/i386/mmx.md (mmx_pinsrw): Remove.
-
-2023-10-22 Andrew Pinski <pinskia@gmail.com>
-
- PR target/110986
- * config/aarch64/aarch64.md (*cmov<mode>_insn_insv): New pattern.
- (*cmov_uxtw_insn_insv): Likewise.
-
-2023-10-22 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
-
- * doc/invoke.texi: Document the new -nodefaultrpaths option.
- * doc/install.texi: Document the new --with-darwin-extra-rpath
- option.
-
-2023-10-22 Iain Sandoe <iain@sandoe.co.uk>
-
- * Makefile.in: set ENABLE_DARWIN_AT_RPATH in site.tmp.
-
-2023-10-22 Iain Sandoe <iain@sandoe.co.uk>
-
- * configure.ac: Add --with-darwin-extra-rpath option.
- * config/darwin.h: Handle DARWIN_EXTRA_RPATH.
- * config.in: Regenerate.
- * configure: Regenerate.
-
-2023-10-22 Iain Sandoe <iain@sandoe.co.uk>
-
- * aclocal.m4: Regenerate.
- * configure: Regenerate.
- * configure.ac: Handle Darwin rpaths.
- * config/darwin.h: Handle Darwin rpaths.
- * config/darwin.opt: Handle Darwin rpaths.
- * Makefile.in: Handle Darwin rpaths.
-
-2023-10-22 Iain Sandoe <iain@sandoe.co.uk>
-
- * gcc.cc (RUNPATH_OPTION): New.
- (do_spec_1): Provide '%P' as a spec to insert rpaths for
- each compiler startfile path.
-
-2023-10-22 Andrew Burgess <andrew.burgess@embecosm.com>
- Maxim Blinov <maxim.blinov@embecosm.com>
- Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
- Iain Sandoe <iain@sandoe.co.uk>
-
- * config.gcc: Default to heap trampolines on macOS 11 and above.
- * config/i386/darwin.h: Define X86_CUSTOM_FUNCTION_TEST.
- * config/i386/i386.h: Define X86_CUSTOM_FUNCTION_TEST.
- * config/i386/i386.cc: Use X86_CUSTOM_FUNCTION_TEST.
-
-2023-10-22 Andrew Burgess <andrew.burgess@embecosm.com>
- Maxim Blinov <maxim.blinov@embecosm.com>
- Iain Sandoe <iain@sandoe.co.uk>
- Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
-
- * builtins.def (BUILT_IN_NESTED_PTR_CREATED): Define.
- (BUILT_IN_NESTED_PTR_DELETED): Ditto.
- * common.opt (ftrampoline-impl): Add option to control
- generation of trampoline instantiation (heap or stack).
- * coretypes.h: Define enum trampoline_impl.
- * tree-nested.cc (convert_tramp_reference_op): Don't bother calling
- __builtin_adjust_trampoline for heap trampolines.
- (finalize_nesting_tree_1): Emit calls to
- __builtin_nested_...{created,deleted} if we're generating with
- -ftrampoline-impl=heap.
- * tree.cc (build_common_builtin_nodes): Build
- __builtin_nested_...{created,deleted}.
- * doc/invoke.texi (-ftrampoline-impl): Document.
-
-2023-10-22 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
- Prohibit 'E' and 'H' combinations.
-
-2023-10-22 Tsukasa OI <research_trasio@irq.a4lg.com>
-
- * common/config/riscv/riscv-common.cc (riscv_ext_version_table):
- Change version number of the 'Zfa' extension to 1.0.
-
-2023-10-21 Pan Li <pan2.li@intel.com>
-
- PR target/111857
- * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Remove.
- * config/riscv/riscv-protos.h (vls_mode_valid_p): New func decl.
- * config/riscv/riscv-v.cc (autovectorize_vector_modes): Replace
- macro reference to func.
- (vls_mode_valid_p): New func impl for vls mode valid or not.
- * config/riscv/riscv-vector-switch.def (VLS_ENTRY): Replace
- macro reference to func.
- * config/riscv/vector-iterators.md: Ditto.
-
-2023-10-20 Roger Sayle <roger@nextmovesoftware.com>
- Uros Bizjak <ubizjak@gmail.com>
-
- PR middle-end/101955
- PR tree-optimization/106245
- * config/i386/i386.md (*extv<mode>_1_0): New define_insn_and_split.
-
-2023-10-20 David Edelsohn <dje.gcc@gmail.com>
-
- * gimple-harden-control-flow.cc: Include memmodel.h.
-
-2023-10-20 David Edelsohn <dje.gcc@gmail.com>
-
- * gimple-harden-control-flow.cc: Include tm_p.h.
-
-2023-10-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- PR tree-optimization/111882
- * tree-if-conv.cc (get_bitfield_rep): Return NULL_TREE for bitfields
- with non-constant offsets.
-
-2023-10-20 Tamar Christina <tamar.christina@arm.com>
-
- PR tree-optimization/111866
- * tree-vect-loop-manip.cc (vect_do_peeling): Pass null as vinfo to
- vect_set_loop_condition during prolog peeling.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111445
- * tree-scalar-evolution.cc (simple_iv_with_niters):
- Add missing check for a sign-conversion.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/110243
- PR tree-optimization/111336
- * tree-ssa-loop-ivopts.cc (strip_offset_1): Rewrite
- operations with undefined behavior on overflow to
- unsigned arithmetic.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111891
- * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fix
- assert.
-
-2023-10-20 Andrew Stubbs <ams@codesourcery.com>
-
- * config.gcc: Allow --with-arch=gfx1030.
- * config/gcn/gcn-hsa.h (NO_XNACK): gfx1030 does not support xnack.
- (ASM_SPEC): gfx1030 needs -mattr=+wavefrontsize64 set.
- * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1030.
- (TARGET_GFX1030): New.
- (TARGET_RDNA2): New.
- * config/gcn/gcn-valu.md (@dpp_move<mode>): Disable for RDNA2.
- (addc<mode>3<exec_vcc>): Add RDNA2 syntax variant.
- (subc<mode>3<exec_vcc>): Likewise.
- (<convop><mode><vndi>2_exec): Add RDNA2 alternatives.
- (vec_cmp<mode>di): Likewise.
- (vec_cmp<u><mode>di): Likewise.
- (vec_cmp<mode>di_exec): Likewise.
- (vec_cmp<u><mode>di_exec): Likewise.
- (vec_cmp<mode>di_dup): Likewise.
- (vec_cmp<mode>di_dup_exec): Likewise.
- (reduc_<reduc_op>_scal_<mode>): Disable for RDNA2.
- (*<reduc_op>_dpp_shr_<mode>): Likewise.
- (*plus_carry_dpp_shr_<mode>): Likewise.
- (*plus_carry_in_dpp_shr_<mode>): Likewise.
- * config/gcn/gcn.cc (gcn_option_override): Recognise gfx1030.
- (gcn_global_address_p): RDNA2 only allows smaller offsets.
- (gcn_addr_space_legitimate_address_p): Likewise.
- (gcn_omp_device_kind_arch_isa): Recognise gfx1030.
- (gcn_expand_epilogue): Use VGPRs instead of SGPRs.
- (output_file_start): Configure gfx1030.
- * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __RDNA2__;
- (ASSEMBLER_DIALECT): New.
- * config/gcn/gcn.md (rdna): New define_attr.
- (enabled): Use "rdna" attribute.
- (gcn_return): Remove s_dcache_wb.
- (addcsi3_scalar): Add RDNA2 syntax variant.
- (addcsi3_scalar_zero): Likewise.
- (addptrdi3): Likewise.
- (mulsi3): v_mul_lo_i32 should be v_mul_lo_u32 on all ISA.
- (*memory_barrier): Add RDNA2 syntax variant.
- (atomic_load<mode>): Add RDNA2 cache control variants, and disable
- scalar atomics for RDNA2.
- (atomic_store<mode>): Likewise.
- (atomic_exchange<mode>): Likewise.
- * config/gcn/gcn.opt (gpu_type): Add gfx1030.
- * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1030): New.
- (main): Recognise -march=gfx1030.
- * config/gcn/t-omp-device: Add gfx1030 isa.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- PR tree-optimization/111000
- * stor-layout.h (element_precision): Move ..
- * tree.h (element_precision): .. here.
- * tree-ssa-loop-im.cc (movement_possibility_1): Restrict
- motion of shifts and rotates.
-
-2023-10-20 Alexandre Oliva <oliva@adacore.com>
-
- * tree-core.h (ECF_XTHROW): New macro.
- * tree.cc (set_call_expr): Add expected_throw attribute when
- ECF_XTHROW is set.
- (build_common_builtin_node): Add ECF_XTHROW to
- __cxa_end_cleanup and _Unwind_Resume or _Unwind_SjLj_Resume.
- * calls.cc (flags_from_decl_or_type): Check for expected_throw
- attribute to set ECF_XTHROW.
- * gimple.cc (gimple_build_call_from_tree): Propagate
- ECF_XTHROW from decl flags to gimple call...
- (gimple_call_flags): ... and back.
- * gimple.h (GF_CALL_XTHROW): New gf_mask flag.
- (gimple_call_set_expected_throw): New.
- (gimple_call_expected_throw_p): New.
- * Makefile.in (OBJS): Add gimple-harden-control-flow.o.
- * builtins.def (BUILT_IN___HARDCFR_CHECK): New.
- * common.opt (fharden-control-flow-redundancy): New.
- (-fhardcfr-check-returning-calls): New.
- (-fhardcfr-check-exceptions): New.
- (-fhardcfr-check-noreturn-calls=*): New.
- (Enum hardcfr_check_noreturn_calls): New.
- (fhardcfr-skip-leaf): New.
- * doc/invoke.texi: Document them.
- (hardcfr-max-blocks, hardcfr-max-inline-blocks): New params.
- * flag-types.h (enum hardcfr_noret): New.
- * gimple-harden-control-flow.cc: New.
- * params.opt (-param=hardcfr-max-blocks=): New.
- (-param=hradcfr-max-inline-blocks=): New.
- * passes.def (pass_harden_control_flow_redundancy): Add.
- * tree-pass.h (make_pass_harden_control_flow_redundancy):
- Declare.
- * doc/extend.texi: Document expected_throw attribute.
-
-2023-10-20 Alex Coplan <alex.coplan@arm.com>
-
- * rtl-ssa/changes.cc (function_info::change_insns): Ensure we call
- ::remove_insn on deleted insns.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- * doc/generic.texi ({L,R}ROTATE_EXPR): Document.
-
-2023-10-20 Oleg Endo <olegendo@gcc.gnu.org>
-
- PR target/101177
- * config/sh/sh.md (unnamed split pattern): Fix comparison of
- find_regno_note result.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- * tree-vect-loop.cc (update_epilogue_loop_vinfo): Rewrite
- both STMT_VINFO_GATHER_SCATTER_P and VMAT_GATHER_SCATTER
- stmt refs.
-
-2023-10-20 Richard Biener <rguenther@suse.de>
-
- * tree-vect-slp.cc (off_map, off_op0_map, off_arg2_map,
- off_arg3_arg2_map): New.
- (vect_get_operand_map): Get flag whether the stmt was
- recognized as gather or scatter and use the above
- accordingly.
- (vect_get_and_check_slp_defs): Adjust.
- (vect_build_slp_tree_2): Likewise.
-
-2023-10-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info): Rename variables.
- (pre_vsetvl::pre_global_vsetvl_info): Ditto.
- (pre_vsetvl::emit_vsetvl): Ditto.
-
-2023-10-20 Tamar Christina <tamar.christina@arm.com>
- Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * tree-if-conv.cc (if_convertible_loop_p_1): Move check from here ...
- (get_loop_body_if_conv_order): ... to here.
- (if_convertible_loop_p): Remove single_exit check.
- (tree_if_conversion): Move single_exit check to if-conversion part and
- support multiple exits.
-
-2023-10-20 Tamar Christina <tamar.christina@arm.com>
- Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- * tree-vect-patterns.cc (vect_init_pattern_stmt): Copy STMT_VINFO_TYPE
- from original statement.
- (vect_recog_bitfield_ref_pattern): Support bitfields in gcond.
-
-2023-10-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
-
- PR target/111848
- * config/riscv/riscv-selftests.cc (run_const_vector_selftests): Adapt selftest.
- * config/riscv/riscv-v.cc (expand_const_vector): Change it into vec_duplicate splitter.
-
-2023-10-20 Lehua Ding <lehua.ding@rivai.ai>
-
- PR target/111037
- PR target/111234
- PR target/111725
- * config/riscv/riscv-vsetvl.cc (bitmap_union_of_preds_with_entry): New.
- (debug): Removed.
- (compute_reaching_defintion): New.
- (enum vsetvl_type): Moved.
- (vlmax_avl_p): Moved.
- (enum emit_type): Moved.
- (vlmul_to_str): Moved.
- (vlmax_avl_insn_p): Removed.
- (policy_to_str): Moved.
- (loop_basic_block_p): Removed.
- (valid_sew_p): Removed.
- (vsetvl_insn_p): Moved.
- (vsetvl_vtype_change_only_p): Removed.
- (after_or_same_p): Removed.
- (before_p): Removed.
- (anticipatable_occurrence_p): Removed.
- (available_occurrence_p): Removed.
- (insn_should_be_added_p): Removed.
- (get_all_sets): Moved.
- (get_same_bb_set): Moved.
- (gen_vsetvl_pat): Removed.
- (calculate_vlmul): Moved.
- (get_max_int_sew): New.
- (emit_vsetvl_insn): Removed.
- (get_max_float_sew): New.
- (eliminate_insn): Removed.
- (insert_vsetvl): Removed.
- (count_regno_occurrences): Moved.
- (get_vl_vtype_info): Removed.
- (enum def_type): Moved.
- (validate_change_or_fail): Moved.
- (change_insn): Removed.
- (get_all_real_uses): Moved.
- (get_forward_read_vl_insn): Removed.
- (get_backward_fault_first_load_insn): Removed.
- (change_vsetvl_insn): Removed.
- (avl_source_has_vsetvl_p): Removed.
- (source_equal_p): Moved.
- (calculate_sew): Removed.
- (same_equiv_note_p): Moved.
- (get_expr_id): New.
- (incompatible_avl_p): Removed.
- (get_regno): New.
- (different_sew_p): Removed.
- (get_bb_index): New.
- (different_lmul_p): Removed.
- (has_no_uses): Moved.
- (different_ratio_p): Removed.
- (different_tail_policy_p): Removed.
- (different_mask_policy_p): Removed.
- (possible_zero_avl_p): Removed.
- (enum demand_flags): New.
- (second_ratio_invalid_for_first_sew_p): Removed.
- (second_ratio_invalid_for_first_lmul_p): Removed.
- (enum class): New.
- (float_insn_valid_sew_p): Removed.
- (second_sew_less_than_first_sew_p): Removed.
- (first_sew_less_than_second_sew_p): Removed.
- (class vsetvl_info): New.
- (compare_lmul): Removed.
- (second_lmul_less_than_first_lmul_p): Removed.
- (second_ratio_less_than_first_ratio_p): Removed.
- (DEF_INCOMPATIBLE_COND): Removed.
- (greatest_sew): Removed.
- (first_sew): Removed.
- (second_sew): Removed.
- (first_vlmul): Removed.
- (second_vlmul): Removed.
- (first_ratio): Removed.
- (second_ratio): Removed.
- (vlmul_for_first_sew_second_ratio): Removed.
- (vlmul_for_greatest_sew_second_ratio): Removed.
- (ratio_for_second_sew_first_vlmul): Removed.
- (class vsetvl_block_info): New.
- (DEF_SEW_LMUL_FUSE_RULE): New.
- (always_unavailable): Removed.
- (avl_unavailable_p): Removed.
- (class demand_system): New.
- (sew_unavailable_p): Removed.
- (lmul_unavailable_p): Removed.
- (ge_sew_unavailable_p): Removed.
- (ge_sew_lmul_unavailable_p): Removed.
- (ge_sew_ratio_unavailable_p): Removed.
- (DEF_UNAVAILABLE_COND): Removed.
- (same_sew_lmul_demand_p): Removed.
- (propagate_avl_across_demands_p): Removed.
- (reg_available_p): Removed.
- (support_relaxed_compatible_p): Removed.
- (demands_can_be_fused_p): Removed.
- (earliest_pred_can_be_fused_p): Removed.
- (vsetvl_dominated_by_p): Removed.
- (avl_info::avl_info): Removed.
- (avl_info::single_source_equal_p): Removed.
- (avl_info::multiple_source_equal_p): Removed.
- (DEF_SEW_LMUL_RULE): New.
- (avl_info::operator=): Removed.
- (avl_info::operator==): Removed.
- (DEF_POLICY_RULE): New.
- (avl_info::operator!=): Removed.
- (avl_info::has_non_zero_avl): Removed.
- (vl_vtype_info::vl_vtype_info): Removed.
- (vl_vtype_info::operator==): Removed.
- (DEF_AVL_RULE): New.
- (vl_vtype_info::operator!=): Removed.
- (vl_vtype_info::same_avl_p): Removed.
- (vl_vtype_info::same_vtype_p): Removed.
- (vl_vtype_info::same_vlmax_p): Removed.
- (vector_insn_info::operator>=): Removed.
- (vector_insn_info::operator==): Removed.
- (class pre_vsetvl): New.
- (vector_insn_info::parse_insn): Removed.
- (vector_insn_info::compatible_p): Removed.
- (vector_insn_info::skip_avl_compatible_p): Removed.
- (vector_insn_info::compatible_a[...]
[diff truncated at 524288 bytes]
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