public inbox for libstdc++-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc r14-6963] Daily bump.
@ 2024-01-06 0:18 GCC Administrator
0 siblings, 0 replies; only message in thread
From: GCC Administrator @ 2024-01-06 0:18 UTC (permalink / raw)
To: gcc-cvs, libstdc++-cvs
https://gcc.gnu.org/g:f38103f5670538f33b0890d2945c3a96c6760e7d
commit r14-6963-gf38103f5670538f33b0890d2945c3a96c6760e7d
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Sat Jan 6 00:18:04 2024 +0000
Daily bump.
Diff:
---
contrib/ChangeLog | 25 +++++
gcc/ChangeLog | 245 ++++++++++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/testsuite/ChangeLog | 176 ++++++++++++++++++++++++++++++++++
libgm2/ChangeLog | 4 +
libstdc++-v3/ChangeLog | 41 ++++++++
6 files changed, 492 insertions(+), 1 deletion(-)
diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index 02de42f2dfc..bf16df87a73 100644
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,28 @@
+2024-01-05 Jonathan Wakely <jwakely@redhat.com>
+
+ * analyze_brprob.py: Remove stray text at end of comment.
+ * analyze_brprob_spec.py: Likewise.
+ * check-params-in-docs.py: Likewise.
+ * check_GNU_style.py: Likewise.
+ * check_GNU_style_lib.py: Likewise.
+ * filter-clang-warnings.py: Likewise.
+ * gcc-changelog/git_check_commit.py: Likewise.
+ * gcc-changelog/git_commit.py: Likewise.
+ * gcc-changelog/git_email.py: Likewise.
+ * gcc-changelog/git_repository.py: Likewise.
+ * gcc-changelog/git_update_version.py: Likewise.
+ * gcc-changelog/test_email.py: Likewise.
+ * gen_autofdo_event.py: Likewise.
+ * mark_spam.py: Likewise.
+ * unicode/gen-box-drawing-chars.py: Likewise.
+ * unicode/gen-combining-chars.py: Likewise.
+ * unicode/gen-printable-chars.py: Likewise.
+ * unicode/gen_wcwidth.py: Likewise.
+
+2024-01-05 Jonathan Wakely <jwakely@redhat.com>
+
+ * unicode/gen_wcwidth.py: Add sys.argv[0] to usage error.
+
2024-01-03 Jakub Jelinek <jakub@redhat.com>
* update-copyright.py (GenericFilter): Skip gpl_v3_without_node.texi.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5bda9c95b59..af1c152f092 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,248 @@
+2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/113104
+ * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
+ (aarch64-vect-compare-costs): ...this.
+ * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
+ Replace with...
+ (-param=aarch64-vect-compare-costs=): ...this new param.
+ * config/aarch64/aarch64.cc (aarch64_override_options_internal):
+ Don't disable it when vectorizing for Advanced SIMD only.
+ (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
+ whenever aarch64_vect_compare_costs is true.
+
+2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
+ Modify the method of determining the memory offset of [x]vld/[x]vst.
+ (lasx_mxst_<lasxfmt_f>): Likewise.
+ * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
+ (loongarch_address_insns): Likewise.
+ * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
+ (lsx_st_<lsxfmt_f>): Likewise.
+ * config/loongarch/predicates.md (aq10b_operand): Likewise.
+ (aq10h_operand): Likewise.
+ (aq10w_operand): Likewise.
+ (aq10d_operand): Likewise.
+
+2024-01-05 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/113217
+ * config/aarch64/aarch64-ldp-fusion.cc
+ (ldp_bb_info::try_fuse_pair): If the second access can throw,
+ narrow the move range to exactly that insn.
+
+2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * asan.cc (asan_function_start): Drop switch_to_section ().
+ (asan_emit_stack_protection): Set .LASANPC alignment.
+ * config/i386/i386.cc: Use assemble_function_label_raw ()
+ instead of ASM_OUTPUT_LABEL ().
+ * config/s390/s390.cc (s390_asm_output_function_label):
+ Likewise.
+ * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
+ * final.cc (final_start_function_1): Drop
+ asan_function_start ().
+ * output.h (assemble_function_label_raw): New function.
+ * varasm.cc (assemble_function_label_raw): Likewise.
+
+2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * config/aarch64/aarch64.cc (aarch64_declare_function_name):
+ Use ASM_OUTPUT_FUNCTION_LABEL ().
+ * config/alpha/alpha.cc (alpha_start_function): Likewise.
+ * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
+ * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
+ * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
+ * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
+ * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
+ * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
+ * config/ia64/ia64.cc (ia64_start_function): Likewise.
+ * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
+ Likewise.
+ * config/microblaze/microblaze.cc (microblaze_function_prologue):
+ Likewise.
+ * config/mips/mips.cc (mips_start_unique_function): Return the
+ tree.
+ (mips_start_function_definition): Use
+ ASM_OUTPUT_FUNCTION_LABEL ().
+ (mips_finish_stub): Pass the tree to
+ mips_start_function_definition ().
+ (mips16_build_function_stub): Likewise.
+ (mips16_build_call_stub): Likewise.
+ (mips_output_function_prologue): Likewise.
+ * config/pa/pa.cc (pa_output_function_label): Use
+ ASM_OUTPUT_FUNCTION_LABEL ().
+ * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
+ * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
+ Likewise.
+ (rs6000_xcoff_declare_function_name): Likewise.
+
+2024-01-05 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/113201
+ * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
+ replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
+
+2024-01-05 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/90693
+ * tree-ssa-math-opts.cc (match_single_bit_test): If
+ tree_expr_nonzero_p (arg), remember it in the second argument to
+ IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
+ arg ^ (arg - 1) > arg - 1.
+ * internal-fn.cc (expand_POPCOUNT): If second argument to
+ IFN_POPCOUNT suggests arg is non-zero, try to expand it as
+ arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
+
+2024-01-05 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/riscv-v.cc (expand_load_store):
+ Remove `value`.
+ (expand_cond_len_op): Ditto.
+ (expand_gather_scatter): Ditto.
+ (expand_lanes_load_store): Ditto.
+ (expand_fold_extract_last): Ditto.
+
+2024-01-05 Pan Li <pan2.li@intel.com>
+
+ Revert:
+ 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
+
+ * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
+ Add new function_base for crypto vector.
+ (class bitmanip): Ditto.
+ (class b_reverse):Ditto.
+ (class vwsll): Ditto.
+ (class clmul): Ditto.
+ (class vg_nhab): Ditto.
+ (class crypto_vv):Ditto.
+ (class crypto_vi):Ditto.
+ (class vaeskf2_vsm3c):Ditto.
+ (class vsm3me): Ditto.
+ (BASE): Add BASE declaration for crypto vector.
+ * config/riscv/riscv-vector-builtins-bases.h: Ditto.
+ * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
+ Add crypto vector intrinsic definition.
+ (vbrev): Ditto.
+ (vclz): Ditto.
+ (vctz): Ditto.
+ (vwsll): Ditto.
+ (vandn): Ditto.
+ (vbrev8): Ditto.
+ (vrev8): Ditto.
+ (vrol): Ditto.
+ (vror): Ditto.
+ (vclmul): Ditto.
+ (vclmulh): Ditto.
+ (vghsh): Ditto.
+ (vgmul): Ditto.
+ (vaesef): Ditto.
+ (vaesem): Ditto.
+ (vaesdf): Ditto.
+ (vaesdm): Ditto.
+ (vaesz): Ditto.
+ (vaeskf1): Ditto.
+ (vaeskf2): Ditto.
+ (vsha2ms): Ditto.
+ (vsha2ch): Ditto.
+ (vsha2cl): Ditto.
+ (vsm4k): Ditto.
+ (vsm4r): Ditto.
+ (vsm3me): Ditto.
+ (vsm3c): Ditto.
+ * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
+ Add new function_shape for crypto vector.
+ (struct crypto_vi_def): Ditto.
+ (struct crypto_vv_no_op_type_def): Ditto.
+ (SHAPE): Add SHAPE declaration of crypto vector.
+ * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
+ * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
+ Add new data type for crypto vector.
+ (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
+ (vuint32mf2_t): Ditto.
+ (vuint32m1_t): Ditto.
+ (vuint32m2_t): Ditto.
+ (vuint32m4_t): Ditto.
+ (vuint32m8_t): Ditto.
+ (vuint64m1_t): Ditto.
+ (vuint64m2_t): Ditto.
+ (vuint64m4_t): Ditto.
+ (vuint64m8_t): Ditto.
+ * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
+ Add new data struct for crypto vector.
+ (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
+ (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
+ * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
+
+2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
+
+ * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
+ Add new function_base for crypto vector.
+ (class bitmanip): Ditto.
+ (class b_reverse):Ditto.
+ (class vwsll): Ditto.
+ (class clmul): Ditto.
+ (class vg_nhab): Ditto.
+ (class crypto_vv):Ditto.
+ (class crypto_vi):Ditto.
+ (class vaeskf2_vsm3c):Ditto.
+ (class vsm3me): Ditto.
+ (BASE): Add BASE declaration for crypto vector.
+ * config/riscv/riscv-vector-builtins-bases.h: Ditto.
+ * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
+ Add crypto vector intrinsic definition.
+ (vbrev): Ditto.
+ (vclz): Ditto.
+ (vctz): Ditto.
+ (vwsll): Ditto.
+ (vandn): Ditto.
+ (vbrev8): Ditto.
+ (vrev8): Ditto.
+ (vrol): Ditto.
+ (vror): Ditto.
+ (vclmul): Ditto.
+ (vclmulh): Ditto.
+ (vghsh): Ditto.
+ (vgmul): Ditto.
+ (vaesef): Ditto.
+ (vaesem): Ditto.
+ (vaesdf): Ditto.
+ (vaesdm): Ditto.
+ (vaesz): Ditto.
+ (vaeskf1): Ditto.
+ (vaeskf2): Ditto.
+ (vsha2ms): Ditto.
+ (vsha2ch): Ditto.
+ (vsha2cl): Ditto.
+ (vsm4k): Ditto.
+ (vsm4r): Ditto.
+ (vsm3me): Ditto.
+ (vsm3c): Ditto.
+ * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
+ Add new function_shape for crypto vector.
+ (struct crypto_vi_def): Ditto.
+ (struct crypto_vv_no_op_type_def): Ditto.
+ (SHAPE): Add SHAPE declaration of crypto vector.
+ * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
+ * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
+ Add new data type for crypto vector.
+ (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
+ (vuint32mf2_t): Ditto.
+ (vuint32m1_t): Ditto.
+ (vuint32m2_t): Ditto.
+ (vuint32m4_t): Ditto.
+ (vuint32m8_t): Ditto.
+ (vuint64m1_t): Ditto.
+ (vuint64m2_t): Ditto.
+ (vuint64m4_t): Ditto.
+ (vuint64m8_t): Ditto.
+ * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
+ Add new data struct for crypto vector.
+ (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
+ (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
+ * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
+
2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index b8ba45eca8a..7d3dc9a39c2 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240105
+20240106
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fae2347eec1..003a18cb37f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,179 @@
+2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/113104
+ * gcc.target/aarch64/pr113104.c: New test.
+ * gcc.target/aarch64/sve/cond_arith_1.c: Update for new parameter
+ names.
+ * gcc.target/aarch64/sve/cond_arith_1_run.c: Likewise.
+ * gcc.target/aarch64/sve/cond_arith_3.c: Likewise.
+ * gcc.target/aarch64/sve/cond_arith_3_run.c: Likewise.
+ * gcc.target/aarch64/sve/gather_load_6.c: Likewise.
+ * gcc.target/aarch64/sve/gather_load_7.c: Likewise.
+ * gcc.target/aarch64/sve/load_const_offset_2.c: Likewise.
+ * gcc.target/aarch64/sve/load_const_offset_3.c: Likewise.
+ * gcc.target/aarch64/sve/mask_gather_load_6.c: Likewise.
+ * gcc.target/aarch64/sve/mask_gather_load_7.c: Likewise.
+ * gcc.target/aarch64/sve/mask_load_slp_1.c: Likewise.
+ * gcc.target/aarch64/sve/mask_struct_load_1.c: Likewise.
+ * gcc.target/aarch64/sve/mask_struct_load_2.c: Likewise.
+ * gcc.target/aarch64/sve/mask_struct_load_3.c: Likewise.
+ * gcc.target/aarch64/sve/mask_struct_load_4.c: Likewise.
+ * gcc.target/aarch64/sve/mask_struct_store_1.c: Likewise.
+ * gcc.target/aarch64/sve/mask_struct_store_1_run.c: Likewise.
+ * gcc.target/aarch64/sve/mask_struct_store_2.c: Likewise.
+ * gcc.target/aarch64/sve/mask_struct_store_2_run.c: Likewise.
+ * gcc.target/aarch64/sve/pack_1.c: Likewise.
+ * gcc.target/aarch64/sve/reduc_4.c: Likewise.
+ * gcc.target/aarch64/sve/scatter_store_6.c: Likewise.
+ * gcc.target/aarch64/sve/scatter_store_7.c: Likewise.
+ * gcc.target/aarch64/sve/strided_load_3.c: Likewise.
+ * gcc.target/aarch64/sve/strided_store_3.c: Likewise.
+ * gcc.target/aarch64/sve/unpack_fcvt_signed_1.c: Likewise.
+ * gcc.target/aarch64/sve/unpack_fcvt_unsigned_1.c: Likewise.
+ * gcc.target/aarch64/sve/unpack_signed_1.c: Likewise.
+ * gcc.target/aarch64/sve/unpack_unsigned_1.c: Likewise.
+ * gcc.target/aarch64/sve/unpack_unsigned_1_run.c: Likewise.
+ * gcc.target/aarch64/sve/vcond_11.c: Likewise.
+ * gcc.target/aarch64/sve/vcond_11_run.c: Likewise.
+
+2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
+
+ * gcc.target/loongarch/vect-ld-st-imm12.c: New test.
+
+2024-01-05 chenxiaolong <chenxiaolong@loongson.cn>
+
+ * gcc.dg/fma-3.c: The intermediate file corresponding to the
+ function does not produce the corresponding FNMA symbol, so the test
+ rules should be skipped when testing.
+ * gcc.dg/fma-4.c: The intermediate file corresponding to the
+ function does not produce the corresponding FNMS symbol, so skip the
+ test rules when testing.
+ * gcc.dg/fma-6.c: The cause is the same as fma-3.c.
+ * gcc.dg/fma-7.c: The cause is the same as fma-4.c
+
+2024-01-05 chenxiaolong <chenxiaolong@loongson.cn>
+
+ * gcc.dg/vect/bb-slp-pattern-1.c: If you are testing on the
+ LoongArch architecture, you need to add the "-mlasx" compilation
+ option to generate vectorized code.
+ * gcc.dg/vect/slp-widen-mult-half.c: Dito.
+ * gcc.dg/vect/vect-widen-mult-const-s16.c: Dito.
+ * gcc.dg/vect/vect-widen-mult-const-u16.c: Dito.
+ * gcc.dg/vect/vect-widen-mult-half-u8.c: Dito.
+ * gcc.dg/vect/vect-widen-mult-half.c: Dito.
+ * gcc.dg/vect/vect-widen-mult-u16.c: Dito.
+ * gcc.dg/vect/vect-widen-mult-u8-s16-s32.c: Dito.
+ * gcc.dg/vect/vect-widen-mult-u8-u32.c: Dito.
+ * gcc.dg/vect/vect-widen-mult-u8.c: Dito.
+
+2024-01-05 chenxiaolong <chenxiaolong@loongson.cn>
+
+ * gfortran.dg/vect/pr60510.f: Delete the default behavior of the
+ program.
+
+2024-01-05 chenxiaolong <chenxiaolong@loongson.cn>
+
+ * gfortran.dg/bind_c_array_params_2.f90: Add code test rules to
+ support testing of the loongArch architecture.
+
+2024-01-05 chenxiaolong <chenxiaolong@loongson.cn>
+
+ * gcc.dg/vect/vect-82.c: Add the LoongArch architecture to the
+ object detection framework.
+ * gcc.dg/vect/vect-83.c: Dito.
+
+2024-01-05 chenxiaolong <chenxiaolong@loongson.cn>
+
+ * gcc.dg/vect/vect-bic-bitmask-12.c: Change the default
+ setting of assembly to compile.
+ * gcc.dg/vect/vect-bic-bitmask-23.c: Dito.
+
+2024-01-05 chenxiaolong <chenxiaolong@loongson.cn>
+
+ * lib/target-supports.exp: Add LoongArch to the list of supported
+ targets.
+
+2024-01-05 Alex Coplan <alex.coplan@arm.com>
+
+ PR target/113217
+ * g++.dg/pr113217.C: New test.
+
+2024-01-05 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/113201
+ * gcc.c-torture/compile/pr113201.c: New test.
+
+2024-01-05 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/90693
+ * gcc.target/i386/pr90693-2.c: New test.
+
+2024-01-05 Kito Cheng <kito.cheng@sifive.com>
+
+ * gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.h:
+ Fix the check condition.
+
+2024-01-05 Kito Cheng <kito.cheng@sifive.com>
+
+ * gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h:
+ Use __builtin_abort instead of assert.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Drop math.h.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.h: Use
+ __builtin_abort instead of assert.
+ * gcc.target/riscv/rvv/autovec/pr112694-1.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.h: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/abs-template.h: Drop stdlib.h.
+ * gcc.target/riscv/rvv/autovec/unop/vneg-template.h: Ditto.
+ * gcc.target/riscv/rvv/autovec/unop/vnot-template.h: Ditto.
+
+2024-01-05 Pan Li <pan2.li@intel.com>
+
+ Revert:
+ 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
+
+ * gcc.target/riscv/rvv/base/zvbb-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c: New test.
+ * gcc.target/riscv/rvv/base/zvbc-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c: New test.
+ * gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c: New test.
+ * gcc.target/riscv/rvv/base/zvkg-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvkned-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvknha-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvknhb-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvksed-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvksh-intrinsic.c: New test.
+ * gcc.target/riscv/zvkb.c: New test.
+
+2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
+
+ * gcc.target/riscv/rvv/base/zvbb-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c: New test.
+ * gcc.target/riscv/rvv/base/zvbc-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c: New test.
+ * gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c: New test.
+ * gcc.target/riscv/rvv/base/zvkg-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvkned-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvknha-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvknhb-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvksed-intrinsic.c: New test.
+ * gcc.target/riscv/rvv/base/zvksh-intrinsic.c: New test.
+ * gcc.target/riscv/zvkb.c: New test.
+
2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c: New test.
diff --git a/libgm2/ChangeLog b/libgm2/ChangeLog
index 803e9149b55..bac9a80edf1 100644
--- a/libgm2/ChangeLog
+++ b/libgm2/ChangeLog
@@ -1,3 +1,7 @@
+2024-01-05 Gaius Mulley <gaiusmod2@gmail.com>
+
+ * libm2iso/RTco.cc (initialized): Use bool instead of int.
+
2023-12-22 Christophe Lyon <christophe.lyon@linaro.org>
* Makefile.am: Allow overriding EXEPCT.
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index aeaa8bd0fb5..1c43b2e720e 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,44 @@
+2024-01-05 Jonathan Wakely <jwakely@redhat.com>
+
+ * src/c++17/fs_path.cc (path::_List::reserve): Limit maximum
+ size and check for overflows in arithmetic.
+ (path::operator/=(const path&)): Remove redundant exponential
+ growth calculation.
+
+2024-01-05 Martin Küttler <martin.kuettler@kernkonzept.com>
+
+ * src/c++17/fs_path.cc (path::_List::reserve): Avoid
+ floating-point arithmetic.
+
+2024-01-05 Jonathan Wakely <jwakely@redhat.com>
+
+ PR libstdc++/113241
+ * include/std/type_traits (is_convertible_v): Guard use of
+ built-in with preprocessor check.
+
+2024-01-05 Jonathan Wakely <jwakely@redhat.com>
+
+ PR libstdc++/113200
+ * include/bits/char_traits.h (__gnu_cxx::char_traits::move): Use
+ __builtin_constant_p to check for unrelated pointers that cannot
+ be compared during constant evaluation.
+ * testsuite/21_strings/char_traits/requirements/113200.cc: New
+ test.
+
+2024-01-05 Cassio Neri <cassio.neri@gmail.com>
+
+ * include/std/chrono: Fix + and - for months and weekdays.
+ * testsuite/std/time/month/1.cc: Add constexpr tests against overflow.
+ * testsuite/std/time/month/2.cc: New test for extreme values.
+ * testsuite/std/time/weekday/1.cc: Add constexpr tests against overflow.
+ * testsuite/std/time/weekday/2.cc: New test for extreme values.
+
+2024-01-05 Jonathan Wakely <jwakely@redhat.com>
+
+ PR libstdc++/113099
+ * include/bits/locale_classes.tcc (__try_use_facet): Use
+ if-constexpr for C++11 and up.
+
2024-01-05 Ken Matsui <kmatsui@gcc.gnu.org>
* include/std/type_traits: Use _GLIBCXX_USE_BUILTIN_TRAIT.
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2024-01-06 0:18 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-01-06 0:18 [gcc r14-6963] Daily bump GCC Administrator
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).