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* [newlib-cygwin] Initialize SVE system registers.
@ 2018-10-31 11:15 Richard Earnshaw
0 siblings, 0 replies; only message in thread
From: Richard Earnshaw @ 2018-10-31 11:15 UTC (permalink / raw)
To: newlib-cvs
https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;h=9a7f131e0e4dcb4833c4b5eb8c04643a05c3c7e3
commit 9a7f131e0e4dcb4833c4b5eb8c04643a05c3c7e3
Author: Tamar Christina <tamar.christina@arm.com>
Date: Fri Oct 26 10:18:17 2018 +0100
Initialize SVE system registers.
This patch initializes the SVE system registers if available
and initializes the vector length to the maximum supported.
This is done according to the SVE specification [1].
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
Diff:
---
libgloss/aarch64/cpu-init/rdimon-aem-el3.S | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/libgloss/aarch64/cpu-init/rdimon-aem-el3.S b/libgloss/aarch64/cpu-init/rdimon-aem-el3.S
index 9edbccd..e00f0b2 100644
--- a/libgloss/aarch64/cpu-init/rdimon-aem-el3.S
+++ b/libgloss/aarch64/cpu-init/rdimon-aem-el3.S
@@ -145,6 +145,33 @@ _flat_map:
dsb sy
msr sctlr_el3, x0
isb
+
+ /* Determine if SVE is available. */
+ mrs x0, id_aa64pfr0_el1
+ tbz x0, 32, .Lnosve
+
+ /* set up CPTR_EL3.TZ to 1. */
+ mrs x0, cptr_el3
+
+ /* TZ is bit 8 of CPTR_EL3. */
+ orr x0, x0, #0x100
+ msr cptr_el3, x0
+ isb
+
+ /* set up vector lenght in ZCR_EL3 (4 LSB). */
+ mov x2, #0xF
+
+ /* Try to set the maximum value supported by the architecture (2048).
+ SVE Arch.
+
+ "If this field is set to a value that is not supported by the
+ implementation then reading the register must return the highest
+ supported vector length that is less than the value written." */
+ mrs x1, s3_6_c1_c2_0 /* mrs x1, zcr_el3. */
+ bfi x1, x2, 0, 4
+ msr s3_6_c1_c2_0, x1 /* msr zcr_el3, x1. */
+ isb
+.Lnosve:
ret
.data
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