From: Sebastian Huber <sebastian.huber@embedded-brains.de>
To: Eshan Dhawan <eshandhawan51@gmail.com>, joel@rtems.org
Cc: Newlib <newlib@sourceware.org>
Subject: Re: [PATCH] Remove multiple defination error
Date: Tue, 14 Jul 2020 19:51:00 +0200 [thread overview]
Message-ID: <628c6d37-9b21-72e2-13d8-0924f5d88504@embedded-brains.de> (raw)
In-Reply-To: <CAFyWVaYp1qx_rKpsJyrOhRMLNewJh9qeQNRju7YpMW5dP4j-rw@mail.gmail.com>
On 14/07/2020 18:59, Jim Wilson wrote:
> On Tue, Jul 14, 2020 at 6:11 AM Joel Sherrill<joel@rtems.org> wrote:
>> The RISC-V would be a good model. Jim Wilson provided some default
>> behavior when there is no hard FPU.
> It wasn't me personally. This predates my involvement. I'd guess
> either Andrew Waterman, Palmer Dabbelt, or Kito Cheng. Anyways, we
> use the hard FPU if available, both for hard-float and soft-float
> ABIs. If no hard FPU, then the various fenv routines do very little,
> just returning some default values.
Ok, good.
Eshan, could you please use the RISC-V as a model for the ARM support.
Please reduce the file count. I think we just need one fenv.c and not
additional source and header files. Alternatively, you can split it up
into one file per function similar to RISC-V.
next prev parent reply other threads:[~2020-07-14 17:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-10 22:41 Eshan dhawan
2020-07-11 15:16 ` Sebastian Huber
2020-07-11 17:18 ` Eshan Dhawan
2020-07-13 5:36 ` Sebastian Huber
2020-07-13 5:48 ` Sebastian Huber
2020-07-14 13:11 ` Joel Sherrill
2020-07-14 16:59 ` Jim Wilson
2020-07-14 17:51 ` Sebastian Huber [this message]
2020-07-23 11:54 Eric Bresie
2020-07-23 12:04 ` Sebastian Huber
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