Re: Help porting newlib to a new CPU architecture (sorta)

[ElijaxApps <elijaxapps@gmail.com>]

Hi all,

I started reading GCC Internals Book, chapter 16 & 17.

I am deciding how exactly define insn statements at this very right moment.
I am using pdp11 as a template. However, there are lots of things I don't
really need, in this config spec.

As far as I have understood, I can follow two paths:

a) Define instructions as my pseudo assy, and use my own "assembler".
b) Define instructions as Linux ASM and use GAS, GNU Assembler.

At first I decided to apart A and use it as a Fallback if B fails. But I
really think I am interested in both approaches. You see, I haven't coded
any in real ASM and I just mimic'ed what it looks like.
But I am a bit lost here, I feel like A is easier but it is not the
"correct" way, but it can be done perhaps in a week or two... And let B for
the long term, as I got practice and training with A.


See the full instruction set for the moment (at the end of the document).
What I would need for A is help writing the insn definition (for A this
moment)
I'll try to define the instructions BNF so you can help me to write insn
definitions:

*Offset*: [ 000000-ffffff ] [h] | <variable_name>
*1) LDx *(Load REG from the BUS):   [ LDA | LDB | LDC | LDD ]
offset_to_load
*2) STx *(Store REG in RAM):   [ STA | STB | STC | STD ]
offset_where_to_store
*3) ADD,SUB*: [ ADD | SUB ] offset (to whatever already there is in A REG)
*4) Jumps*: Always redirect to another direction in RAM, so they always are
followed by an offset.
*5) Branches*: Always redirect to another direction in RAM, this time a
function beginning offset. They return a 24 bit address, and continue
execution below where Branch was called.
*6)* *DEC *(Read char and store in A REG) *Is all hardwired, is just the
mnemonic - DEC - (cannot use another REG)
*7) OUTx *(Output REG on LCD Screen)   [ OUTA | OUTB | OUTC | OUTD ]
*8) NOP, HLT *are just the mnemonic.

MOV is not fully supported yet...
"Spawning" a value into any register is not supported yet. You have to
previously store the value you'll load into RAM. I have to encode ASCII
table in the firmware, yet I not had time.

So I need basically 2 TWO isns:


*[ LDx | STx | Bx | Jx | ADD | SUB ] <offset> (24 bit hexadecimal, or
variable name)[ DEC | OUTx | HLT | NOP ] - as is, just the mnemonic...*


So that way I could continue the reading and go on.

Thank You,
Elijax Apps.

Code tokenMeaningExamples
;; This is a comment. line will be ignored ;;This is a comment
LDA Basic load A register. Always followed by a variable name or an memory
address (up to 24 bit) LDA one
LDA ff0010h
LDB Same as LDA with B register
LDC Same as LDA with C register
LDD Same as LDA with D register
STA Store contents of register A into the following address memory (also up
to 24 bit) STA one
STA ff0010h
STB Same as STA with B register
STC Same as STA with C register
STD Same as STA with D register
OUTA Echoes the value of register A to LCD Screen LDA one
OUTA (prints value of variable "one")
OUTB Same as OUTA with B register
OUTC Same as OUTA with C register
OUTD Same as OUTA with D register
DEC Reads a byte from keyboard and stores in A register DEC
STA readChar
ADD Adds the value of the following address or variable to the contents of
register A DEC
ADD one
SUB Substracts the value of the following address or variable to the
contents of register A DEC
ADD one
JZ Jumps to the specified address or to specified address contained within
a variable if Zero Flag == 0 JZ addressToJumpTo, JZ 0000ffh
JNZ Jumps to the specified address or to specified address contained within
a variable if Zero Flag != 0 JNZ addressToJumpTo, JNZ 0000ffh
JC Jumps to the specified address or to specified address contained within
a variable if Carry Flag == 0 JC addressToJumpTo, JC 0000ffh
JNC Jumps to the specified address or to specified address contained within
a variable if Carry Flag != 0 JNC addressToJumpTo, JNC 0000ffh
J Jumps always J addressToJumpTo
BZ Creates a branch (calls a function) if Zero Flag == 0 BZ offsetOfFunction
BNZ Creates a branch (calls a function) if Zero Flag != 0 BNZ
offsetOfFunction
BC Creates a branch (calls a function) Carry Flag == 0 BC offsetOfFunction
BNC Creates a branch (calls a function) if Carry Flag != 0 BNC
offsetOfFunction
B Creates a branch (calls a function) always it is found B offsetOfFunction
BX Returns a value contained in the following address BX returnValueAddress
NOP No operation. Just reads the next operation NOP
HLT Halts the computer HLT
MOV Limited, not documented support for some MOV operations. SEE THE
CODE!!! MOV
A, C

El mar, 6 jul 2021 a las 15:05, Paul Koning (<paulkoning@comcast.net>)
escribió:

>
>
> > On Jul 6, 2021, at 12:35 AM, Mike Frysinger <vapier@gentoo.org> wrote:
> >
> > On 06 Jul 2021 02:49, ElijaxApps wrote:
> >> I designed a Logisim schematic of a full system, able to run programs in
> >> the simulation, as shown in this video:
> >>
> >> https://www.youtube.com/watch?v=UP6tO8x5I5A
> >>
> >> Is based on a SAP-1 (Simplest as Possible) basis, containing 4 GP
> registers
> >> (8 bit), stack for function operations (up to 256 depth levels of
> >> recursivity), 24bit plain RAM component, and a simple ALU able to echo
> >> strings and perform not floating point math.
> >>
> >> AFAIK, newlib is suitable for embedded devices, and I want to create the
> >> full toolchain for C/C++ language at least.
> >
> > i don't know that these would work that well (or at all) on an 8-bit CPU.
> > you'd really want a 32-bit CPU nowadays as a minimum if you want to
> support
> > modern software.
>
> Consider the AVR toolchain, used in Arduino.  Isn't that an 8-bit
> machine?  It certainly is small.
>
>         paul
>
>
>