From: Orlando Arias <orlandoarias@gmail.com>
To: newlib@sourceware.org
Subject: Re: Help porting newlib to a new CPU architecture (sorta)
Date: Wed, 7 Jul 2021 09:58:36 -0400 [thread overview]
Message-ID: <a528ba87-a964-1a57-73be-96e4f329345f@gmail.com> (raw)
In-Reply-To: <54a6bb07-717c-ddf2-3e84-822c523b9035@SystematicSw.ab.ca>
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Greetings,
On 7/7/21 1:45 AM, Brian Inglis wrote:
> Function and object pointer inter-conversions are UB - daemons fly out
> your nose! For example, when code and data model pointer sizes are
> different, pointers are physically incompatible.
Yes, such is with the case of AVR. Attempting to cast a function pointer
to a data pointer and dereferencing writes to that new pointer is a nice
way to bring about disaster.
>> However, the implementations I have seen would treat this pointer as
>> something in data memory, rather than something in program memory.
>> Actually modifying what fn_ptr points to would require the use of an
>> extension to the language [which would be implied if the behavior was
>> indeed UB or implementation defined]. Please correct me on this one.
>
> Works on von Neumann architecture implementations, or where mapping
> registers map the same address ranges for code and data, perhaps with
> different access modes.
> Modifying what a function pointer object points to is fairly common in
> C, as long as when they are used, they are (cast to) a pointer to a
> function of the correct type; c.f. qsort pointer to comparison function
> in its last argument, and Unix system driver interfaces which are
> effectively arrays of function pointers.
>
I have done similar to this before: mapping a page as RWX, writing to
it, then jumping to it to execute code. It was done as a way to
demonstrate shellcode injection in AMD64. I also had a few students do
something similar on an MSP430 for a homework [gave them a binary with a
vulnerability, had them reverse engineer it, then exploit it to trigger
certain behaviors to get points in the assignment].
> If you look at e.g the PDP11 architecture, somewhat similar 6800 series
> models, or the like, it had a number of mainly orthogonal general
> register addressing modes, including PC relative, indirect PC relative,
> and either with autoinc-/decrement, so it could use many registers to
> access "program" memory, absolute "program" addresses, and move through
> that space like an IP for threaded code, or as a subroutine stack, or
> access RO data in the instruction space directly.
> For example, to copy RO instruction space data to RAM, the move source
> register uses autoincrement PC relative addressing and the destination
> register uses autoincrement relative addressing from a RAM base address.
Speaking of, this sounds a lot like the MSP430 ISA. I do recall reading
somewhere that the MSP430 ISA was rather similar to the PDP11's. I can
not recall where I found that bit though. I have never used a PDP11
before, acquiring [and possibly restoring] one is in my to do list.
Anyway, thank you for your time and insights.
Cheers,
Orlando.
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next prev parent reply other threads:[~2021-07-07 13:57 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-06 0:49 ElijaxApps
2021-07-06 4:35 ` Mike Frysinger
2021-07-06 13:05 ` Paul Koning
2021-07-07 20:32 ` ElijaxApps
2021-07-07 20:56 ` Orlando Arias
2021-07-06 14:02 ` Brian Inglis
2021-07-06 14:35 ` Orlando Arias
2021-07-06 18:08 ` Brian Inglis
2021-07-06 19:04 ` Orlando Arias
2021-07-06 20:01 ` Hans-Bernhard Bröker
2021-07-06 20:46 ` Orlando Arias
2021-07-07 5:45 ` Brian Inglis
2021-07-07 13:58 ` Orlando Arias [this message]
2021-07-07 15:18 ` Dave Nadler
2021-07-07 18:43 ` Hans-Bernhard Bröker
2021-07-07 20:23 ` Orlando Arias
2021-07-06 21:08 ElijaxApps
2021-07-06 22:00 ` Joel Sherrill
2021-07-06 23:50 ` Paul Koning
2021-07-07 0:29 ` ElijaxApps
2021-07-07 15:09 ` Grant Edwards
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