SID/CGEN IRQ bug

SID/CGEN IRQ bug

[Robert Shideleff]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

I am sending this to both the SID and CGEN mailing lists because I am not sure 
who would be in a position to fix this.

The SID model of the arm7t currently enters an interrupt in a way that 
resembles edge detected interrupts in hardware. (It doesn't model them 
perfectly, because it currently doesn't sense high-to-low transitions. 
Instead, any call to drive the pin low no matter what state it is currently 
in will spark an interrupt.)

However, regardless of the correctness of how the edge detected interrupts are 
currently modeled, the arm7 irq pin is actually level sensitive, not edge 
sensitive. This means that any attempt to model interrupt clearing and 
setting cannot be made accurate. As an example, eCos depends on the level 
sensitive behavior of interrupts. Otherwise, if multiple interrupts arrive at 
the same time, it will miss all but one of them.

There is an incredibly trivial way to fix this in the already comgen'ed code. 
I would simply modify the function that sets cpsr to check the sense of the 
two interrupt pins and drive another irq if necessary. But this wouldn't fix 
the original code. I looked through the compgen stuff, and got completely 
lost. Is there anybody out there who knows how to fix this in the compgen 
code?

Bob
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.4 (GNU/Linux)

iD8DBQFA5FWR8XjOGQDr37YRAvlKAKCKGjrYiRDU6typvSPUgmeuI12HTACfSnAC
dyIlHVNVcg9qlLcMNtfOJcM=
=DCFz
-----END PGP SIGNATURE-----

Re: SID/CGEN IRQ bug

[Robert Shideleff]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Upon further reflection, I found that it could/should be done entirely within 
the sid code. (cgen people can ignore my previous email.) Patch file 
forthcoming on SID mail list.

Bob
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.4 (GNU/Linux)

iD8DBQFA5al18XjOGQDr37YRAg6oAKCqpUd4O030Fletyyg+ANgEY40fGACcC80D
zcloCYxp03ZMtLp2SVYGTEo=
=3Mvd
-----END PGP SIGNATURE-----