From: Ben Elliston <bje@au.ibm.com>
To: sid@sources.redhat.com
Subject: Re: Level sensitive ARM interrupts
Date: Mon, 05 Jul 2004 00:27:00 -0000 [thread overview]
Message-ID: <87eknr70xk.fsf@au.ibm.com> (raw)
In-Reply-To: <200407021439.08654.bigbob@shideleff.com>
Robert Shideleff <bigbob@shideleff.com> writes:
> This patch makes arm interrupts level sensitive, as they are in hardware.
> The nirq and nfiq pins are no longer callbacks, but rather simple input
> pins. They are 'pulled' to high at processor invocation and reset. Their
> level is 'sense()-ed' at the beginning of each step.
>
> The patch file was taken from within the sid/component/cgen-cpu/arm7t
> directory.
>
> This is necessary for proper operation of eCos, and for the ability to
> model interrupts as they occur in actual hardware.
There are a number of ARM-related interrupt tests which, from
recollection, passed. Does your patch suggest that the tests are
wrong? If so, can you update them, too?
Ben
next prev parent reply other threads:[~2004-07-05 0:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-07-02 18:37 Robert Shideleff
2004-07-02 18:39 ` Robert Shideleff
2004-07-05 0:27 ` Ben Elliston [this message]
[not found] ` <200407141850.05451.bigbob@shideleff.com>
[not found] ` <20040804023021.GA16871@redhat.com>
[not found] ` <200408041117.50677.bigbob@shideleff.com>
2004-08-04 15:43 ` Frank Ch. Eigler
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