[binutils-gdb] Arm64: check tied operand specifier in aarch64-gen

[binutils-gdb] Arm64: check tied operand specifier in aarch64-gen

[Jan Beulich]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=b1c4af2086db25da1acf546b28df5b6fe8198cd6

commit b1c4af2086db25da1acf546b28df5b6fe8198cd6
Author: Jan Beulich <jbeulich@suse.com>
Date:   Wed Apr 3 10:42:44 2024 +0200

    Arm64: check tied operand specifier in aarch64-gen
    
    Make sure that field actually matches the specified operands. Don't
    follow existing F_PSEUDO checking in using assertions, though. Print
    meaningful error messages, thus - while not having a line number
    available - at least providing some indication of where things are
    wrong.
    
    Fix SVE2.1's extq accordingly, but don't extend the testsuite there:
    There are further issues with its operands (SVE_Zm_imm4 doesn't look to
    be correct to use there, as that describes an indexed vector register,
    while here a separate vector register and immediate operand are to be
    specified).

Diff:
---
 opcodes/aarch64-gen.c | 37 +++++++++++++++++++++++++++++++++++++
 opcodes/aarch64-tbl.h |  2 +-
 2 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c
index eab1add0ce2..02dcde1f676 100644
--- a/opcodes/aarch64-gen.c
+++ b/opcodes/aarch64-gen.c
@@ -129,6 +129,7 @@ read_table (const struct aarch64_opcode* table)
   const struct aarch64_opcode *ent = table;
   opcode_node **new_ent;
   unsigned int index = initialize_index (table);
+  unsigned int errors = 0;
 
   if (!ent->name)
     return;
@@ -140,6 +141,8 @@ read_table (const struct aarch64_opcode* table)
 
   do
     {
+      bool match = false;
+
       /* F_PSEUDO needs to be used together with F_ALIAS to indicate an alias
 	 opcode is a programmer friendly pseudo instruction available only in
 	 the assembly code (thus will not show up in the disassembly).  */
@@ -150,12 +153,46 @@ read_table (const struct aarch64_opcode* table)
 	  index++;
 	  continue;
 	}
+
+      /* Check tied_operand against operands[].  */
+      for (unsigned int i = 1; i < ARRAY_SIZE (ent->operands); ++i)
+	{
+	  if (ent->operands[i] == AARCH64_OPND_NIL)
+	    break;
+
+	  if (ent->operands[i] != ent->operands[0])
+	    continue;
+	  match = true;
+
+	  if (i != ent->tied_operand)
+	    {
+	      fprintf (stderr,
+		       "%s (%08x,%08x): operands 1 and %u match, but tied=%u\n",
+		       ent->name, ent->opcode, ent->mask, i + 1, ent->tied_operand);
+	      ++errors;
+	    }
+	}
+      if (!match && ent->tied_operand
+	  /* SME LDR/STR (array vector) tie together inner immediates only.  */
+	  && ent->iclass != sme_ldr && ent->iclass != sme_str)
+	{
+	  fprintf (stderr, "%s: no operands match, but tied=%u\n",
+		   ent->name, ent->tied_operand);
+	  ++errors;
+	}
+
       *new_ent = new_opcode_node ();
       (*new_ent)->opcode = ent->opcode;
       (*new_ent)->mask = ent->mask;
       (*new_ent)->index = index++;
       new_ent = &((*new_ent)->next);
     } while ((++ent)->name);
+
+  if (errors)
+    {
+      fprintf (stderr, "%u errors, exiting\n", errors);
+      xexit (3);
+    }
 }
 
 static inline void
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5b1c8561ac6..356d303bc1a 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6425,7 +6425,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
 
   SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
-  SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 0),
+  SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 1),
   SVE2p1_INSNC("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zt, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS_QD, 0, C_SCAN_MOVPRFX, 0),
   SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
   SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),