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From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Subject: [PATCH 1/5] x86/Intel: adjust representation of embedded broadcast
Date: Wed, 4 May 2022 13:57:29 +0200	[thread overview]
Message-ID: <0af2ae4a-d0d5-5d90-a607-3fc89604e208@suse.com> (raw)
In-Reply-To: <26c648e6-d76b-052e-6392-48265a859a7c@suse.com>

[-- Attachment #1: Type: text/plain, Size: 2654 bytes --]

MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling
DWORD PTR) and alike are to be used there instead. Make the disassembler
follow this first, before also adjusting the assembler (such that it'll
be easy to see that the assembler change doesn't alter generated code).

For VFPCLASSP{S,D,H} and vector conversions with shrinking element sizes
the original {1to<n>} operand suffix is retained, to disambiguate
output. I have no insight (yet) into how MASM expects those to be
disambiguated.
---
Presenting only the non-testsuite changes inline. See attachment for the
full patch.

--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -267,6 +267,7 @@ struct instr_info
 
 
 #define EVEX_b_used 1
+#define EVEX_len_used 2
 
 /* Flags stored in PREFIXES.  */
 #define PREFIX_REPZ 1
@@ -10931,14 +10932,14 @@ intel_operand_size (instr_info *ins, int
 	  case x_mode:
 	  case evex_half_bcst_xmmq_mode:
 	    if (ins->vex.w)
-	      oappend (ins, "QWORD PTR ");
+	      oappend (ins, "QWORD BCST ");
 	    else
-	      oappend (ins, "DWORD PTR ");
+	      oappend (ins, "DWORD BCST ");
 	    break;
 	  case xh_mode:
 	  case evex_half_bcst_xmmqh_mode:
 	  case evex_half_bcst_xmmqdh_mode:
-	    oappend (ins, "WORD PTR ");
+	    oappend (ins, "WORD BCST ");
 	    break;
 	  default:
 	    ins->vex.no_broadcast = true;
@@ -11768,7 +11769,8 @@ OP_E_memory (instr_info *ins, int bytemo
       if (ins->obufp == ins->op_out[0])
 	ins->vex.no_broadcast = true;
 
-      if (!ins->vex.no_broadcast)
+      if (!ins->vex.no_broadcast
+	  && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
 	{
 	  if (bytemode == xh_mode)
 	    {
@@ -12484,6 +12486,7 @@ print_vector_reg (instr_info *ins, unsig
 	  break;
 	case 512:
 	  names = att_names_ymm;
+	  ins->evex_used |= EVEX_len_used;
 	  break;
 	default:
 	  abort ();
@@ -12512,6 +12515,7 @@ print_vector_reg (instr_info *ins, unsig
 	   && bytemode != d_mode
 	   && bytemode != q_mode)
     {
+      ins->evex_used |= EVEX_len_used;
       switch (ins->vex.length)
 	{
 	case 128:
@@ -13237,6 +13241,7 @@ OP_VEX (instr_info *ins, int bytemode, i
 	{
 	case x_mode:
 	  names = att_names_xmm;
+	  ins->evex_used |= EVEX_len_used;
 	  break;
 	case dq_mode:
 	  if (ins->rex & REX_W)
@@ -13263,6 +13268,7 @@ OP_VEX (instr_info *ins, int bytemode, i
 	{
 	case x_mode:
 	  names = att_names_ymm;
+	  ins->evex_used |= EVEX_len_used;
 	  break;
 	case mask_bd_mode:
 	case mask_mode:
@@ -13281,6 +13287,7 @@ OP_VEX (instr_info *ins, int bytemode, i
       break;
     case 512:
       names = att_names_zmm;
+      ins->evex_used |= EVEX_len_used;
       break;
     default:
       abort ();

[-- Attachment #2: binutils-master-x86-AVX512-broadcast-Intel-dis.patch.bz2 --]
[-- Type: application/octet-stream, Size: 207876 bytes --]

  reply	other threads:[~2022-05-04 11:57 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-04 11:44 [PATCH 0/5] x86/Intel: AVX512 syntax enhancements Jan Beulich
2022-05-04 11:57 ` Jan Beulich [this message]
2022-05-04 11:58 ` [PATCH 2/5] x86/Intel: allow MASM representation of embedded broadcast Jan Beulich
2022-05-04 11:59 ` [PATCH 3/5] x86/Intel: adjust representation of embedded rounding / SAE Jan Beulich
2022-05-04 12:00 ` [PATCH 4/5] x86: re-work AVX512 " Jan Beulich
2022-05-04 12:01 ` [PATCH 5/5] x86/Intel: allow MASM representation of " Jan Beulich
2022-05-10  2:37 ` [PATCH 0/5] x86/Intel: AVX512 syntax enhancements Cui, Lili
2022-05-17 12:00   ` Jan Beulich
2022-05-18  3:15     ` Cui, Lili
2022-05-18  6:40       ` Jan Beulich
2022-05-18 15:07         ` H.J. Lu
2022-05-25  7:44 ` Jan Beulich
2022-05-26 14:48   ` H.J. Lu

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