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From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Subject: [PATCH 3/5] x86/Intel: adjust representation of embedded rounding / SAE
Date: Wed, 4 May 2022 13:59:36 +0200	[thread overview]
Message-ID: <c24265af-ca0c-c3d1-ad9b-1e32f5192928@suse.com> (raw)
In-Reply-To: <26c648e6-d76b-052e-6392-48265a859a7c@suse.com>

[-- Attachment #1: Type: text/plain, Size: 1946 bytes --]

MASM doesn't consider {sae} and alike a separate operand; it is attached
to the last register operand instead, just like spelled out by the SDM.
Make the disassembler follow this first, before also adjusting the
assembler (such that it'll be easy to see that the assembler change
doesn't alter generated code).
---
Presenting only the non-testsuite changes inline. See attachment for the
full patch.

--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -9313,6 +9313,7 @@ print_insn (bfd_vma pc, instr_info *ins)
   int i;
   char *op_txt[MAX_OPERANDS];
   int needcomma;
+  bool intel_swap_2_3;
   int sizeflag, orig_sizeflag;
   const char *p;
   struct dis_private priv;
@@ -9770,6 +9771,7 @@ print_insn (bfd_vma pc, instr_info *ins)
 
   /* The enter and bound instructions are printed with operands in the same
      order as the intel book; everything else is printed in reverse order.  */
+  intel_swap_2_3 = false;
   if (ins->intel_syntax || ins->two_source_ops)
     {
       for (i = 0; i < MAX_OPERANDS; ++i)
@@ -9780,6 +9782,7 @@ print_insn (bfd_vma pc, instr_info *ins)
 	{
 	  op_txt[2] = ins->op_out[3];
 	  op_txt[3] = ins->op_out[2];
+	  intel_swap_2_3 = true;
 	}
 
       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
@@ -9804,6 +9807,20 @@ print_insn (bfd_vma pc, instr_info *ins)
   for (i = 0; i < MAX_OPERANDS; ++i)
     if (*op_txt[i])
       {
+	/* In Intel syntax embedded rounding / SAE are not separate operands.
+	   Instead they're attached to the prior register operand.  Simply
+	   suppress emission of the comma to achieve that effect.  */
+	switch (i & -(ins->intel_syntax && dp))
+	  {
+	  case 2:
+	    if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
+	      needcomma = 0;
+	    break;
+	  case 3:
+	    if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
+	      needcomma = 0;
+	    break;
+	  }
 	if (needcomma)
 	  (*ins->info->fprintf_styled_func) (ins->info->stream,
 					     dis_style_text, ",");

[-- Attachment #2: binutils-master-x86-AVX512-SAE-Intel-dis.patch.bz2 --]
[-- Type: application/octet-stream, Size: 89855 bytes --]

  parent reply	other threads:[~2022-05-04 11:59 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-04 11:44 [PATCH 0/5] x86/Intel: AVX512 syntax enhancements Jan Beulich
2022-05-04 11:57 ` [PATCH 1/5] x86/Intel: adjust representation of embedded broadcast Jan Beulich
2022-05-04 11:58 ` [PATCH 2/5] x86/Intel: allow MASM " Jan Beulich
2022-05-04 11:59 ` Jan Beulich [this message]
2022-05-04 12:00 ` [PATCH 4/5] x86: re-work AVX512 embedded rounding / SAE Jan Beulich
2022-05-04 12:01 ` [PATCH 5/5] x86/Intel: allow MASM representation of " Jan Beulich
2022-05-10  2:37 ` [PATCH 0/5] x86/Intel: AVX512 syntax enhancements Cui, Lili
2022-05-17 12:00   ` Jan Beulich
2022-05-18  3:15     ` Cui, Lili
2022-05-18  6:40       ` Jan Beulich
2022-05-18 15:07         ` H.J. Lu
2022-05-25  7:44 ` Jan Beulich
2022-05-26 14:48   ` H.J. Lu

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