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* [PATCH] RISC-V: Update zfinx implement with zicsr.
@ 2022-05-20 10:09 jiawei
  2022-05-20 12:05 ` Tsukasa OI
  0 siblings, 1 reply; 3+ messages in thread
From: jiawei @ 2022-05-20 10:09 UTC (permalink / raw)
  To: binutils
  Cc: nelson.chu, palmer, jim.wilson.gcc, kito.cheng, philipp.tomsich,
	christoph.muellner, tariqandlaura, wuwei2016, Jia-Wei Chen

From: Jia-Wei Chen <jiawei@iscas.ac.cn>

Update zfinx implement with zicsr, fix missing fcsr use by zfinx.
add zicsr imply by zfinx.

bfd/ChangeLog:

        * elfxx-riscv.c: New imply.

gas/ChangeLog:

        * testsuite/gas/riscv/csr-insns-pseudo-zfinx.d: New test.

opcodes/ChangeLog:

        * riscv-opc.c: Update insn class.

---
 bfd/elfxx-riscv.c                             |  1 +
 .../gas/riscv/csr-insns-pseudo-zfinx.d        | 36 +++++++++++++++++++
 opcodes/riscv-opc.c                           | 28 +++++++--------
 3 files changed, 51 insertions(+), 14 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 069832fece7..b2806185fa8 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1104,6 +1104,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zfh", "zicsr",	check_implicit_always},
   {"zqinx", "zdinx",	check_implicit_always},
   {"zdinx", "zfinx",	check_implicit_always},
+  {"zfinx", "zicsr",	check_implicit_always},
   {"zk", "zkn",		check_implicit_always},
   {"zk", "zkr",		check_implicit_always},
   {"zk", "zkt",		check_implicit_always},
diff --git a/gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d b/gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d
new file mode 100644
index 00000000000..6e86398cf7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d
@@ -0,0 +1,36 @@
+#source: csr-insns-pseudo.s
+#as: -march=rv32i_zfinx
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <pseudo_csr_insn>:
+[ 	]+[0-9a-f]+:[ 	]+000022f3[ 	]+csrr[ 	]+t0,ustatus
+[ 	]+[0-9a-f]+:[ 	]+00029073[ 	]+csrw[ 	]+ustatus,t0
+[ 	]+[0-9a-f]+:[ 	]+0002a073[ 	]+csrs[ 	]+ustatus,t0
+[ 	]+[0-9a-f]+:[ 	]+0002b073[ 	]+csrc[ 	]+ustatus,t0
+[ 	]+[0-9a-f]+:[ 	]+000fd073[ 	]+csrwi[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+000fe073[ 	]+csrsi[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+000ff073[ 	]+csrci[ 	]+ustatus,31
+[ 	]+[0-9a-f]+:[ 	]+c00022f3[ 	]+rdcycle[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+c01022f3[ 	]+rdtime[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+c02022f3[ 	]+rdinstret[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+c80022f3[ 	]+rdcycleh[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+c81022f3[ 	]+rdtimeh[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+c82022f3[ 	]+rdinstreth[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+003022f3[ 	]+frcsr[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+003392f3[ 	]+fscsr[ 	]+t0,t2
+[ 	]+[0-9a-f]+:[ 	]+00339073[ 	]+fscsr[ 	]+t2
+[ 	]+[0-9a-f]+:[ 	]+002022f3[ 	]+frrm[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+002312f3[ 	]+fsrm[ 	]+t0,t1
+[ 	]+[0-9a-f]+:[ 	]+00231073[ 	]+fsrm[ 	]+t1
+[ 	]+[0-9a-f]+:[ 	]+002fd2f3[ 	]+fsrmi[ 	]+t0,31
+[ 	]+[0-9a-f]+:[ 	]+002fd073[ 	]+fsrmi[ 	]+zero,31
+[ 	]+[0-9a-f]+:[ 	]+001022f3[ 	]+frflags[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+001312f3[ 	]+fsflags[ 	]+t0,t1
+[ 	]+[0-9a-f]+:[ 	]+00131073[ 	]+fsflags[ 	]+t1
+[ 	]+[0-9a-f]+:[ 	]+001fd2f3[ 	]+fsflagsi[ 	]+t0,31
+[ 	]+[0-9a-f]+:[ 	]+001fd073[ 	]+fsflagsi[ 	]+zero,31
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 7524be7feae..2a41db0a440 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -638,22 +638,22 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fcvt.h.lu", 64, INSN_CLASS_ZFH,  "D,s,m",     MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
 
 /* Single-precision floating-point instruction subset.  */
-{"frcsr",      0, INSN_CLASS_F,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
-{"frsr",       0, INSN_CLASS_F,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
-{"fscsr",      0, INSN_CLASS_F,   "s",         MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS },
-{"fscsr",      0, INSN_CLASS_F,   "d,s",       MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
-{"fssr",       0, INSN_CLASS_F,   "s",         MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS },
-{"fssr",       0, INSN_CLASS_F,   "d,s",       MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
-{"frrm",       0, INSN_CLASS_F,   "d",         MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS },
-{"fsrm",       0, INSN_CLASS_F,   "s",         MATCH_FSRM, MASK_FSRM|MASK_RD, match_opcode, INSN_ALIAS },
-{"fsrm",       0, INSN_CLASS_F,   "d,s",       MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
-{"fsrmi",      0, INSN_CLASS_F,   "d,Z",       MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS },
-{"fsrmi",      0, INSN_CLASS_F,   "Z",         MATCH_FSRMI, MASK_FSRMI|MASK_RD, match_opcode, INSN_ALIAS },
+{"frcsr",      0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+{"frsr",       0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+{"fscsr",      0, INSN_CLASS_F_OR_ZFINX,   "s",         MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS },
+{"fscsr",      0, INSN_CLASS_F_OR_ZFINX,   "d,s",       MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
+{"fssr",       0, INSN_CLASS_F_OR_ZFINX,   "s",         MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS },
+{"fssr",       0, INSN_CLASS_F_OR_ZFINX,   "d,s",       MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
+{"frrm",       0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS },
+{"fsrm",       0, INSN_CLASS_F_OR_ZFINX,   "s",         MATCH_FSRM, MASK_FSRM|MASK_RD, match_opcode, INSN_ALIAS },
+{"fsrm",       0, INSN_CLASS_F_OR_ZFINX,   "d,s",       MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
+{"fsrmi",      0, INSN_CLASS_F_OR_ZFINX,   "d,Z",       MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS },
+{"fsrmi",      0, INSN_CLASS_F_OR_ZFINX,   "Z",         MATCH_FSRMI, MASK_FSRMI|MASK_RD, match_opcode, INSN_ALIAS },
 {"frflags",    0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
 {"fsflags",    0, INSN_CLASS_F_OR_ZFINX,   "s",         MATCH_FSFLAGS, MASK_FSFLAGS|MASK_RD, match_opcode, INSN_ALIAS },
-{"fsflags",    0, INSN_CLASS_F,   "d,s",       MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS },
-{"fsflagsi",   0, INSN_CLASS_F,   "d,Z",       MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS },
-{"fsflagsi",   0, INSN_CLASS_F,   "Z",         MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS },
+{"fsflags",    0, INSN_CLASS_F_OR_ZFINX,   "d,s",       MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS },
+{"fsflagsi",   0, INSN_CLASS_F_OR_ZFINX,   "d,Z",       MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS },
+{"fsflagsi",   0, INSN_CLASS_F_OR_ZFINX,   "Z",         MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS },
 {"flw",       32, INSN_CLASS_F_AND_C, "D,Cm(Cc)",  MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
 {"flw",       32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
 {"flw",        0, INSN_CLASS_F,   "D,o(s)",    MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
-- 
2.25.1


^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-05-20 14:24 UTC | newest]

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2022-05-20 10:09 [PATCH] RISC-V: Update zfinx implement with zicsr jiawei
2022-05-20 12:05 ` Tsukasa OI
2022-05-20 14:24   ` Nelson Chu

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