From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: binutils@sourceware.org
Cc: Kito Cheng <kito.cheng@sifive.com>,
Nelson Chu <nelson.chu@sifive.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [RFC PATCH v1] RISC-V: Support Zicond extension
Date: Sat, 21 Jan 2023 01:29:34 +0100 [thread overview]
Message-ID: <20230121002935.1139281-1-philipp.tomsich@vrull.eu> (raw)
*** Zicond is not FROZEN at this time. Do not merge until FROZEN. ***
This implements the Zicond (conditional integer operations) extension,
as of version 1.0-draft-20230120.
The Zicond extension acts as a building block for branchless sequences
including conditional-arithmetic, conditional-logic and
conditional-select/move.
The following instructions constitute Zicond:
- czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1
- czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1
See
https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf
for the proposed specification and usage details.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Recognize
INSN_CLASS_XVENTANACONDOPS.
(riscv_multi_subset_supports_ext): Recognize
INSN_CLASS_XVENTANACONDOPS,
gas/ChangeLog:
* testsuite/gas/riscv/zicond.d: New test.
* testsuite/gas/riscv/zicond.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define.
(MASK_CZERO_EQZ): Define.
(MATCH_CZERO_NEZ): Define,
(MASK_CZERO_NEZ): Define.
(DECLARE_INSN): Add czero.eqz and czero.nez.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZICOND
opcodes/ChangeLog:
* riscv-opc.c: Add czero.eqz and czero.nez.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zicond.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zicond.s | 3 +++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
6 files changed, 33 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zicond.d
create mode 100644 gas/testsuite/gas/riscv/zicond.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index a48d6300a1f..ec69c7fdc4d 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1168,6 +1168,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
@@ -2267,6 +2268,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zicbop");
case INSN_CLASS_ZICBOZ:
return riscv_subset_supports (rps, "zicboz");
+ case INSN_CLASS_ZICOND:
+ return riscv_subset_supports (rps, "zicond");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
@@ -2435,6 +2438,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "zicbop";
case INSN_CLASS_ZICBOZ:
return "zicboz";
+ case INSN_CLASS_ZICOND:
+ return "zicond";
case INSN_CLASS_ZICSR:
return "zicsr";
case INSN_CLASS_ZIFENCEI:
diff --git a/gas/testsuite/gas/riscv/zicond.d b/gas/testsuite/gas/riscv/zicond.d
new file mode 100644
index 00000000000..7a79ee6a716
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicond.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zicond
+#source: zicond.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+0ec5d533[ ]+czero.eqz[ ]+a0,a1,a2
+[ ]+4:[ ]+0ee6f533[ ]+czero.nez[ ]+a0,a3,a4
diff --git a/gas/testsuite/gas/riscv/zicond.s b/gas/testsuite/gas/riscv/zicond.s
new file mode 100644
index 00000000000..4e5edd5056a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicond.s
@@ -0,0 +1,3 @@
+target:
+ czero.eqz a0, a1, a2
+ czero.nez a0, a3, a4
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 32b160660d3..c99756e47e1 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2187,6 +2187,11 @@
#define MASK_CBO_INVAL 0xfff07fff
#define MATCH_CBO_ZERO 0x40200f
#define MASK_CBO_ZERO 0xfff07fff
+/* Zicond instructions. */
+#define MATCH_CZERO_EQZ 0xe005033
+#define MASK_CZERO_EQZ 0xfe00707f
+#define MATCH_CZERO_NEZ 0xe007033
+#define MASK_CZERO_NEZ 0xfe00707f
/* Zawrs intructions. */
#define MATCH_WRS_NTO 0x00d00073
#define MASK_WRS_NTO 0xffffffff
@@ -3194,6 +3199,9 @@ DECLARE_INSN(cbo_clean, MATCH_CBO_CLEAN, MASK_CBO_CLEAN);
DECLARE_INSN(cbo_flush, MATCH_CBO_FLUSH, MASK_CBO_FLUSH);
DECLARE_INSN(cbo_inval, MATCH_CBO_INVAL, MASK_CBO_INVAL);
DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
+/* Zicond instructions. */
+DECLARE_INSN(czero_eqz, MATCH_CZERO_EQZ, MASK_CZERO_EQZ)
+DECLARE_INSN(czero_nez, MATCH_CZERO_NEZ, MASK_CZERO_NEZ)
/* Zawrs instructions. */
DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 57bea48704d..dfab0502d49 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -379,6 +379,7 @@ enum riscv_insn_class
INSN_CLASS_Q,
INSN_CLASS_F_AND_C,
INSN_CLASS_D_AND_C,
+ INSN_CLASS_ZICOND,
INSN_CLASS_ZICSR,
INSN_CLASS_ZIFENCEI,
INSN_CLASS_ZIHINTPAUSE,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 639683e76b1..33cd4ab57d1 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -935,6 +935,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
+/* Zicond instructions. */
+{"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 },
+{"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 },
+
/* Zawrs instructions. */
{"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
{"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },
--
2.34.1
next reply other threads:[~2023-01-21 0:29 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-21 0:29 Philipp Tomsich [this message]
2023-01-26 0:26 ` Jeff Law
2023-01-26 1:02 ` Andrew Waterman
2023-03-01 1:58 ` Nelson Chu
2023-03-01 2:03 ` Palmer Dabbelt
2023-06-19 14:21 ` Philipp Tomsich
2023-06-21 4:25 ` Jeff Law
2023-06-21 4:38 ` Palmer Dabbelt
2023-06-27 13:27 ` Jeff Law
2023-06-27 14:32 ` Philipp Tomsich
2023-06-27 23:12 ` Jeff Law
2023-06-27 23:33 ` Palmer Dabbelt
2023-06-27 14:48 ` Palmer Dabbelt
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