Re: [RFC PATCH v1] RISC-V: Support Zicond extension

[Palmer Dabbelt <palmer@rivosinc.com>]

On Tue, 28 Feb 2023 17:58:29 PST (-0800), nelson@rivosinc.com wrote:
> Hey Guys,
>
> I had heard that the final ratification of the zicond extension is
> coming soon, so it's time to see what we should do for those old
> vendor mnemonics and encodings, according to the current gnu policy.

Do you mean the Ventana cond ops?  IIUC those are in their chip, so we'd 
need to support them regardless of what happens at RVI.

> Not sure if maintaining compatibility of vendor stuff is worth it, but
> considering that obsolete vendor stuff should be replaced by the
> ratified zicond as soon as possible (or we should encourage everyone
> to use the RVI extension rather than the vendor one), maybe just
> removing them when the zicond committed is more intuitive.

Unless I'm missing something, neither the pre-freeze flavors of Zicond 
or the Ventana cond ops have landed upstream yet.  So we shouldn't need 
to remove anything (which would generally be a problem if it had been 
released).

>
> Thanks
> Nelson
>
> On Thu, Jan 26, 2023 at 9:03 AM Andrew Waterman <andrew@sifive.com> wrote:
>>
>> On Wed, Jan 25, 2023 at 4:27 PM Jeff Law via Binutils
>> <binutils@sourceware.org> wrote:
>> >
>> >
>> >
>> > On 1/20/23 17:29, Philipp Tomsich wrote:
>> > > *** Zicond is not FROZEN at this time. Do not merge until FROZEN. ***
>> > >
>> > > This implements the Zicond (conditional integer operations) extension,
>> > > as of version 1.0-draft-20230120.
>> > >
>> > > The Zicond extension acts as a building block for branchless sequences
>> > > including conditional-arithmetic, conditional-logic and
>> > > conditional-select/move.
>> > > The following instructions constitute Zicond:
>> > >    - czero.eqz rd, rs1, rs2  =>  rd = (rs2 == 0) ? 0 : rs1
>> > >    - czero.nez rd, rs1, rs2  =>  rd = (rs2 != 0) ? 0 : rs1
>> > >
>> > > See
>> > >    https://github.com/riscv/riscv-zicond/releases/download/v1.0-draft-20230120/riscv-zicond_1.0-draft-20230120.pdf
>> > > for the proposed specification and usage details.
>> > >
>> > > bfd/ChangeLog:
>> > >
>> > >       * elfxx-riscv.c (riscv_multi_subset_supports): Recognize
>> > >          INSN_CLASS_XVENTANACONDOPS.
>> > >       (riscv_multi_subset_supports_ext): Recognize
>> > >       INSN_CLASS_XVENTANACONDOPS,
>> > >
>> > > gas/ChangeLog:
>> > >
>> > >       * testsuite/gas/riscv/zicond.d: New test.
>> > >       * testsuite/gas/riscv/zicond.s: New test.
>> > >
>> > > include/ChangeLog:
>> > >
>> > >       * opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define.
>> > >       (MASK_CZERO_EQZ): Define.
>> > >       (MATCH_CZERO_NEZ): Define,
>> > >       (MASK_CZERO_NEZ): Define.
>> > >       (DECLARE_INSN): Add czero.eqz and czero.nez.
>> > >       * opcode/riscv.h (enum riscv_insn_class): Add
>> > >          INSN_CLASS_ZICOND
>> > >
>> > > opcodes/ChangeLog:
>> > >
>> > >       * riscv-opc.c: Add czero.eqz and czero.nez.
>> > Given this extension is derived from the Ventana condops extension, I
>> > may be somewhat biased.
>>
>> This is very much a standardized version of Ventana's custom condops
>> extension, modulo some details.
>>
>> > The mnemonics and encoding is obviously
>> > different, but the behavior is the same (perhaps differing in timing
>> > characteristics, but I think that's outside of what we care about here).
>> >
>> > I assume nobody cares about gdbsim, so nothing to do there.  With that
>> > assumption this is fine to go forward once the spec freezes.
>>
>> As for a status update, the RVI architecture-review committee recently
>> voted to approve the extension, so the official freeze should be
>> forthcoming.
>>
>> >
>> > jeff
>> >