[RFC PATCH v3 0/8] RISC-V: Add support for vector crypto extensions

[RFC PATCH v3 0/8] RISC-V: Add support for vector crypto extensions

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This series add support for the vector crypto extensions:
* Zvkb
* Zvkg
* Zvknh[a,b]
* Zvkned
* Zvkn
* Zvksed
* Zvksh
* Zvks

The implementation follows version v0.3.0 20230206 of the specification,
which can be found here:
  https://github.com/riscv/riscv-crypto/releases/tag/v20230206

Note, that this specification is not frozen yet, meaning that
incompatible changes are possible.
Therefore, this patchset is marked as RFC and should not be considered
for upstream inclusion.

All extensions come with (passing) tests.

A branch with all patches applied can be found in this GitHub repo:
  https://github.com/cmuellner/binutils-gdb/tree/riscv-zvk-v3

Changes in v3:
- Rebased
- Rename Zvkns -> Zvknsed
- Drop vghmac.vv from Zvkg
- Add vghsh.vv and vgmul.vv to Zvkg
- Introduce Zvkn and Zvks

Changes in v2:
- Rebased
- Adjusted code following 6eb099ae9324 (expr_end -> expr_parse_end)
- Rename Zvkn -> Zvkns

Christoph Müllner (8):
  RISC-V: Add Zvkb ISA extension support
  RISC-V: Add Zvkg ISA extension support
  RISC-V: Add Zvkned ISA extension support
  RISC-V: Add Zvknh[a,b] ISA extension support
  RISC-V: Add Zvkn ISA extension support
  RISC-V: Add Zvksed ISA extension support
  RISC-V: Add Zvksh ISA extension support
  RISC-V: Add Zvks ISA extension support

 bfd/elfxx-riscv.c                       |  45 +++++++++
 gas/config/tc-riscv.c                   |  13 +++
 gas/testsuite/gas/riscv/zvkb.d          |  36 ++++++++
 gas/testsuite/gas/riscv/zvkb.s          |  28 ++++++
 gas/testsuite/gas/riscv/zvkg.d          |  10 ++
 gas/testsuite/gas/riscv/zvkg.s          |   2 +
 gas/testsuite/gas/riscv/zvkn.d          |  10 ++
 gas/testsuite/gas/riscv/zvkn.s          |   2 +
 gas/testsuite/gas/riscv/zvkned.d        |  21 +++++
 gas/testsuite/gas/riscv/zvkned.s        |  13 +++
 gas/testsuite/gas/riscv/zvknha.d        |  12 +++
 gas/testsuite/gas/riscv/zvknha_zvknhb.s |   3 +
 gas/testsuite/gas/riscv/zvknhb.d        |  12 +++
 gas/testsuite/gas/riscv/zvks.d          |  10 ++
 gas/testsuite/gas/riscv/zvks.s          |   2 +
 gas/testsuite/gas/riscv/zvksed.d        |  12 +++
 gas/testsuite/gas/riscv/zvksed.s        |   4 +
 gas/testsuite/gas/riscv/zvksh.d         |  11 +++
 gas/testsuite/gas/riscv/zvksh.s         |   3 +
 include/opcode/riscv-opc.h              | 117 ++++++++++++++++++++++++
 include/opcode/riscv.h                  |  12 +++
 opcodes/riscv-dis.c                     |   4 +
 opcodes/riscv-opc.c                     |  47 ++++++++++
 23 files changed, 429 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvkb.d
 create mode 100644 gas/testsuite/gas/riscv/zvkb.s
 create mode 100644 gas/testsuite/gas/riscv/zvkg.d
 create mode 100644 gas/testsuite/gas/riscv/zvkg.s
 create mode 100644 gas/testsuite/gas/riscv/zvkn.d
 create mode 100644 gas/testsuite/gas/riscv/zvkn.s
 create mode 100644 gas/testsuite/gas/riscv/zvkned.d
 create mode 100644 gas/testsuite/gas/riscv/zvkned.s
 create mode 100644 gas/testsuite/gas/riscv/zvknha.d
 create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s
 create mode 100644 gas/testsuite/gas/riscv/zvknhb.d
 create mode 100644 gas/testsuite/gas/riscv/zvks.d
 create mode 100644 gas/testsuite/gas/riscv/zvks.s
 create mode 100644 gas/testsuite/gas/riscv/zvksed.d
 create mode 100644 gas/testsuite/gas/riscv/zvksed.s
 create mode 100644 gas/testsuite/gas/riscv/zvksh.d
 create mode 100644 gas/testsuite/gas/riscv/zvksh.s

-- 
2.39.1

[RFC PATCH v3 1/8] RISC-V: Add Zvkb ISA extension support

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This commit adds the Zvkb ISA extension instructions, which are part
of the vector crypto extensions.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
Changes in v2:
- Adjusted code following 6eb099ae9324 (expr_end -> expr_parse_end)

 bfd/elfxx-riscv.c              |  5 ++++
 gas/config/tc-riscv.c          | 13 ++++++++++
 gas/testsuite/gas/riscv/zvkb.d | 36 ++++++++++++++++++++++++++++
 gas/testsuite/gas/riscv/zvkb.s | 28 ++++++++++++++++++++++
 include/opcode/riscv-opc.h     | 44 ++++++++++++++++++++++++++++++++++
 include/opcode/riscv.h         |  5 ++++
 opcodes/riscv-dis.c            |  4 ++++
 opcodes/riscv-opc.c            | 16 +++++++++++++
 8 files changed, 151 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvkb.d
 create mode 100644 gas/testsuite/gas/riscv/zvkb.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 19391d94e30..c9952a51c3c 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1205,6 +1205,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64x",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zve64f",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2355,6 +2356,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zve64d")
 	      || riscv_subset_supports (rps, "zve64f")
 	      || riscv_subset_supports (rps, "zve32f"));
+    case INSN_CLASS_ZVKB:
+      return riscv_subset_supports (rps, "zvkb");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2513,6 +2516,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64x' or `zve32x");
     case INSN_CLASS_ZVEF:
       return _("v' or `zve64d' or `zve64f' or `zve32f");
+    case INSN_CLASS_ZVKB:
+      return _("zvkb");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 08b806d8c4e..08cecd4d78a 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1324,6 +1324,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	    case 'i':
 	    case 'j':
 	    case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
+	    case 'l': used_bits |= ENCODE_RVV_VI_UIMM6(-1U); break;
 	    case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
 	    case 'M': break; /* Macro operand, must be a mask register.  */
 	    case 'T': break; /* Macro operand, must be a vector register.  */
@@ -2987,6 +2988,18 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  asarg = expr_parse_end;
 		  continue;
 
+		case 'l': /* 6-bit vector arith unsigned immediate */
+		  my_getExpression (imm_expr, asarg);
+		  check_absolute_expr (ip, imm_expr, FALSE);
+		  if (imm_expr->X_add_number < 0
+		      || imm_expr->X_add_number >= 64)
+		    as_bad (_("bad value for vector immediate field, "
+			      "value must be 0...63"));
+		  ip->insn_opcode |= ENCODE_RVV_VI_UIMM6 (imm_expr->X_add_number);
+		  imm_expr->X_op = O_absent;
+		  asarg = expr_parse_end;
+		  continue;
+
 		case 'm': /* optional vector mask */
 		  if (*asarg == '\0')
 		    {
diff --git a/gas/testsuite/gas/riscv/zvkb.d b/gas/testsuite/gas/riscv/zvkb.d
new file mode 100644
index 00000000000..63aacba951c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkb.d
@@ -0,0 +1,36 @@
+#as: -march=rv64gc_zvkb
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+32862257[ 	]+vclmul.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+30862257[ 	]+vclmul.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3285e257[ 	]+vclmul.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3085e257[ 	]+vclmul.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+36862257[ 	]+vclmulh.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+34862257[ 	]+vclmulh.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3685e257[ 	]+vclmulh.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3485e257[ 	]+vclmulh.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+56860257[ 	]+vrol.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+54860257[ 	]+vrol.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5685c257[ 	]+vrol.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+5485c257[ 	]+vrol.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+52860257[ 	]+vror.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+50860257[ 	]+vror.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5285c257[ 	]+vror.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+5085c257[ 	]+vror.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+52803257[ 	]+vror.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+548fb257[ 	]+vror.vi[ 	]+v4,v8,63,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a842257[ 	]+vbrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48842257[ 	]+vbrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a84a257[ 	]+vrev8.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+4884a257[ 	]+vrev8.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+06860257[ 	]+vandn.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+04860257[ 	]+vandn.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0685c257[ 	]+vandn.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+0485c257[ 	]+vandn.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0687b257[ 	]+vandn.vi[ 	]+v4,v8,15
+[ 	]+[0-9a-f]+:[ 	]+04883257[ 	]+vandn.vi[ 	]+v4,v8,-16,v0.t
diff --git a/gas/testsuite/gas/riscv/zvkb.s b/gas/testsuite/gas/riscv/zvkb.s
new file mode 100644
index 00000000000..fd741505883
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkb.s
@@ -0,0 +1,28 @@
+	vclmul.vv v4, v8, v12
+	vclmul.vv v4, v8, v12, v0.t
+	vclmul.vx v4, v8, a1
+	vclmul.vx v4, v8, a1, v0.t
+	vclmulh.vv v4, v8, v12
+	vclmulh.vv v4, v8, v12, v0.t
+	vclmulh.vx v4, v8, a1
+	vclmulh.vx v4, v8, a1, v0.t
+	vrol.vv v4, v8, v12
+	vrol.vv v4, v8, v12, v0.t
+	vrol.vx v4, v8, a1
+	vrol.vx v4, v8, a1, v0.t
+	vror.vv v4, v8, v12
+	vror.vv v4, v8, v12, v0.t
+	vror.vx v4, v8, a1
+	vror.vx v4, v8, a1, v0.t
+	vror.vi v4, v8, 0
+	vror.vi v4, v8, 63, v0.t
+	vbrev8.v v4, v8
+	vbrev8.v v4, v8, v0.t
+	vrev8.v v4, v8
+	vrev8.v v4, v8, v0.t
+	vandn.vv v4, v8, v12
+	vandn.vv v4, v8, v12, v0.t
+	vandn.vx v4, v8, a1
+	vandn.vx v4, v8, a1, v0.t
+	vandn.vi v4, v8, 15
+	vandn.vi v4, v8, -16, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 85d35c1efc9..bdcb3e442f8 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2055,6 +2055,35 @@
 #define MASK_VDOTUVV  0xfc00707f
 #define MATCH_VFDOTVV  0xe4001057
 #define MASK_VFDOTVV  0xfc00707f
+/* Zvkb instructions.  */
+#define MATCH_VCLMULVV 0x30002057
+#define MASK_VCLMULVV 0xfc00707f
+#define MATCH_VCLMULVX 0x30006057
+#define MASK_VCLMULVX 0xfc00707f
+#define MATCH_VCLMULHVV 0x34002057
+#define MASK_VCLMULHVV 0xfc00707f
+#define MATCH_VCLMULHVX 0x34006057
+#define MASK_VCLMULHVX 0xfc00707f
+#define MATCH_VROLVV 0x54000057
+#define MASK_VROLVV 0xfc00707f
+#define MATCH_VROLVX 0x54004057
+#define MASK_VROLVX 0xfc00707f
+#define MATCH_VRORVV 0x50000057
+#define MASK_VRORVV 0xfc00707f
+#define MATCH_VRORVX 0x50004057
+#define MASK_VRORVX 0xfc00707f
+#define MATCH_VRORVI 0x50003057
+#define MASK_VRORVI 0xf800707f
+#define MATCH_VBREV8V 0x48042057
+#define MASK_VBREV8V 0xfc0ff07f
+#define MATCH_VREV8V 0x4804a057
+#define MASK_VREV8V 0xfc0ff07f
+#define MATCH_VANDNVV 0x04000057
+#define MASK_VANDNVV 0xfc00707f
+#define MATCH_VANDNVX 0x04004057
+#define MASK_VANDNVX 0xfc00707f
+#define MATCH_VANDNVI 0x04003057
+#define MASK_VANDNVI 0xfc00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3118,6 +3147,21 @@ DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, MASK_CBO_ZERO);
 /* Zawrs instructions.  */
 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
+/* Zvkb instructions.  */
+DECLARE_INSN(vclmulvv, MATCH_VCLMULVV, MASK_VCLMULVV)
+DECLARE_INSN(vclmulvx, MATCH_VCLMULVX, MASK_VCLMULVX)
+DECLARE_INSN(vclmulhvv, MATCH_VCLMULHVV, MASK_VCLMULHVV)
+DECLARE_INSN(vclmulhvx, MATCH_VCLMULHVX, MASK_VCLMULHVX)
+DECLARE_INSN(vrolvv, MATCH_VROLVV, MASK_VROLVV)
+DECLARE_INSN(vrolvx, MATCH_VROLVX, MASK_VROLVX)
+DECLARE_INSN(vrorvv, MATCH_VRORVV, MASK_VRORVV)
+DECLARE_INSN(vrorvx, MATCH_VRORVX, MASK_VRORVX)
+DECLARE_INSN(vrorvi, MATCH_VRORVI, MASK_VRORVI)
+DECLARE_INSN(vbrev8v, MATCH_VBREV8V, MASK_VBREV8V)
+DECLARE_INSN(vrev8v, MATCH_VREV8V, MASK_VREV8V)
+DECLARE_INSN(vandnvv, MATCH_VANDNVV, MASK_VANDNVV)
+DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX)
+DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b4ae55249bb..cc3950f56b8 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -100,6 +100,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
 #define EXTRACT_RVV_VI_UIMM(x) \
   (RV_X(x, 15, 5))
+#define EXTRACT_RVV_VI_UIMM6(x) \
+  (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))
 #define EXTRACT_RVV_OFFSET(x) \
   (RV_X(x, 29, 3))
 #define EXTRACT_RVV_VB_IMM(x) \
@@ -151,6 +153,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
   (RV_X(x, 0, 10) << 20)
 #define ENCODE_RVV_VC_IMM(x) \
   (RV_X(x, 0, 11) << 20)
+#define ENCODE_RVV_VI_UIMM6(x) \
+  (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
 
 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
@@ -405,6 +409,7 @@ enum riscv_insn_class
   INSN_CLASS_ZKND_OR_ZKNE,
   INSN_CLASS_V,
   INSN_CLASS_ZVEF,
+  INSN_CLASS_ZVKB,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 7baba054daa..7dfc987717c 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -397,6 +397,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	      print (info->stream, dis_style_immediate, "%d",
 		     (int)EXTRACT_RVV_OFFSET (l));
 	      break;
+	    case 'l':
+	      print (info->stream, dis_style_immediate, "%d",
+		     (int)EXTRACT_RVV_VI_UIMM6 (l));
+	      break;
 	    case 'm':
 	      if (!EXTRACT_OPERAND (VMASK, l))
 		{
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index f67375f10a9..4d0c5a4ec37 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1815,6 +1815,22 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vmv4r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0},
 {"vmv8r.v",    0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0},
 
+/* Zvkb instructions.  */
+{"vclmul.vv",  0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VCLMULVV, MASK_VCLMULVV, match_opcode, 0},
+{"vclmul.vx",  0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VCLMULVX, MASK_VCLMULVX, match_opcode, 0},
+{"vclmulh.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VCLMULHVV, MASK_VCLMULHVV, match_opcode, 0},
+{"vclmulh.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VCLMULHVX, MASK_VCLMULHVX, match_opcode, 0},
+{"vrol.vv",    0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VROLVV, MASK_VROLVV, match_opcode, 0},
+{"vrol.vx",    0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VROLVX, MASK_VROLVX, match_opcode, 0},
+{"vror.vv",    0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VRORVV, MASK_VRORVV, match_opcode, 0},
+{"vror.vx",    0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VRORVX, MASK_VRORVX, match_opcode, 0},
+{"vror.vi",    0, INSN_CLASS_ZVKB, "Vd,Vt,VlVm", MATCH_VRORVI, MASK_VRORVI, match_opcode, 0},
+{"vbrev8.v",   0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VBREV8V, MASK_VBREV8V, match_opcode, 0},
+{"vrev8.v",    0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VREV8V, MASK_VREV8V, match_opcode, 0},
+{"vandn.vv",   0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDNVV, MASK_VANDNVV, match_opcode, 0},
+{"vandn.vx",   0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDNVX, MASK_VANDNVX, match_opcode, 0},
+{"vandn.vi",   0, INSN_CLASS_ZVKB, "Vd,Vt,ViVm", MATCH_VANDNVI, MASK_VANDNVI, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.39.1

[RFC PATCH v3 2/8] RISC-V: Add Zvkg ISA extension support

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This commit adds the Zvkg ISA extension instruction, which is part
of the vector crypto extensions.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
Changes in v3:
- Updated to spec v0.3.0 (2023-02-06)
- Removed vghmac.vv
- Added vghsh.vv and vgmul.vv

 bfd/elfxx-riscv.c              |  5 +++++
 gas/testsuite/gas/riscv/zvkg.d | 10 ++++++++++
 gas/testsuite/gas/riscv/zvkg.s |  2 ++
 include/opcode/riscv-opc.h     |  8 ++++++++
 include/opcode/riscv.h         |  1 +
 opcodes/riscv-opc.c            |  4 ++++
 6 files changed, 30 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvkg.d
 create mode 100644 gas/testsuite/gas/riscv/zvkg.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c9952a51c3c..9e0dee9cc72 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1206,6 +1206,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64f",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2358,6 +2359,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zve32f"));
     case INSN_CLASS_ZVKB:
       return riscv_subset_supports (rps, "zvkb");
+    case INSN_CLASS_ZVKG:
+      return riscv_subset_supports (rps, "zvkg");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2518,6 +2521,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64d' or `zve64f' or `zve32f");
     case INSN_CLASS_ZVKB:
       return _("zvkb");
+    case INSN_CLASS_ZVKG:
+      return _("zvkg");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkg.d b/gas/testsuite/gas/riscv/zvkg.d
new file mode 100644
index 00000000000..7f898d377b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.d
@@ -0,0 +1,10 @@
+#as: -march=rv64gc_zvkg
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+b2862277[ 	]+vghsh.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+a2c8a277[ 	]+vgmul.vv[ 	]+v4,v12
diff --git a/gas/testsuite/gas/riscv/zvkg.s b/gas/testsuite/gas/riscv/zvkg.s
new file mode 100644
index 00000000000..b802d6add39
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.s
@@ -0,0 +1,2 @@
+	vghsh.vv v4, v8, v12
+	vgmul.vv v4, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index bdcb3e442f8..03eda5a9e49 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2084,6 +2084,11 @@
 #define MASK_VANDNVX 0xfc00707f
 #define MATCH_VANDNVI 0x04003057
 #define MASK_VANDNVI 0xfc00707f
+/* Zvkg instructions.  */
+#define MATCH_VGHSHVV 0xb2002077
+#define MASK_VGHSHVV 0xfe00707f
+#define MATCH_VGMULVV 0xa208a077
+#define MASK_VGMULVV 0xfe0ff07f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3162,6 +3167,9 @@ DECLARE_INSN(vrev8v, MATCH_VREV8V, MASK_VREV8V)
 DECLARE_INSN(vandnvv, MATCH_VANDNVV, MASK_VANDNVV)
 DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX)
 DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
+/* Zvkg instructions.  */
+DECLARE_INSN(vghshvv, MATCH_VGHASHVV, MASK_VGHASHVV)
+DECLARE_INSN(vgmulvv, MATCH_VGMULTVV, MASK_VGMULTVV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index cc3950f56b8..9e883f030d6 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -410,6 +410,7 @@ enum riscv_insn_class
   INSN_CLASS_V,
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVKB,
+  INSN_CLASS_ZVKG,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 4d0c5a4ec37..0bb0bb4cce7 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1831,6 +1831,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vandn.vx",   0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDNVX, MASK_VANDNVX, match_opcode, 0},
 {"vandn.vi",   0, INSN_CLASS_ZVKB, "Vd,Vt,ViVm", MATCH_VANDNVI, MASK_VANDNVI, match_opcode, 0},
 
+/* Zvkg instructions.  */
+{"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSHVV, MASK_VGHSHVV, match_opcode, 0},
+{"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMULVV, MASK_VGMULVV, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.39.1

[RFC PATCH v3 3/8] RISC-V: Add Zvkned ISA extension support

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This commit adds the Zvkned ISA extension instructions, which are
part of the vector crypto extensions.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
Changes in v3:
- Rename Zvkns -> Zvkned

Changes in v2:
- Rename Zvkn -> Zvkns

 bfd/elfxx-riscv.c                |  5 +++++
 gas/testsuite/gas/riscv/zvkned.d | 21 +++++++++++++++++++
 gas/testsuite/gas/riscv/zvkned.s | 13 ++++++++++++
 include/opcode/riscv-opc.h       | 35 ++++++++++++++++++++++++++++++++
 include/opcode/riscv.h           |  1 +
 opcodes/riscv-opc.c              | 13 ++++++++++++
 6 files changed, 88 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvkned.d
 create mode 100644 gas/testsuite/gas/riscv/zvkned.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 9e0dee9cc72..51ddaace420 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1207,6 +1207,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2361,6 +2362,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvkb");
     case INSN_CLASS_ZVKG:
       return riscv_subset_supports (rps, "zvkg");
+    case INSN_CLASS_ZVKNED:
+      return riscv_subset_supports (rps, "zvkned");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2523,6 +2526,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvkb");
     case INSN_CLASS_ZVKG:
       return _("zvkg");
+    case INSN_CLASS_ZVKNED:
+      return _("zvkned");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkned.d b/gas/testsuite/gas/riscv/zvkned.d
new file mode 100644
index 00000000000..0b09da9dbc2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkned.d
@@ -0,0 +1,21 @@
+#as: -march=rv64gc_zvkned
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+a280a277[ 	]+vaesdf.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a680a277[ 	]+vaesdf.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a2802277[ 	]+vaesdm.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a6802277[ 	]+vaesdm.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a281a277[ 	]+vaesef.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a681a277[ 	]+vaesef.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a2812277[ 	]+vaesem.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a6812277[ 	]+vaesem.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a812277[ 	]+vaeskf1.vi[ 	]+v4,v8,2
+[ 	]+[0-9a-f]+:[ 	]+8a872277[ 	]+vaeskf1.vi[ 	]+v4,v8,14
+[ 	]+[0-9a-f]+:[ 	]+aa812277[ 	]+vaeskf2.vi[ 	]+v4,v8,2
+[ 	]+[0-9a-f]+:[ 	]+aa872277[ 	]+vaeskf2.vi[ 	]+v4,v8,14
+[ 	]+[0-9a-f]+:[ 	]+a683a277[ 	]+vaesz.vs[ 	]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvkned.s b/gas/testsuite/gas/riscv/zvkned.s
new file mode 100644
index 00000000000..f0f3811eaec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkned.s
@@ -0,0 +1,13 @@
+	vaesdf.vv v4, v8
+	vaesdf.vs v4, v8
+	vaesdm.vv v4, v8
+	vaesdm.vs v4, v8
+	vaesef.vv v4, v8
+	vaesef.vs v4, v8
+	vaesem.vv v4, v8
+	vaesem.vs v4, v8
+	vaeskf1.vi v4, v8, 2
+	vaeskf1.vi v4, v8, 14
+	vaeskf2.vi v4, v8, 2
+	vaeskf2.vi v4, v8, 14
+	vaesz.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 03eda5a9e49..5f593222ea6 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2089,6 +2089,29 @@
 #define MASK_VGHSHVV 0xfe00707f
 #define MATCH_VGMULVV 0xa208a077
 #define MASK_VGMULVV 0xfe0ff07f
+/* Zvkned instructions.  */
+#define MATCH_VAESDFVV 0xa200a077
+#define MASK_VAESDFVV 0xfe0ff07f
+#define MATCH_VAESDFVS 0xa600a077
+#define MASK_VAESDFVS 0xfe0ff07f
+#define MATCH_VAESDMVV 0xa2002077
+#define MASK_VAESDMVV 0xfe0ff07f
+#define MATCH_VAESDMVS 0xa6002077
+#define MASK_VAESDMVS 0xfe0ff07f
+#define MATCH_VAESEFVV 0xa201a077
+#define MASK_VAESEFVV 0xfe0ff07f
+#define MATCH_VAESEFVS 0xa601a077
+#define MASK_VAESEFVS 0xfe0ff07f
+#define MATCH_VAESEMVV 0xa2012077
+#define MASK_VAESEMVV 0xfe0ff07f
+#define MATCH_VAESEMVS 0xa6012077
+#define MASK_VAESEMVS 0xfe0ff07f
+#define MATCH_VAESKF1VI 0x8a002077
+#define MASK_VAESKF1VI 0xfe00707f
+#define MATCH_VAESKF2VI 0xaa002077
+#define MASK_VAESKF2VI 0xfe00707f
+#define MATCH_VAESZVS 0xa603a077
+#define MASK_VAESZVS 0xfe0ff07f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3170,6 +3193,18 @@ DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
 /* Zvkg instructions.  */
 DECLARE_INSN(vghshvv, MATCH_VGHASHVV, MASK_VGHASHVV)
 DECLARE_INSN(vgmulvv, MATCH_VGMULTVV, MASK_VGMULTVV)
+/* Zvkned instructions.  */
+DECLARE_INSN(vaesdfvv, MATCH_VAESDFVV, MASK_VAESDFVV)
+DECLARE_INSN(vaesdfvs, MATCH_VAESDFVS, MASK_VAESDFVS)
+DECLARE_INSN(vaesdmvv, MATCH_VAESDMVV, MASK_VAESDMVV)
+DECLARE_INSN(vaesdmvs, MATCH_VAESDMVS, MASK_VAESDMVS)
+DECLARE_INSN(vaesefvv, MATCH_VAESEFVV, MASK_VAESEFVV)
+DECLARE_INSN(vaesefvs, MATCH_VAESEFVS, MASK_VAESEFVS)
+DECLARE_INSN(vaesemvv, MATCH_VAESEMVV, MASK_VAESEMVV)
+DECLARE_INSN(vaesemvs, MATCH_VAESEMVS, MASK_VAESEMVS)
+DECLARE_INSN(vaeskf1vi, MATCH_VAESKF1VI, MASK_VAESKF1VI)
+DECLARE_INSN(vaeskf2vi, MATCH_VAESKF2VI, MASK_VAESKF2VI)
+DECLARE_INSN(vaeszvs, MATCH_VAESZVS, MASK_VAESZVS)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 9e883f030d6..4b7e72150e5 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -411,6 +411,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVKB,
   INSN_CLASS_ZVKG,
+  INSN_CLASS_ZVKNED,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0bb0bb4cce7..3465670d951 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1835,6 +1835,19 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSHVV, MASK_VGHSHVV, match_opcode, 0},
 {"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMULVV, MASK_VGMULVV, match_opcode, 0},
 
+/* Zvkned instructions.  */
+{"vaesdf.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDFVV, MASK_VAESDFVV, match_opcode, 0},
+{"vaesdf.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDFVS, MASK_VAESDFVV, match_opcode, 0},
+{"vaesdm.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDMVV, MASK_VAESDMVV, match_opcode, 0},
+{"vaesdm.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDMVS, MASK_VAESDMVV, match_opcode, 0},
+{"vaesef.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEFVV, MASK_VAESEFVV, match_opcode, 0},
+{"vaesef.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEFVS, MASK_VAESEFVV, match_opcode, 0},
+{"vaesem.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEMVV, MASK_VAESEMVV, match_opcode, 0},
+{"vaesem.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEMVS, MASK_VAESEMVV, match_opcode, 0},
+{"vaeskf1.vi",   0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF1VI, MASK_VAESKF1VI, match_opcode, 0},
+{"vaeskf2.vi",   0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2VI, MASK_VAESKF2VI, match_opcode, 0},
+{"vaesz.vs",     0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZVS, MASK_VAESZVS, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.39.1

[RFC PATCH v3 4/8] RISC-V: Add Zvknh[a,b] ISA extension support

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This commit adds the Zvknh[a,b] ISA extension instructions, which are part
of the vector crypto extensions.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
Changes in v2:
- Rename Zvkh[a,b] -> Zvknh[a,b]

 bfd/elfxx-riscv.c                       | 13 +++++++++++++
 gas/testsuite/gas/riscv/zvknha.d        | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvknha_zvknhb.s |  3 +++
 gas/testsuite/gas/riscv/zvknhb.d        | 12 ++++++++++++
 include/opcode/riscv-opc.h              | 11 +++++++++++
 include/opcode/riscv.h                  |  3 +++
 opcodes/riscv-opc.c                     |  5 +++++
 7 files changed, 59 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvknha.d
 create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s
 create mode 100644 gas/testsuite/gas/riscv/zvknhb.d

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 51ddaace420..c0a71c771fc 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1208,6 +1208,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2364,6 +2366,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvkg");
     case INSN_CLASS_ZVKNED:
       return riscv_subset_supports (rps, "zvkned");
+    case INSN_CLASS_ZVKNHA:
+      return riscv_subset_supports (rps, "zvknha");
+    case INSN_CLASS_ZVKNHB:
+      return riscv_subset_supports (rps, "zvknhb");
+    case INSN_CLASS_ZVKNHA_OR_ZVKNHB:
+      return (riscv_subset_supports (rps, "zvknha")
+	      || riscv_subset_supports (rps, "zvknhb"));
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2528,6 +2537,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvkg");
     case INSN_CLASS_ZVKNED:
       return _("zvkned");
+    case INSN_CLASS_ZVKNHA:
+      return _("zvknha");
+    case INSN_CLASS_ZVKNHB:
+      return _("zvknhb");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvknha.d b/gas/testsuite/gas/riscv/zvknha.d
new file mode 100644
index 00000000000..36d660f634f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknha.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvknha
+#source: zvknha_zvknhb.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ba862277[ 	]+vsha2ch.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+be862277[ 	]+vsha2cl.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+b6862277[ 	]+vsha2ms.vv[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvknha_zvknhb.s b/gas/testsuite/gas/riscv/zvknha_zvknhb.s
new file mode 100644
index 00000000000..d20e6310531
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknha_zvknhb.s
@@ -0,0 +1,3 @@
+	vsha2ch.vv v4, v8, v12
+	vsha2cl.vv v4, v8, v12
+	vsha2ms.vv v4, v8, v12
diff --git a/gas/testsuite/gas/riscv/zvknhb.d b/gas/testsuite/gas/riscv/zvknhb.d
new file mode 100644
index 00000000000..ab0f035889e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknhb.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvknhb
+#source: zvknha_zvknhb.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ba862277[ 	]+vsha2ch.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+be862277[ 	]+vsha2cl.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+b6862277[ 	]+vsha2ms.vv[ 	]+v4,v8,v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 5f593222ea6..e82e53be687 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2112,6 +2112,13 @@
 #define MASK_VAESKF2VI 0xfe00707f
 #define MATCH_VAESZVS 0xa603a077
 #define MASK_VAESZVS 0xfe0ff07f
+/* Zvknh[a,b] instructions.  */
+#define MATCH_VSHA2CHVV 0xba002077
+#define MASK_VSHA2CHVV 0xfe00707f
+#define MATCH_VSHA2CLVV 0xbe002077
+#define MASK_VSHA2CLVV 0xfe00707f
+#define MATCH_VSHA2MSVV 0xb6002077
+#define MASK_VSHA2MSVV 0xfe00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3205,6 +3212,10 @@ DECLARE_INSN(vaesemvs, MATCH_VAESEMVS, MASK_VAESEMVS)
 DECLARE_INSN(vaeskf1vi, MATCH_VAESKF1VI, MASK_VAESKF1VI)
 DECLARE_INSN(vaeskf2vi, MATCH_VAESKF2VI, MASK_VAESKF2VI)
 DECLARE_INSN(vaeszvs, MATCH_VAESZVS, MASK_VAESZVS)
+/* Zvknh[a,b] instructions.  */
+DECLARE_INSN(vsha2chvv, MATCH_VSHA2CHVV, MASK_VSHA2CHVV)
+DECLARE_INSN(vsha2clvv, MATCH_VSHA2CLVV, MASK_VSHA2CLVV)
+DECLARE_INSN(vsha2msvv, MATCH_VSHA2MSVV, MASK_VSHA2MSVV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 4b7e72150e5..17f28355360 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -412,6 +412,9 @@ enum riscv_insn_class
   INSN_CLASS_ZVKB,
   INSN_CLASS_ZVKG,
   INSN_CLASS_ZVKNED,
+  INSN_CLASS_ZVKNHA,
+  INSN_CLASS_ZVKNHB,
+  INSN_CLASS_ZVKNHA_OR_ZVKNHB,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 3465670d951..a57b084b20e 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1848,6 +1848,11 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vaeskf2.vi",   0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2VI, MASK_VAESKF2VI, match_opcode, 0},
 {"vaesz.vs",     0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZVS, MASK_VAESZVS, match_opcode, 0},
 
+/* Zvknh[a,b] instructions.  */
+{"vsha2ch.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CHVV, MASK_VSHA2CHVV, match_opcode, 0},
+{"vsha2cl.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CLVV, MASK_VSHA2CLVV, match_opcode, 0},
+{"vsha2ms.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MSVV, MASK_VSHA2MSVV, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.39.1

[RFC PATCH v3 5/8] RISC-V: Add Zvkn ISA extension support

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This commit adds support for the Zvkn ISA extension,
which is part of the vector crypto extensions.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 bfd/elfxx-riscv.c              |  4 ++++
 gas/testsuite/gas/riscv/zvkn.d | 10 ++++++++++
 gas/testsuite/gas/riscv/zvkn.s |  2 ++
 3 files changed, 16 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvkn.d
 create mode 100644 gas/testsuite/gas/riscv/zvkn.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c0a71c771fc..88846bcf807 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1101,6 +1101,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zks", "zbkx",	check_implicit_always},
   {"zks", "zksed",	check_implicit_always},
   {"zks", "zksh",	check_implicit_always},
+  {"zvkn", "zvkned",	check_implicit_always},
+  {"zvkn", "zvknha",	check_implicit_always},
+  {"zvkn", "zvknhb",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
@@ -1207,6 +1210,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkn",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
diff --git a/gas/testsuite/gas/riscv/zvkn.d b/gas/testsuite/gas/riscv/zvkn.d
new file mode 100644
index 00000000000..d6be3bd671b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkn.d
@@ -0,0 +1,10 @@
+#as: -march=rv64gc_zvkn
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+a280a277[ 	]+vaesdf.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+ba862277[ 	]+vsha2ch.vv[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvkn.s b/gas/testsuite/gas/riscv/zvkn.s
new file mode 100644
index 00000000000..f7516e075e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkn.s
@@ -0,0 +1,2 @@
+	vaesdf.vv v4, v8
+	vsha2ch.vv v4, v8, v12
-- 
2.39.1

[RFC PATCH v3 6/8] RISC-V: Add Zvksed ISA extension support

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This commit adds the Zvksed ISA extension instructions, which are
part of the vector crypto extensions.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 bfd/elfxx-riscv.c                |  5 +++++
 gas/testsuite/gas/riscv/zvksed.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvksed.s |  4 ++++
 include/opcode/riscv-opc.h       | 11 +++++++++++
 include/opcode/riscv.h           |  1 +
 opcodes/riscv-opc.c              |  5 +++++
 6 files changed, 38 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvksed.d
 create mode 100644 gas/testsuite/gas/riscv/zvksed.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 88846bcf807..2163117d451 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1214,6 +1214,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvksed",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2377,6 +2378,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZVKNHA_OR_ZVKNHB:
       return (riscv_subset_supports (rps, "zvknha")
 	      || riscv_subset_supports (rps, "zvknhb"));
+    case INSN_CLASS_ZVKSED:
+      return riscv_subset_supports (rps, "zvksed");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2545,6 +2548,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvknha");
     case INSN_CLASS_ZVKNHB:
       return _("zvknhb");
+    case INSN_CLASS_ZVKSED:
+      return _("zvksed");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksed.d b/gas/testsuite/gas/riscv/zvksed.d
new file mode 100644
index 00000000000..48b4aafdbb1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.d
@@ -0,0 +1,12 @@
+#as: -march=rv64gc_zvksed
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+86802277[ 	]+vsm4k.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+8683a277[ 	]+vsm4k.vi[ 	]+v4,v8,7
+[ 	]+[0-9a-f]+:[ 	]+a2882277[ 	]+vsm4r.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a6882277[ 	]+vsm4r.vs[ 	]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvksed.s b/gas/testsuite/gas/riscv/zvksed.s
new file mode 100644
index 00000000000..754b4646adf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.s
@@ -0,0 +1,4 @@
+	vsm4k.vi v4, v8, 0
+	vsm4k.vi v4, v8, 7
+	vsm4r.vv v4, v8
+	vsm4r.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index e82e53be687..ae9a89b0bd2 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2119,6 +2119,13 @@
 #define MASK_VSHA2CLVV 0xfe00707f
 #define MATCH_VSHA2MSVV 0xb6002077
 #define MASK_VSHA2MSVV 0xfe00707f
+/* Zvksed instructions.  */
+#define MATCH_VSM4KVI 0x86002077
+#define MASK_VSM4KVI 0xfe00707f
+#define MATCH_VSM4RVV 0xa2082077
+#define MASK_VSM4RVV 0xfe0ff07f
+#define MATCH_VSM4RVS 0xa6082077
+#define MASK_VSM4RVS 0xfe0ff07f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3216,6 +3223,10 @@ DECLARE_INSN(vaeszvs, MATCH_VAESZVS, MASK_VAESZVS)
 DECLARE_INSN(vsha2chvv, MATCH_VSHA2CHVV, MASK_VSHA2CHVV)
 DECLARE_INSN(vsha2clvv, MATCH_VSHA2CLVV, MASK_VSHA2CLVV)
 DECLARE_INSN(vsha2msvv, MATCH_VSHA2MSVV, MASK_VSHA2MSVV)
+/* Zvksed instructions.  */
+DECLARE_INSN(vsm4kvi, MATCH_VSM4KVI, MASK_VSM4KVI)
+DECLARE_INSN(vsm4rvv, MATCH_VSM4RVV, MASK_VSM4RVV)
+DECLARE_INSN(vsm4rvs, MATCH_VSM4RVS, MASK_VSM4RVS)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 17f28355360..1910ea7529c 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -415,6 +415,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVKNHA,
   INSN_CLASS_ZVKNHB,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
+  INSN_CLASS_ZVKSED,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index a57b084b20e..98d17ef8b03 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1853,6 +1853,11 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vsha2cl.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CLVV, MASK_VSHA2CLVV, match_opcode, 0},
 {"vsha2ms.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MSVV, MASK_VSHA2MSVV, match_opcode, 0},
 
+/* Zvksed instructions.  */
+{"vsm4k.vi",     0, INSN_CLASS_ZVKSED, "Vd,Vt,Vj", MATCH_VSM4KVI, MASK_VSM4KVI, match_opcode, 0},
+{"vsm4r.vv",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVV, MASK_VSM4RVV, match_opcode, 0},
+{"vsm4r.vs",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVS, MASK_VSM4RVS, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.39.1

[RFC PATCH v3 7/8] RISC-V: Add Zvksh ISA extension support

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This commit adds the Zvksh ISA extension instructions, which are
part of the vector crypto extensions.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 bfd/elfxx-riscv.c               |  5 +++++
 gas/testsuite/gas/riscv/zvksh.d | 11 +++++++++++
 gas/testsuite/gas/riscv/zvksh.s |  3 +++
 include/opcode/riscv-opc.h      |  8 ++++++++
 include/opcode/riscv.h          |  1 +
 opcodes/riscv-opc.c             |  4 ++++
 6 files changed, 32 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvksh.d
 create mode 100644 gas/testsuite/gas/riscv/zvksh.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 2163117d451..f333c26189a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1215,6 +1215,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksed",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvksh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2380,6 +2381,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zvknhb"));
     case INSN_CLASS_ZVKSED:
       return riscv_subset_supports (rps, "zvksed");
+    case INSN_CLASS_ZVKSH:
+      return riscv_subset_supports (rps, "zvksh");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2550,6 +2553,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvknhb");
     case INSN_CLASS_ZVKSED:
       return _("zvksed");
+    case INSN_CLASS_ZVKSH:
+      return _("zvksh");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksh.d b/gas/testsuite/gas/riscv/zvksh.d
new file mode 100644
index 00000000000..b24d126ed7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.d
@@ -0,0 +1,11 @@
+#as: -march=rv64gc_zvksh
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ae802277[ 	]+vsm3c.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+ae8fa277[ 	]+vsm3c.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+82862277[ 	]+vsm3me.vv[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvksh.s b/gas/testsuite/gas/riscv/zvksh.s
new file mode 100644
index 00000000000..bde705c5e33
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.s
@@ -0,0 +1,3 @@
+	vsm3c.vi v4, v8, 0
+	vsm3c.vi v4, v8, 31
+	vsm3me.vv v4, v8, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ae9a89b0bd2..c534fd095e0 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2126,6 +2126,11 @@
 #define MASK_VSM4RVV 0xfe0ff07f
 #define MATCH_VSM4RVS 0xa6082077
 #define MASK_VSM4RVS 0xfe0ff07f
+/* Zvksh instructions.  */
+#define MATCH_VSM3CVI 0xae002077
+#define MASK_VSM3CVI 0xfe00707f
+#define MATCH_VSM3MEVV 0x82002077
+#define MASK_VSM3MEVV 0xfe00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3227,6 +3232,9 @@ DECLARE_INSN(vsha2msvv, MATCH_VSHA2MSVV, MASK_VSHA2MSVV)
 DECLARE_INSN(vsm4kvi, MATCH_VSM4KVI, MASK_VSM4KVI)
 DECLARE_INSN(vsm4rvv, MATCH_VSM4RVV, MASK_VSM4RVV)
 DECLARE_INSN(vsm4rvs, MATCH_VSM4RVS, MASK_VSM4RVS)
+/* Zvksh instructions.  */
+DECLARE_INSN(vsm3cvi, MATCH_VSM3CVI, MASK_VSM3CVI)
+DECLARE_INSN(vsm3mevv, MATCH_VSM3MEVV, MASK_VSM3MEVV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 1910ea7529c..5399a0bb991 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -416,6 +416,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVKNHB,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
   INSN_CLASS_ZVKSED,
+  INSN_CLASS_ZVKSH,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 98d17ef8b03..798ce56abeb 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1858,6 +1858,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vsm4r.vv",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVV, MASK_VSM4RVV, match_opcode, 0},
 {"vsm4r.vs",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVS, MASK_VSM4RVS, match_opcode, 0},
 
+/* Zvksh instructions.  */
+{"vsm3c.vi",     0, INSN_CLASS_ZVKSH, "Vd,Vt,Vj", MATCH_VSM3CVI, MASK_VSM3CVI, match_opcode, 0},
+{"vsm3me.vv",    0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3MEVV, MASK_VSM3MEVV, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
-- 
2.39.1

[RFC PATCH v3 8/8] RISC-V: Add Zvks ISA extension support

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This commit adds support for the Zvks ISA extension,
which is part of the vector crypto extensions.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 bfd/elfxx-riscv.c              |  3 +++
 gas/testsuite/gas/riscv/zvks.d | 10 ++++++++++
 gas/testsuite/gas/riscv/zvks.s |  2 ++
 3 files changed, 15 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvks.d
 create mode 100644 gas/testsuite/gas/riscv/zvks.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index f333c26189a..09ce4b15a3e 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1104,6 +1104,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvkn", "zvkned",	check_implicit_always},
   {"zvkn", "zvknha",	check_implicit_always},
   {"zvkn", "zvknhb",	check_implicit_always},
+  {"zvks", "zvksed",	check_implicit_always},
+  {"zvks", "zvksh",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
@@ -1216,6 +1218,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksed",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvks",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
diff --git a/gas/testsuite/gas/riscv/zvks.d b/gas/testsuite/gas/riscv/zvks.d
new file mode 100644
index 00000000000..013e9880b06
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvks.d
@@ -0,0 +1,10 @@
+#as: -march=rv64gc_zvks
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+86802277[ 	]+vsm4k.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+ae802277[ 	]+vsm3c.vi[ 	]+v4,v8,0
diff --git a/gas/testsuite/gas/riscv/zvks.s b/gas/testsuite/gas/riscv/zvks.s
new file mode 100644
index 00000000000..454e701d9d6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvks.s
@@ -0,0 +1,2 @@
+	vsm4k.vi v4, v8, 0
+	vsm3c.vi v4, v8, 0
-- 
2.39.1