[PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks

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* [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks
@ 2023-02-15 18:02 WANG Xuerui
  2023-02-15 18:02 ` [PATCH v4 1/6] LoongArch: support disassembling certain pseudo-instructions WANG Xuerui
                   ` (6 more replies)
  0 siblings, 7 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-02-15 18:02 UTC (permalink / raw)
  To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Xi Ruoyao, WANG Xuerui

From: WANG Xuerui <git@xen0n.name>

Hi,

This series implements colored output for LoongArch disassembly, and
some minor tweaks to the output so there is less clutter.

Changes from v3:

- Fixed ld test cases (make check-gas and make check-ld both pass on
  x86_64 and loongarch64)
- Branch target address is now correctly printed in comment style, plus
  code simplification as suggested

Changes from v2:

- Fixed test cases
- Added the fixed "LoongArch: support disassembling certain pseudo-
  instructions" patch into this series
- Fixed ".insn" in the last patch to say ".word" instead (MIPS muscle
  memory strikes back hard)
- Fixed some commit messages
- Added mengqinggang to Cc list

WANG Xuerui (6):
  LoongArch: support disassembling certain pseudo-instructions
  opcodes/loongarch: remove unused code
  opcodes/loongarch: implement style support in the disassembler
  opcodes/loongarch: style disassembled address offsets as such
  opcodes/loongarch: do not print hex notation for signed immediates
  opcodes/loongarch: print unrecognized insn words with the .word
    directive

 gas/config/tc-loongarch.c                     |   3 +-
 gas/testsuite/gas/loongarch/imm_ins.d         |  84 ++++++-------
 gas/testsuite/gas/loongarch/imm_ins_32.d      |  54 ++++-----
 gas/testsuite/gas/loongarch/imm_op.d          |  44 +++----
 gas/testsuite/gas/loongarch/jmp_op.d          |  44 +++----
 gas/testsuite/gas/loongarch/li.d              |   8 +-
 gas/testsuite/gas/loongarch/load_store_op.d   |  80 ++++++------
 gas/testsuite/gas/loongarch/macro_op.d        |   4 +-
 gas/testsuite/gas/loongarch/macro_op_32.d     |   4 +-
 .../gas/loongarch/macro_op_large_abs.d        |  14 +--
 .../gas/loongarch/macro_op_large_pc.d         |  14 +--
 gas/testsuite/gas/loongarch/nop.d             |   2 +-
 gas/testsuite/gas/loongarch/privilege_op.d    |   8 +-
 gas/testsuite/gas/loongarch/raw-insn.d        |  11 ++
 gas/testsuite/gas/loongarch/raw-insn.s        |   7 ++
 gas/testsuite/gas/loongarch/reloc.d           |   2 +-
 include/opcode/loongarch.h                    |   7 +-
 ld/testsuite/ld-loongarch-elf/jmp_op.d        |  40 +++---
 ld/testsuite/ld-loongarch-elf/macro_op.d      |  24 ++--
 opcodes/disassemble.c                         |   5 +
 opcodes/loongarch-dis.c                       | 114 ++++++++----------
 opcodes/loongarch-opc.c                       |  73 ++++++-----
 22 files changed, 333 insertions(+), 313 deletions(-)
 create mode 100644 gas/testsuite/gas/loongarch/raw-insn.d
 create mode 100644 gas/testsuite/gas/loongarch/raw-insn.s

-- 
2.39.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v4 1/6] LoongArch: support disassembling certain pseudo-instructions
  2023-02-15 18:02 [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks WANG Xuerui
@ 2023-02-15 18:02 ` WANG Xuerui
  2023-02-15 18:02 ` [PATCH v4 2/6] opcodes/loongarch: remove unused code WANG Xuerui
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-02-15 18:02 UTC (permalink / raw)
  To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Xi Ruoyao, WANG Xuerui

From: WANG Xuerui <git@xen0n.name>

Add a flag in the pinfo field for being able to mark certain specialized
matchers as disassembler-only, so some degree of isolation between
assembler-side and disassembler-side can be achieved.

This isolation is necessary, firstly because some pseudo-instructions
cannot be fully described in the opcode table, like `li.[wd]`, so the
corresponding opcode entry cannot have meaningful match/mask values.
Secondly, some of these pseudo-instructions can be realized in more than
one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can
be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie
disassembly of such aliases with the corresponding GAS support, only one
canonical form among the above would be recognized as `li.w`, and it
would mildly impact the readability of disassembly output.
People wanting the exact disassembly can always set `-M no-aliases` to
get the original behavior back.

In addition, in certain cases, information is irreversibly lost after
assembling, so perfect round-trip would not be possible in such cases.
For example, `li.w` and `li.d` of immediates within int32_t range
produce the same code; in this patch, `addi.d rd, $zero, imm` is treated
as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`,
due to the expressible value range well within 32 bits.
---
 gas/config/tc-loongarch.c                     |  3 ++-
 gas/testsuite/gas/loongarch/imm_ins.d         |  4 ++--
 gas/testsuite/gas/loongarch/imm_ins_32.d      |  2 +-
 gas/testsuite/gas/loongarch/jmp_op.d          | 12 +++++-----
 gas/testsuite/gas/loongarch/li.d              |  8 +++----
 gas/testsuite/gas/loongarch/macro_op.d        |  4 ++--
 .../gas/loongarch/macro_op_large_abs.d        | 14 +++++------
 .../gas/loongarch/macro_op_large_pc.d         | 14 +++++------
 gas/testsuite/gas/loongarch/nop.d             |  2 +-
 gas/testsuite/gas/loongarch/reloc.d           |  2 +-
 include/opcode/loongarch.h                    |  2 ++
 ld/testsuite/ld-loongarch-elf/jmp_op.d        |  2 +-
 ld/testsuite/ld-loongarch-elf/macro_op.d      | 24 +++++++++----------
 opcodes/loongarch-dis.c                       | 24 ++++++++++++-------
 opcodes/loongarch-opc.c                       | 23 ++++++++++++++++--
 15 files changed, 85 insertions(+), 55 deletions(-)

diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index dd47581ed7a..ae289ed18de 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -743,7 +743,8 @@ get_loongarch_opcode (struct loongarch_cl_insn *insn)
 	  for (it = ase->opcodes; it->name; it++)
 	    {
 	      if ((!it->include || (it->include && *it->include))
-		  && (!it->exclude || (it->exclude && !(*it->exclude))))
+		  && (!it->exclude || (it->exclude && !(*it->exclude)))
+		  && !(it->pinfo & INSN_DIS_ALIAS))
 		str_hash_insert (ase->name_hash_entry, it->name,
 				 (void *) it, 0);
 	    }
diff --git a/gas/testsuite/gas/loongarch/imm_ins.d b/gas/testsuite/gas/loongarch/imm_ins.d
index 0ceaead3edf..c588b5e0e25 100644
--- a/gas/testsuite/gas/loongarch/imm_ins.d
+++ b/gas/testsuite/gas/loongarch/imm_ins.d
@@ -8,10 +8,10 @@
 Disassembly of section .text:
 
 00000000.* <.text>:
-[ 	]+0:[ 	]+03848c0c[ 	]+ori[ 	]+\$t0,[ 	]+\$zero,[ 	]+0x123
+[ 	]+0:[ 	]+03848c0c[ 	]+li.w[ 	]+\$t0,[ 	]+0x123
 [ 	]+4:[ 	]+15ffe00d[ 	]+lu12i.w[ 	]+\$t1,[ 	]+-256\(0xfff00\)
 [ 	]+8:[ 	]+16001fed[ 	]+lu32i.d[ 	]+\$t1,[ 	]+255\(0xff\)
-[ 	]+c:[ 	]+02bffc0e[ 	]+addi.w[ 	]+\$t2,[ 	]+\$zero,[ 	]+-1\(0xfff\)
+[ 	]+c:[ 	]+02bffc0e[ 	]+li.w[ 	]+\$t2,[ 	]+-1\(0xfff\)
 [ 	]+10:[ 	]+1601ffee[ 	]+lu32i.d[ 	]+\$t2,[ 	]+4095\(0xfff\)
 [ 	]+14:[ 	]+0004b58b[ 	]+alsl.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+18:[ 	]+0006b58b[ 	]+alsl.wu[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.d b/gas/testsuite/gas/loongarch/imm_ins_32.d
index 0a826bfba5b..5fd5835a342 100644
--- a/gas/testsuite/gas/loongarch/imm_ins_32.d
+++ b/gas/testsuite/gas/loongarch/imm_ins_32.d
@@ -8,7 +8,7 @@
 Disassembly of section .text:
 
 00000000.* <.text>:
-[ 	]+0:[ 	]+03848c0c[ 	]+ori[ 	]+\$t0,[ 	]+\$zero,[ 	]+0x123
+[ 	]+0:[ 	]+03848c0c[ 	]+li.w[ 	]+\$t0,[ 	]+0x123
 [ 	]+4:[ 	]+0004b58b[ 	]+alsl.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+8:[ 	]+0006b58b[ 	]+alsl.wu[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+c:[ 	]+0009358b[ 	]+bytepick.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loongarch/jmp_op.d
index 218c13f9398..e34660c2fd4 100644
--- a/gas/testsuite/gas/loongarch/jmp_op.d
+++ b/gas/testsuite/gas/loongarch/jmp_op.d
@@ -7,15 +7,15 @@
 Disassembly of section .text:
 
 00000000.* <.text>:
-[ 	]+0:[ 	]+03400000[ 	]+[ 	]+andi[ 	]+\$zero, \$zero, 0x0
-[ 	]+4:[ 	]+63fffc04[ 	]+[ 	]+blt[ 	]+\$zero, \$a0, -4\(0x3fffc\)[ 	]+# 0x0
-[ 	]+8:[ 	]+67fff880[ 	]+[ 	]+bge[ 	]+\$a0, \$zero, -8\(0x3fff8\)[ 	]+# 0x0
-[ 	]+c:[ 	]+67fff404[ 	]+[ 	]+bge[ 	]+\$zero, \$a0, -12\(0x3fff4\)[ 	]+# 0x0
+[ 	]+0:[ 	]+03400000[ 	]+[ 	]+nop[ 	]+
+[ 	]+4:[ 	]+63fffc04[ 	]+[ 	]+bgtz[ 	]+\$a0, -4\(0x3fffc\)[ 	]+# 0x0
+[ 	]+8:[ 	]+67fff880[ 	]+[ 	]+bgez[ 	]+\$a0, -8\(0x3fff8\)[ 	]+# 0x0
+[ 	]+c:[ 	]+67fff404[ 	]+[ 	]+blez[ 	]+\$a0, -12\(0x3fff4\)[ 	]+# 0x0
 [ 	]+10:[ 	]+43fff09f[ 	]+[ 	]+beqz[ 	]+\$a0, -16\(0x7ffff0\)[ 	]+# 0x0
 [ 	]+14:[ 	]+47ffec9f[ 	]+[ 	]+bnez[ 	]+\$a0, -20\(0x7fffec\)[ 	]+# 0x0
 [ 	]+18:[ 	]+4bffe81f[ 	]+[ 	]+bceqz[ 	]+\$fcc0, -24\(0x7fffe8\)[ 	]+# 0x0
 [ 	]+1c:[ 	]+4bffe51f[ 	]+[ 	]+bcnez[ 	]+\$fcc0, -28\(0x7fffe4\)[ 	]+# 0x0
-[ 	]+20:[ 	]+4c000080[ 	]+[ 	]+jirl[ 	]+\$zero, \$a0, 0
+[ 	]+20:[ 	]+4c000080[ 	]+[ 	]+jr[ 	]+\$a0
 [ 	]+24:[ 	]+53ffdfff[ 	]+[ 	]+b[ 	]+-36\(0xfffffdc\)[ 	]+# 0x0
 [ 	]+28:[ 	]+57ffdbff[ 	]+[ 	]+bl[ 	]+-40\(0xfffffd8\)[ 	]+# 0x0
 [ 	]+2c:[ 	]+5bffd485[ 	]+[ 	]+beq[ 	]+\$a0, \$a1, -44\(0x3ffd4\)[ 	]+# 0x0
@@ -28,4 +28,4 @@ Disassembly of section .text:
 [ 	]+48:[ 	]+6bffb8a4[ 	]+[ 	]+bltu[ 	]+\$a1, \$a0, -72\(0x3ffb8\)[ 	]+# 0x0
 [ 	]+4c:[ 	]+6fffb485[ 	]+[ 	]+bgeu[ 	]+\$a0, \$a1, -76\(0x3ffb4\)[ 	]+# 0x0
 [ 	]+50:[ 	]+6fffb0a4[ 	]+[ 	]+bgeu[ 	]+\$a1, \$a0, -80\(0x3ffb0\)[ 	]+# 0x0
-[ 	]+54:[ 	]+4c000020[ 	]+[ 	]+jirl[ 	]+\$zero, \$ra, 0
+[ 	]+54:[ 	]+4c000020[ 	]+[ 	]+ret[ 	]+
diff --git a/gas/testsuite/gas/loongarch/li.d b/gas/testsuite/gas/loongarch/li.d
index 850a3f48e30..bb53fb1496e 100644
--- a/gas/testsuite/gas/loongarch/li.d
+++ b/gas/testsuite/gas/loongarch/li.d
@@ -8,14 +8,14 @@
 Disassembly of section .text:
 
 00000000.* <_start>:
-[ 	]+0:[ 	]+03803c06[ 	]+ori[ 	]+\$a2,[ 	]+\$zero,[ 	]+0xf
+[ 	]+0:[ 	]+03803c06[ 	]+li.w[ 	]+\$a2,[ 	]+0xf
 [ 	]+4:[ 	]+1a000005[ 	]+pcalau12i[ 	]+\$a1,[ 	]+0
 [ 	]+4:[ 	]+R_LARCH_PCALA_HI20[ 	]+.rodata
 [ 	]+8:[ 	]+02c000a5[ 	]+addi.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
 [ 	]+8:[ 	]+R_LARCH_PCALA_LO12[ 	]+.rodata
-[ 	]+c:[ 	]+03800404[ 	]+ori[ 	]+\$a0,[ 	]+\$zero,[ 	]+0x1
-[ 	]+10:[ 	]+0381000b[ 	]+ori[ 	]+\$a7,[ 	]+\$zero,[ 	]+0x40
+[ 	]+c:[ 	]+03800404[ 	]+li.w[ 	]+\$a0,[ 	]+0x1
+[ 	]+10:[ 	]+0381000b[ 	]+li.w[ 	]+\$a7,[ 	]+0x40
 [ 	]+14:[ 	]+002b0000[ 	]+syscall[ 	]+0x0
 [ 	]+18:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+1c:[ 	]+0381740b[ 	]+ori[ 	]+\$a7,[ 	]+\$zero,[ 	]+0x5d
+[ 	]+1c:[ 	]+0381740b[ 	]+li.w[ 	]+\$a7,[ 	]+0x5d
 [ 	]+20:[ 	]+002b0000[ 	]+syscall[ 	]+0x0
diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d
index d264c4f25c5..7ffb3e7b9c6 100644
--- a/gas/testsuite/gas/loongarch/macro_op.d
+++ b/gas/testsuite/gas/loongarch/macro_op.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
 
 00000000.* <.text>:
 [ 	]+0:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+4:[ 	]+02bffc04[ 	]+addi.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1\(0xfff\)
+[ 	]+4:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1\(0xfff\)
 [ 	]+8:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+c:[ 	]+02bffc04[ 	]+addi.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1\(0xfff\)
+[ 	]+c:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1\(0xfff\)
 [ 	]+10:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+10:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
 [ 	]+14:[ 	]+28c00084[ 	]+ld.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
diff --git a/gas/testsuite/gas/loongarch/macro_op_large_abs.d b/gas/testsuite/gas/loongarch/macro_op_large_abs.d
index c3214a859e6..3c35ef81223 100644
--- a/gas/testsuite/gas/loongarch/macro_op_large_abs.d
+++ b/gas/testsuite/gas/loongarch/macro_op_large_abs.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
 00000000.* <.text>:
 [ 	]+0:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+0:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
-[ 	]+4:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+4:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+4:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
 [ 	]+8:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+8:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.text
@@ -19,7 +19,7 @@ Disassembly of section .text:
 [ 	]+10:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+14:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+14:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.text
-[ 	]+18:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+18:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+18:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+1c:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+1c:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.text
@@ -28,7 +28,7 @@ Disassembly of section .text:
 [ 	]+24:[ 	]+380c1484[ 	]+ldx.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+28:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+28:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
-[ 	]+2c:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+2c:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+2c:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
 [ 	]+30:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+30:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.text
@@ -37,7 +37,7 @@ Disassembly of section .text:
 [ 	]+38:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+3c:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+3c:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.text
-[ 	]+40:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+40:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+40:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+44:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+44:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.text
@@ -50,7 +50,7 @@ Disassembly of section .text:
 [ 	]+54:[ 	]+R_LARCH_TLS_LE_LO12[ 	]+TLS1
 [ 	]+58:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+58:[ 	]+R_LARCH_TLS_IE_PC_HI20[ 	]+TLS1
-[ 	]+5c:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+5c:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+5c:[ 	]+R_LARCH_TLS_IE_PC_LO12[ 	]+TLS1
 [ 	]+60:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+60:[ 	]+R_LARCH_TLS_IE64_PC_LO20[ 	]+TLS1
@@ -59,7 +59,7 @@ Disassembly of section .text:
 [ 	]+68:[ 	]+380c1484[ 	]+ldx.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+6c:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+6c:[ 	]+R_LARCH_TLS_LD_PC_HI20[ 	]+TLS1
-[ 	]+70:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+70:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+70:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
 [ 	]+74:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+74:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
@@ -68,7 +68,7 @@ Disassembly of section .text:
 [ 	]+7c:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+80:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+80:[ 	]+R_LARCH_TLS_GD_PC_HI20[ 	]+TLS1
-[ 	]+84:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+84:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+84:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
 [ 	]+88:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+88:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
diff --git a/gas/testsuite/gas/loongarch/macro_op_large_pc.d b/gas/testsuite/gas/loongarch/macro_op_large_pc.d
index c3214a859e6..3c35ef81223 100644
--- a/gas/testsuite/gas/loongarch/macro_op_large_pc.d
+++ b/gas/testsuite/gas/loongarch/macro_op_large_pc.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
 00000000.* <.text>:
 [ 	]+0:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+0:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
-[ 	]+4:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+4:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+4:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
 [ 	]+8:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+8:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.text
@@ -19,7 +19,7 @@ Disassembly of section .text:
 [ 	]+10:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+14:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+14:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.text
-[ 	]+18:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+18:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+18:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+1c:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+1c:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.text
@@ -28,7 +28,7 @@ Disassembly of section .text:
 [ 	]+24:[ 	]+380c1484[ 	]+ldx.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+28:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+28:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
-[ 	]+2c:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+2c:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+2c:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
 [ 	]+30:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+30:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.text
@@ -37,7 +37,7 @@ Disassembly of section .text:
 [ 	]+38:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+3c:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+3c:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.text
-[ 	]+40:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+40:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+40:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+44:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+44:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.text
@@ -50,7 +50,7 @@ Disassembly of section .text:
 [ 	]+54:[ 	]+R_LARCH_TLS_LE_LO12[ 	]+TLS1
 [ 	]+58:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+58:[ 	]+R_LARCH_TLS_IE_PC_HI20[ 	]+TLS1
-[ 	]+5c:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+5c:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+5c:[ 	]+R_LARCH_TLS_IE_PC_LO12[ 	]+TLS1
 [ 	]+60:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+60:[ 	]+R_LARCH_TLS_IE64_PC_LO20[ 	]+TLS1
@@ -59,7 +59,7 @@ Disassembly of section .text:
 [ 	]+68:[ 	]+380c1484[ 	]+ldx.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+6c:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+6c:[ 	]+R_LARCH_TLS_LD_PC_HI20[ 	]+TLS1
-[ 	]+70:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+70:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+70:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
 [ 	]+74:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+74:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
@@ -68,7 +68,7 @@ Disassembly of section .text:
 [ 	]+7c:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+80:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+80:[ 	]+R_LARCH_TLS_GD_PC_HI20[ 	]+TLS1
-[ 	]+84:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+84:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+84:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
 [ 	]+88:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+88:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
diff --git a/gas/testsuite/gas/loongarch/nop.d b/gas/testsuite/gas/loongarch/nop.d
index 4cdcc5ce0d2..222456e8b8c 100644
--- a/gas/testsuite/gas/loongarch/nop.d
+++ b/gas/testsuite/gas/loongarch/nop.d
@@ -7,4 +7,4 @@
 Disassembly of section .text:
 
 0+000 <target>:
-[ 	]+0:[ 	]+03400000[ 	]+andi[ 	]+\$zero, \$zero, 0x0
+[ 	]+0:[ 	]+03400000[ 	]+nop[ 	]+
diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d
index 6f5f110b1af..c3820c55f98 100644
--- a/gas/testsuite/gas/loongarch/reloc.d
+++ b/gas/testsuite/gas/loongarch/reloc.d
@@ -8,7 +8,7 @@
 Disassembly of section .text:
 
 00000000.* <.text>:
-[ 	]+0:[ 	]+03400000[ 	]+andi[ 	]+\$zero,[ 	]+\$zero,[ 	]+0x0
+[ 	]+0:[ 	]+03400000[ 	]+nop[ 	]+
 [ 	]+4:[ 	]+58000085[ 	]+beq[ 	]+\$a0,[ 	]+\$a1,[ 	]+0[ 	]+#[ 	]+0x4
 [ 	]+4:[ 	]+R_LARCH_B16[ 	]+.L1
 [ 	]+8:[ 	]+5c000085[ 	]+bne[ 	]+\$a0,[ 	]+\$a1,[ 	]+0[ 	]+#[ 	]+0x8
diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h
index 548732e5c70..797ed45b67c 100644
--- a/include/opcode/loongarch.h
+++ b/include/opcode/loongarch.h
@@ -118,6 +118,8 @@ dec2 : [1-9][0-9]?
 
     const unsigned long pinfo;
 #define USELESS 0x0l
+/* Instruction is a simple alias only for disassembler use.  */
+#define INSN_DIS_ALIAS		0x00000001l
   };
 
   struct hash_control;
diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d
index 218c13f9398..d646c75fce0 100644
--- a/ld/testsuite/ld-loongarch-elf/jmp_op.d
+++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d
@@ -1,5 +1,5 @@
 #as:
-#objdump: -dr
+#objdump: -dr -M no-aliases
 
 .*:[    ]+file format .*
 
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
index a1c64fcf00f..a419c509584 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -8,9 +8,9 @@ Disassembly of section .text:
 
 00000000.* <.text>:
 [ 	]+0:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+4:[ 	]+02bffc04[ 	]+addi.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1\(0xfff\)
+[ 	]+4:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1\(0xfff\)
 [ 	]+8:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+c:[ 	]+02bffc04[ 	]+addi.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1\(0xfff\)
+[ 	]+c:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1\(0xfff\)
 [ 	]+10:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+10:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.text
 [ 	]+14:[ 	]+28c00084[ 	]+ld.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
@@ -21,7 +21,7 @@ Disassembly of section .text:
 [ 	]+1c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+20:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+20:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.text
-[ 	]+24:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+24:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+24:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+28:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+28:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.text
@@ -34,7 +34,7 @@ Disassembly of section .text:
 [ 	]+38:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+3c:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+3c:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.text
-[ 	]+40:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+40:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+40:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+44:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+44:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.text
@@ -47,7 +47,7 @@ Disassembly of section .text:
 [ 	]+54:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+58:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+58:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.text
-[ 	]+5c:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+5c:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+5c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+60:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+60:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.text
@@ -60,7 +60,7 @@ Disassembly of section .text:
 [ 	]+70:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
 [ 	]+74:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+74:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
-[ 	]+78:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+78:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+78:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
 [ 	]+7c:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+7c:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.text
@@ -73,7 +73,7 @@ Disassembly of section .text:
 [ 	]+8c:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
 [ 	]+90:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+90:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
-[ 	]+94:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+94:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+94:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
 [ 	]+98:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+98:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.text
@@ -99,7 +99,7 @@ Disassembly of section .text:
 [ 	]+c0:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
 [ 	]+c4:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+c4:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
-[ 	]+c8:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+c8:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+c8:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
 [ 	]+cc:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+cc:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.text
@@ -112,7 +112,7 @@ Disassembly of section .text:
 [ 	]+dc:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+e0:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+e0:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.text
-[ 	]+e4:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+e4:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+e4:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.text
 [ 	]+e8:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+e8:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.text
@@ -129,7 +129,7 @@ Disassembly of section .text:
 [ 	]+100:[ 	]+R_LARCH_TLS_IE_PC_LO12[ 	]+TLS1
 [ 	]+104:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+104:[ 	]+R_LARCH_TLS_IE_PC_HI20[ 	]+TLS1
-[ 	]+108:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+108:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+108:[ 	]+R_LARCH_TLS_IE_PC_LO12[ 	]+TLS1
 [ 	]+10c:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+10c:[ 	]+R_LARCH_TLS_IE64_PC_LO20[ 	]+TLS1
@@ -142,7 +142,7 @@ Disassembly of section .text:
 [ 	]+11c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
 [ 	]+120:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+120:[ 	]+R_LARCH_TLS_LD_PC_HI20[ 	]+TLS1
-[ 	]+124:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+124:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+124:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
 [ 	]+128:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+128:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
@@ -155,7 +155,7 @@ Disassembly of section .text:
 [ 	]+138:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
 [ 	]+13c:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+13c:[ 	]+R_LARCH_TLS_GD_PC_HI20[ 	]+TLS1
-[ 	]+140:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+140:[ 	]+02c00005[ 	]+li.d[ 	]+\$a1,[ 	]+0
 [ 	]+140:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
 [ 	]+144:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+144:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index d064d30d553..d747bc59c50 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -25,6 +25,14 @@
 #include "libiberty.h"
 #include <stdlib.h>
 
+static bool loongarch_dis_show_aliases = true;
+static const char *const *loongarch_r_disname = NULL;
+static const char *const *loongarch_f_disname = NULL;
+static const char *const *loongarch_c_disname = NULL;
+static const char *const *loongarch_cr_disname = NULL;
+static const char *const *loongarch_v_disname = NULL;
+static const char *const *loongarch_x_disname = NULL;
+
 static const struct loongarch_opcode *
 get_loongarch_opcode_by_binfmt (insn_t insn)
 {
@@ -41,7 +49,9 @@ get_loongarch_opcode_by_binfmt (insn_t insn)
 	{
 	  for (it = ase->opcodes; it->mask; it++)
 	    if (!ase->opc_htab[LARCH_INSN_OPC (it->match)]
-		&& it->macro == NULL)
+		&& it->macro == NULL
+		&& (!(it->pinfo & INSN_DIS_ALIAS)
+		    || loongarch_dis_show_aliases))
 	      ase->opc_htab[LARCH_INSN_OPC (it->match)] = it;
 	  for (i = 0; i < 16; i++)
 	    if (!ase->opc_htab[i])
@@ -59,13 +69,6 @@ get_loongarch_opcode_by_binfmt (insn_t insn)
   return NULL;
 }
 
-static const char *const *loongarch_r_disname = NULL;
-static const char *const *loongarch_f_disname = NULL;
-static const char *const *loongarch_c_disname = NULL;
-static const char *const *loongarch_cr_disname = NULL;
-static const char *const *loongarch_v_disname = NULL;
-static const char *const *loongarch_x_disname = NULL;
-
 static void
 set_default_loongarch_dis_options (void)
 {
@@ -87,6 +90,9 @@ set_default_loongarch_dis_options (void)
 static int
 parse_loongarch_dis_option (const char *option)
 {
+  if (strcmp (option, "no-aliases") == 0)
+    loongarch_dis_show_aliases = false;
+
   if (strcmp (option, "numeric") == 0)
     {
       loongarch_r_disname = loongarch_r_normal_name;
@@ -301,6 +307,8 @@ print_loongarch_disassembler_options (FILE *stream)
 The following LoongArch disassembler options are supported for use\n\
 with the -M switch (multiple options should be separated by commas):\n"));
 
+  fprintf (stream, _("\n\
+    no-aliases    Use canonical instruction forms.\n"));
   fprintf (stream, _("\n\
     numeric       Print numeric register names, rather than ABI names.\n"));
   fprintf (stream, _("\n"));
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 32f73075bad..23e2ff689c8 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -331,9 +331,29 @@ static struct loongarch_opcode loongarch_macro_opcodes[] =
   { 0 } /* Terminate the list.  */
 };
 
+static struct loongarch_opcode loongarch_alias_opcodes[] =
+{
+  /* match,	mask,		name,		format,				macro,	include, exclude, pinfo.  */
+  { 0x00150000,	0xfffffc00,	"move",		"r0:5,r5:5",			0,	0, 0, INSN_DIS_ALIAS }, /* or rd, rj, zero */
+  { 0x02800000, 0xffc003e0,	"li.w",		"r0:5,s10:12",			0,	0, 0, INSN_DIS_ALIAS }, /* addi.w rd, zero, simm */
+  { 0x02c00000, 0xffc003e0,	"li.d",		"r0:5,s10:12",			0,	0, 0, INSN_DIS_ALIAS }, /* addi.d rd, zero, simm */
+  { 0x03400000,	0xffffffff,	"nop",		"",				0,	0, 0, INSN_DIS_ALIAS }, /* andi zero, zero, 0 */
+  { 0x03800000, 0xffc003e0,	"li.w",		"r0:5,u10:12",			0,	0, 0, INSN_DIS_ALIAS }, /* ori rd, zero, uimm */
+  /* ret must come before jr because it is more specific.  */
+  { 0x4c000020,	0xffffffff,	"ret",		"",				0,	0, 0, INSN_DIS_ALIAS }, /* jirl zero, ra, 0 */
+  { 0x4c000000,	0xfffffc1f,	"jr",		"r5:5",				0,	0, 0, INSN_DIS_ALIAS }, /* jirl zero, rj, 0 */
+  { 0x60000000,	0xfc00001f,	"bltz",		"r5:5,sb10:16<<2",		0,	0, 0, INSN_DIS_ALIAS }, /* blt rj, zero, offset */
+  { 0x60000000,	0xfc0003e0,	"bgtz",		"r0:5,sb10:16<<2",		0,	0, 0, INSN_DIS_ALIAS }, /* blt zero, rd, offset */
+  { 0x64000000,	0xfc00001f,	"bgez",		"r5:5,sb10:16<<2",		0,	0, 0, INSN_DIS_ALIAS }, /* bge rj, zero, offset */
+  { 0x64000000,	0xfc0003e0,	"blez",		"r0:5,sb10:16<<2",		0,	0, 0, INSN_DIS_ALIAS }, /* bge zero, rd, offset */
+  { 0 } /* Terminate the list.  */
+};
+
+
 static struct loongarch_opcode loongarch_fix_opcodes[] =
 {
   /* match,	mask,		name,		format,				macro,			include, exclude, pinfo.  */
+  { 0x0,	0x0,		"move",		"r,r",				"or %1,%2,$r0",		0,	0,	0 },
   { 0x00001000, 0xfffffc00,	"clo.w",	"r0:5,r5:5",			0,			0,	0,	0 },
   { 0x00001400, 0xfffffc00,	"clz.w",	"r0:5,r5:5",			0,			0,	0,	0 },
   { 0x00001800, 0xfffffc00,	"cto.w",	"r0:5,r5:5",			0,			0,	0,	0 },
@@ -354,8 +374,6 @@ static struct loongarch_opcode loongarch_fix_opcodes[] =
   { 0x00005400, 0xfffffc00,	"bitrev.d",	"r0:5,r5:5",			0,			0,	0,	0 },
   { 0x00005800, 0xfffffc00,	"ext.w.h",	"r0:5,r5:5",			0,			0,	0,	0 },
   { 0x00005c00, 0xfffffc00,	"ext.w.b",	"r0:5,r5:5",			0,			0,	0,	0 },
-  /* or %1,%2,$r0  */
-  { 0x00150000, 0xfffffc00,	"move",		"r0:5,r5:5",			0,			0,	0,	0 },
   { 0x00006000, 0xfffffc00,	"rdtimel.w",	"r0:5,r5:5",			0,			0,	0,	0 },
   { 0x00006400, 0xfffffc00,	"rdtimeh.w",	"r0:5,r5:5",			0,			0,	0,	0 },
   { 0x00006800, 0xfffffc00,	"rdtime.d",	"r0:5,r5:5",			0,			0,	0,	0 },
@@ -848,6 +866,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
 struct loongarch_ase loongarch_ASEs[] =
 {
   { &LARCH_opts.ase_ilp32, loongarch_macro_opcodes,		0, 0, { 0 }, 0, 0 },
+  { &LARCH_opts.ase_ilp32, loongarch_alias_opcodes,		0, 0, { 0 }, 0, 0 },
   { &LARCH_opts.ase_ilp32, loongarch_imm_opcodes,		0, 0, { 0 }, 0, 0 },
   { &LARCH_opts.ase_ilp32, loongarch_privilege_opcodes,		0, 0, { 0 }, 0, 0 },
   { &LARCH_opts.ase_ilp32, loongarch_load_store_opcodes,	0, 0, { 0 }, 0, 0 },
-- 
2.39.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v4 2/6] opcodes/loongarch: remove unused code
  2023-02-15 18:02 [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks WANG Xuerui
  2023-02-15 18:02 ` [PATCH v4 1/6] LoongArch: support disassembling certain pseudo-instructions WANG Xuerui
@ 2023-02-15 18:02 ` WANG Xuerui
  2023-02-15 18:03 ` [PATCH v4 3/6] opcodes/loongarch: implement style support in the disassembler WANG Xuerui
                   ` (4 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-02-15 18:02 UTC (permalink / raw)
  To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Xi Ruoyao, WANG Xuerui

From: WANG Xuerui <git@xen0n.name>

Remove some unused declarations and code.
---
 include/opcode/loongarch.h |  5 -----
 opcodes/loongarch-dis.c    | 35 -----------------------------------
 2 files changed, 40 deletions(-)

diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h
index 797ed45b67c..a374f8dabd6 100644
--- a/include/opcode/loongarch.h
+++ b/include/opcode/loongarch.h
@@ -174,11 +174,6 @@ dec2 : [1-9][0-9]?
 
   extern void loongarch_eliminate_adjacent_repeat_char (char *dest, char c);
 
-  extern int loongarch_parse_dis_options (const char *opts_in);
-  extern void loongarch_disassemble_one (
-    int64_t pc, insn_t insn,
-    int (*fprintf_func) (void *stream, const char *format, ...), void *stream);
-
   extern const char *const loongarch_r_normal_name[32];
   extern const char *const loongarch_r_lp64_name[32];
   extern const char *const loongarch_r_lp64_name1[32];
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index d747bc59c50..085d0ab2d75 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -313,38 +313,3 @@ with the -M switch (multiple options should be separated by commas):\n"));
     numeric       Print numeric register names, rather than ABI names.\n"));
   fprintf (stream, _("\n"));
 }
-
-int
-loongarch_parse_dis_options (const char *opts_in)
-{
-  return parse_loongarch_dis_options (opts_in);
-}
-
-static void
-my_print_address_func (bfd_vma addr, struct disassemble_info *dinfo)
-{
-  dinfo->fprintf_func (dinfo->stream, "0x%llx", (long long) addr);
-}
-
-void
-loongarch_disassemble_one (int64_t pc, insn_t insn,
-			   int (*fprintf_func) (void *stream,
-						const char *format, ...),
-			   void *stream)
-{
-  static struct disassemble_info my_disinfo =
-  {
-    .print_address_func = my_print_address_func,
-  };
-  static int not_init_yet = 1;
-  if (not_init_yet)
-    {
-      loongarch_parse_dis_options (NULL);
-      not_init_yet = 0;
-    }
-
-  my_disinfo.fprintf_func = fprintf_func;
-  my_disinfo.stream = stream;
-  my_disinfo.target = pc;
-  disassemble_one (insn, &my_disinfo);
-}
-- 
2.39.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v4 3/6] opcodes/loongarch: implement style support in the disassembler
  2023-02-15 18:02 [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks WANG Xuerui
  2023-02-15 18:02 ` [PATCH v4 1/6] LoongArch: support disassembling certain pseudo-instructions WANG Xuerui
  2023-02-15 18:02 ` [PATCH v4 2/6] opcodes/loongarch: remove unused code WANG Xuerui
@ 2023-02-15 18:03 ` WANG Xuerui
  2023-02-15 18:03 ` [PATCH v4 4/6] opcodes/loongarch: style disassembled address offsets as such WANG Xuerui
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-02-15 18:03 UTC (permalink / raw)
  To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Xi Ruoyao, WANG Xuerui

From: WANG Xuerui <git@xen0n.name>

Update the LoongArch disassembler to supply style information to the
disassembler output. The output formatting remains unchanged.
---
 opcodes/disassemble.c   |  5 +++++
 opcodes/loongarch-dis.c | 43 ++++++++++++++++++++---------------------
 2 files changed, 26 insertions(+), 22 deletions(-)

diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index ff8cb87f599..0216811c955 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -647,6 +647,11 @@ disassemble_init_for_target (struct disassemble_info * info)
       info->skip_zeroes = 16;
       break;
 #endif
+#ifdef ARCH_loongarch
+    case bfd_arch_loongarch:
+      info->created_styled_output = true;
+      break;
+#endif
 #ifdef ARCH_tic4x
     case bfd_arch_tic4x:
       info->skip_zeroes = 32;
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 085d0ab2d75..3238495a845 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -136,7 +136,7 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
   if (esc1)
     {
       if (need_comma)
-	info->fprintf_func (info->stream, ", ");
+	info->fprintf_styled_func (info->stream, dis_style_text, ", ");
       need_comma = 1;
       imm = loongarch_decode_imm (bit_field, insn, 1);
       u_imm = loongarch_decode_imm (bit_field, insn, 0);
@@ -145,35 +145,38 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
   switch (esc1)
     {
     case 'r':
-      info->fprintf_func (info->stream, "%s", loongarch_r_disname[u_imm]);
+      info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_r_disname[u_imm]);
       break;
     case 'f':
-      info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_imm]);
+      info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_f_disname[u_imm]);
       break;
     case 'c':
       switch (esc2)
 	{
 	case 'r':
-	  info->fprintf_func (info->stream, "%s", loongarch_cr_disname[u_imm]);
+	  info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_cr_disname[u_imm]);
 	  break;
 	default:
-	  info->fprintf_func (info->stream, "%s", loongarch_c_disname[u_imm]);
+	  info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_c_disname[u_imm]);
 	}
       break;
     case 'v':
-      info->fprintf_func (info->stream, "%s", loongarch_v_disname[u_imm]);
+      info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_v_disname[u_imm]);
       break;
     case 'x':
-      info->fprintf_func (info->stream, "%s", loongarch_x_disname[u_imm]);
+      info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_x_disname[u_imm]);
       break;
     case 'u':
-      info->fprintf_func (info->stream, "0x%x", u_imm);
+      info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%x", u_imm);
       break;
     case 's':
       if (imm == 0)
-	info->fprintf_func (info->stream, "%d", imm);
+	info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
       else
-	info->fprintf_func (info->stream, "%d(0x%x)", imm, u_imm);
+	{
+	  info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
+	  info->fprintf_styled_func (info->stream, dis_style_text, "(0x%x)", u_imm);
+	}
       switch (esc2)
 	{
 	case 'b':
@@ -227,44 +230,40 @@ disassemble_one (insn_t insn, struct disassemble_info *info)
   for (i = 31; 0 <= i; i--)
     {
       if (t & insn)
-	info->fprintf_func (info->stream, "1");
+	info->fprintf_styled_func (info->stream, dis_style_text, "1");
       else
-	info->fprintf_func (info->stream, "0");
+	info->fprintf_styled_func (info->stream, dis_style_text, "0");
       if (have_space[i])
-	info->fprintf_func (info->stream, " ");
+	info->fprintf_styled_func (info->stream, dis_style_text, " ");
       t = t >> 1;
     }
-  info->fprintf_func (info->stream, "\t");
+  info->fprintf_styled_func (info->stream, dis_style_text, "\t");
 #endif
 
   if (!opc)
     {
       info->insn_type = dis_noninsn;
-      info->fprintf_func (info->stream, "0x%08x", insn);
+      info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%08x", insn);
       return;
     }
 
   info->insn_type = dis_nonbranch;
-  info->fprintf_func (info->stream, "%-12s", opc->name);
+  info->fprintf_styled_func (info->stream, dis_style_mnemonic, "%-12s", opc->name);
 
   {
     char *fake_args = xmalloc (strlen (opc->format) + 1);
     const char *fake_arg_strs[MAX_ARG_NUM_PLUS_2];
     strcpy (fake_args, opc->format);
     if (0 < loongarch_split_args_by_comma (fake_args, fake_arg_strs))
-      info->fprintf_func (info->stream, "\t");
+      info->fprintf_styled_func (info->stream, dis_style_text, "\t");
     info->private_data = &insn;
     loongarch_foreach_args (opc->format, fake_arg_strs, dis_one_arg, info);
     free (fake_args);
   }
 
-  if (info->insn_type == dis_branch || info->insn_type == dis_condbranch
-      /* Someother if we have extra info to print.  */)
-    info->fprintf_func (info->stream, "\t#");
-
   if (info->insn_type == dis_branch || info->insn_type == dis_condbranch)
     {
-      info->fprintf_func (info->stream, " ");
+      info->fprintf_styled_func (info->stream, dis_style_comment_start, "\t# ");
       info->print_address_func (info->target, info);
     }
 }
-- 
2.39.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v4 4/6] opcodes/loongarch: style disassembled address offsets as such
  2023-02-15 18:02 [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks WANG Xuerui
                   ` (2 preceding siblings ...)
  2023-02-15 18:03 ` [PATCH v4 3/6] opcodes/loongarch: implement style support in the disassembler WANG Xuerui
@ 2023-02-15 18:03 ` WANG Xuerui
  2023-02-15 18:03 ` [PATCH v4 5/6] opcodes/loongarch: do not print hex notation for signed immediates WANG Xuerui
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-02-15 18:03 UTC (permalink / raw)
  To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Xi Ruoyao, WANG Xuerui

From: WANG Xuerui <git@xen0n.name>

Add a modifier char 'o' telling the disassembler to print the immediate
using the address offset style, and mark the memory access instructions'
offset operands as such.
---
 opcodes/loongarch-dis.c | 19 +++++++++++++---
 opcodes/loongarch-opc.c | 50 ++++++++++++++++++++---------------------
 2 files changed, 41 insertions(+), 28 deletions(-)

diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 3238495a845..8eacea4ed94 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -132,6 +132,7 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
   struct disassemble_info *info = context;
   insn_t insn = *(insn_t *) info->private_data;
   int32_t imm, u_imm;
+  enum disassembler_style style;
 
   if (esc1)
     {
@@ -167,14 +168,26 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
       info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_x_disname[u_imm]);
       break;
     case 'u':
-      info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%x", u_imm);
+      style = esc2 == 'o' ? dis_style_address_offset : dis_style_immediate;
+      info->fprintf_styled_func (info->stream, style, "0x%x", u_imm);
       break;
     case 's':
+      switch (esc2)
+	{
+	case 'b':
+	case 'o':
+	  /* Both represent address offsets.  */
+	  style = dis_style_address_offset;
+	  break;
+	default:
+	  style = dis_style_immediate;
+	  break;
+	}
       if (imm == 0)
-	info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
+	info->fprintf_styled_func (info->stream, style, "%d", imm);
       else
 	{
-	  info->fprintf_styled_func (info->stream, dis_style_immediate, "%d", imm);
+	  info->fprintf_styled_func (info->stream, style, "%d", imm);
 	  info->fprintf_styled_func (info->stream, dis_style_text, "(0x%x)", u_imm);
 	}
       switch (esc2)
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 23e2ff689c8..2581e986174 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -663,26 +663,26 @@ static struct loongarch_opcode loongarch_4opt_double_float_opcodes[] =
 static struct loongarch_opcode loongarch_load_store_opcodes[] =
 {
   /* match,	mask,		name,		format,				macro,			include, exclude, pinfo.  */
-  { 0x20000000, 0xff000000,	"ll.w",		"r0:5,r5:5,s10:14<<2",		0,			0,	0,	0 },
-  { 0x21000000, 0xff000000,	"sc.w",		"r0:5,r5:5,s10:14<<2",		0,			0,	0,	0 },
-  { 0x22000000, 0xff000000,	"ll.d",		"r0:5,r5:5,s10:14<<2",		0,			0,	0,	0 },
-  { 0x23000000, 0xff000000,	"sc.d",		"r0:5,r5:5,s10:14<<2",		0,			0,	0,	0 },
-  { 0x24000000, 0xff000000,	"ldptr.w",	"r0:5,r5:5,s10:14<<2",		0,			0,	0,	0 },
-  { 0x25000000, 0xff000000,	"stptr.w",	"r0:5,r5:5,s10:14<<2",		0,			0,	0,	0 },
-  { 0x26000000, 0xff000000,	"ldptr.d",	"r0:5,r5:5,s10:14<<2",		0,			0,	0,	0 },
-  { 0x27000000, 0xff000000,	"stptr.d",	"r0:5,r5:5,s10:14<<2",		0,			0,	0,	0 },
-  { 0x28000000, 0xffc00000,	"ld.b",		"r0:5,r5:5,s10:12",		0,			0,	0,	0 },
-  { 0x28400000, 0xffc00000,	"ld.h",		"r0:5,r5:5,s10:12",		0,			0,	0,	0 },
-  { 0x28800000, 0xffc00000,	"ld.w",		"r0:5,r5:5,s10:12",		0,			0,	0,	0 },
-  { 0x28c00000, 0xffc00000,	"ld.d",		"r0:5,r5:5,s10:12",		0,			0,	0,	0 },
-  { 0x29000000, 0xffc00000,	"st.b",		"r0:5,r5:5,s10:12",		0,			0,	0,	0 },
-  { 0x29400000, 0xffc00000,	"st.h",		"r0:5,r5:5,s10:12",		0,			0,	0,	0 },
-  { 0x29800000, 0xffc00000,	"st.w",		"r0:5,r5:5,s10:12",		0,			0,	0,	0 },
-  { 0x29c00000, 0xffc00000,	"st.d",		"r0:5,r5:5,s10:12",		0,			0,	0,	0 },
-  { 0x2a000000, 0xffc00000,	"ld.bu",	"r0:5,r5:5,s10:12",		0,			0,	0,	0 },
-  { 0x2a400000, 0xffc00000,	"ld.hu",	"r0:5,r5:5,s10:12",		0,			0,	0,	0 },
-  { 0x2a800000, 0xffc00000,	"ld.wu",	"r0:5,r5:5,s10:12",		0,			0,	0,	0 },
-  { 0x2ac00000, 0xffc00000,	"preld",	"u0:5,r5:5,s10:12",		0,			0,	0,	0 },
+  { 0x20000000, 0xff000000,	"ll.w",		"r0:5,r5:5,so10:14<<2",		0,			0,	0,	0 },
+  { 0x21000000, 0xff000000,	"sc.w",		"r0:5,r5:5,so10:14<<2",		0,			0,	0,	0 },
+  { 0x22000000, 0xff000000,	"ll.d",		"r0:5,r5:5,so10:14<<2",		0,			0,	0,	0 },
+  { 0x23000000, 0xff000000,	"sc.d",		"r0:5,r5:5,so10:14<<2",		0,			0,	0,	0 },
+  { 0x24000000, 0xff000000,	"ldptr.w",	"r0:5,r5:5,so10:14<<2",		0,			0,	0,	0 },
+  { 0x25000000, 0xff000000,	"stptr.w",	"r0:5,r5:5,so10:14<<2",		0,			0,	0,	0 },
+  { 0x26000000, 0xff000000,	"ldptr.d",	"r0:5,r5:5,so10:14<<2",		0,			0,	0,	0 },
+  { 0x27000000, 0xff000000,	"stptr.d",	"r0:5,r5:5,so10:14<<2",		0,			0,	0,	0 },
+  { 0x28000000, 0xffc00000,	"ld.b",		"r0:5,r5:5,so10:12",		0,			0,	0,	0 },
+  { 0x28400000, 0xffc00000,	"ld.h",		"r0:5,r5:5,so10:12",		0,			0,	0,	0 },
+  { 0x28800000, 0xffc00000,	"ld.w",		"r0:5,r5:5,so10:12",		0,			0,	0,	0 },
+  { 0x28c00000, 0xffc00000,	"ld.d",		"r0:5,r5:5,so10:12",		0,			0,	0,	0 },
+  { 0x29000000, 0xffc00000,	"st.b",		"r0:5,r5:5,so10:12",		0,			0,	0,	0 },
+  { 0x29400000, 0xffc00000,	"st.h",		"r0:5,r5:5,so10:12",		0,			0,	0,	0 },
+  { 0x29800000, 0xffc00000,	"st.w",		"r0:5,r5:5,so10:12",		0,			0,	0,	0 },
+  { 0x29c00000, 0xffc00000,	"st.d",		"r0:5,r5:5,so10:12",		0,			0,	0,	0 },
+  { 0x2a000000, 0xffc00000,	"ld.bu",	"r0:5,r5:5,so10:12",		0,			0,	0,	0 },
+  { 0x2a400000, 0xffc00000,	"ld.hu",	"r0:5,r5:5,so10:12",		0,			0,	0,	0 },
+  { 0x2a800000, 0xffc00000,	"ld.wu",	"r0:5,r5:5,so10:12",		0,			0,	0,	0 },
+  { 0x2ac00000, 0xffc00000,	"preld",	"u0:5,r5:5,so10:12",		0,			0,	0,	0 },
   { 0x38000000, 0xffff8000,	"ldx.b",	"r0:5,r5:5,r10:5",		0,			0,	0,	0 },
   { 0x38040000, 0xffff8000,	"ldx.h",	"r0:5,r5:5,r10:5",		0,			0,	0,	0 },
   { 0x38080000, 0xffff8000,	"ldx.w",	"r0:5,r5:5,r10:5",		0,			0,	0,	0 },
@@ -791,8 +791,8 @@ static struct loongarch_opcode loongarch_load_store_opcodes[] =
 static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] =
 {
   /* match,	mask,		name,		format,				macro,	include,		exclude, pinfo.  */
-  { 0x2b000000, 0xffc00000,	"fld.s",	"f0:5,r5:5,s10:12",		0,	0,			0,	0 },
-  { 0x2b400000, 0xffc00000,	"fst.s",	"f0:5,r5:5,s10:12",		0,	0,			0,	0 },
+  { 0x2b000000, 0xffc00000,	"fld.s",	"f0:5,r5:5,so10:12",		0,	0,			0,	0 },
+  { 0x2b400000, 0xffc00000,	"fst.s",	"f0:5,r5:5,so10:12",		0,	0,			0,	0 },
   { 0x38300000, 0xffff8000,	"fldx.s",	"f0:5,r5:5,r10:5",		0,	&LARCH_opts.ase_lp64,	0,	0 },
   { 0x38380000, 0xffff8000,	"fstx.s",	"f0:5,r5:5,r10:5",		0,	&LARCH_opts.ase_lp64,	0,	0 },
   { 0x38740000, 0xffff8000,	"fldgt.s",	"f0:5,r5:5,r10:5",		0,	&LARCH_opts.ase_lp64,	0,	0 },
@@ -805,8 +805,8 @@ static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] =
 static struct loongarch_opcode loongarch_double_float_load_store_opcodes[] =
 {
   /* match,	mask,		name,		format,				macro,	include,		exclude, pinfo.  */
-  { 0x2b800000, 0xffc00000,	"fld.d",	"f0:5,r5:5,s10:12",		0,	0,			0,	0 },
-  { 0x2bc00000, 0xffc00000,	"fst.d",	"f0:5,r5:5,s10:12",		0,	0,			0,	0 },
+  { 0x2b800000, 0xffc00000,	"fld.d",	"f0:5,r5:5,so10:12",		0,	0,			0,	0 },
+  { 0x2bc00000, 0xffc00000,	"fst.d",	"f0:5,r5:5,so10:12",		0,	0,			0,	0 },
   { 0x38340000, 0xffff8000,	"fldx.d",	"f0:5,r5:5,r10:5",		0,	&LARCH_opts.ase_lp64,	0,	0 },
   { 0x383c0000, 0xffff8000,	"fstx.d",	"f0:5,r5:5,r10:5",		0,	&LARCH_opts.ase_lp64,	0,	0 },
   { 0x38748000, 0xffff8000,	"fldgt.d",	"f0:5,r5:5,r10:5",		0,	&LARCH_opts.ase_lp64,	0,	0 },
@@ -832,7 +832,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
   { 0x40000000, 0xfc000000,	"beqz",		"r5:5,sb0:5|10:16<<2",		0,				0, 0, 0 },
   { 0x0,	0x0,		"bnez",		"r,la",				"bnez %1,%%b21(%2)",		0, 0, 0 },
   { 0x44000000, 0xfc000000,	"bnez",		"r5:5,sb0:5|10:16<<2",		0,				0, 0, 0 },
-  { 0x4c000000, 0xfc000000,	"jirl",		"r0:5,r5:5,s10:16<<2",		0,				0, 0, 0 },
+  { 0x4c000000, 0xfc000000,	"jirl",		"r0:5,r5:5,so10:16<<2",		0,				0, 0, 0 },
   { 0x0,	0x0,		"b",		"la",				"b %%b26(%1)",			0, 0, 0 },
   { 0x50000000, 0xfc000000,	"b",		"sb0:10|10:16<<2",		0,				0, 0, 0 },
   { 0x0,	0x0,		"bl",		"la",				"bl %%b26(%1)",			0, 0, 0 },
-- 
2.39.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v4 5/6] opcodes/loongarch: do not print hex notation for signed immediates
  2023-02-15 18:02 [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks WANG Xuerui
                   ` (3 preceding siblings ...)
  2023-02-15 18:03 ` [PATCH v4 4/6] opcodes/loongarch: style disassembled address offsets as such WANG Xuerui
@ 2023-02-15 18:03 ` WANG Xuerui
  2023-02-15 18:03 ` [PATCH v4 6/6] opcodes/loongarch: print unrecognized insn words with the .word directive WANG Xuerui
  2023-03-02  9:23 ` [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks mengqinggang
  6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-02-15 18:03 UTC (permalink / raw)
  To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Xi Ruoyao, WANG Xuerui

From: WANG Xuerui <git@xen0n.name>

The additional hex notation was minimally useful when one had to
inspect code with heavy bit manipulation, or of unclear signedness, but
it clutters the output, and the style is not regular assembly language
syntax either.

Precisely how one approaches the original use case is not taken care of
in this patch (maybe we want a disassembler option forcing a certain
style for immediates, like for example printing every immediate in
decimal or hexadecimal notation), but at least let's stop the current
practice that does little good in hindsight.
---
 gas/testsuite/gas/loongarch/imm_ins.d       | 82 ++++++++++-----------
 gas/testsuite/gas/loongarch/imm_ins_32.d    | 52 ++++++-------
 gas/testsuite/gas/loongarch/imm_op.d        | 44 +++++------
 gas/testsuite/gas/loongarch/jmp_op.d        | 38 +++++-----
 gas/testsuite/gas/loongarch/load_store_op.d | 80 ++++++++++----------
 gas/testsuite/gas/loongarch/macro_op.d      |  4 +-
 gas/testsuite/gas/loongarch/macro_op_32.d   |  4 +-
 gas/testsuite/gas/loongarch/privilege_op.d  |  8 +-
 ld/testsuite/ld-loongarch-elf/jmp_op.d      | 38 +++++-----
 ld/testsuite/ld-loongarch-elf/macro_op.d    |  4 +-
 opcodes/loongarch-dis.c                     |  8 +-
 11 files changed, 178 insertions(+), 184 deletions(-)

diff --git a/gas/testsuite/gas/loongarch/imm_ins.d b/gas/testsuite/gas/loongarch/imm_ins.d
index c588b5e0e25..f00110cd8a3 100644
--- a/gas/testsuite/gas/loongarch/imm_ins.d
+++ b/gas/testsuite/gas/loongarch/imm_ins.d
@@ -9,10 +9,10 @@ Disassembly of section .text:
 
 00000000.* <.text>:
 [ 	]+0:[ 	]+03848c0c[ 	]+li.w[ 	]+\$t0,[ 	]+0x123
-[ 	]+4:[ 	]+15ffe00d[ 	]+lu12i.w[ 	]+\$t1,[ 	]+-256\(0xfff00\)
-[ 	]+8:[ 	]+16001fed[ 	]+lu32i.d[ 	]+\$t1,[ 	]+255\(0xff\)
-[ 	]+c:[ 	]+02bffc0e[ 	]+li.w[ 	]+\$t2,[ 	]+-1\(0xfff\)
-[ 	]+10:[ 	]+1601ffee[ 	]+lu32i.d[ 	]+\$t2,[ 	]+4095\(0xfff\)
+[ 	]+4:[ 	]+15ffe00d[ 	]+lu12i.w[ 	]+\$t1,[ 	]+-256
+[ 	]+8:[ 	]+16001fed[ 	]+lu32i.d[ 	]+\$t1,[ 	]+255
+[ 	]+c:[ 	]+02bffc0e[ 	]+li.w[ 	]+\$t2,[ 	]+-1
+[ 	]+10:[ 	]+1601ffee[ 	]+lu32i.d[ 	]+\$t2,[ 	]+4095
 [ 	]+14:[ 	]+0004b58b[ 	]+alsl.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+18:[ 	]+0006b58b[ 	]+alsl.wu[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+1c:[ 	]+0009358b[ 	]+bytepick.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
@@ -31,50 +31,50 @@ Disassembly of section .text:
 [ 	]+50:[ 	]+008209ac[ 	]+bstrins.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2,[ 	]+0x2
 [ 	]+54:[ 	]+00c209ac[ 	]+bstrpick.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2,[ 	]+0x2
 [ 	]+58:[ 	]+00c209ac[ 	]+bstrpick.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2,[ 	]+0x2
-[ 	]+5c:[ 	]+02048dac[ 	]+slti[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
-[ 	]+60:[ 	]+02448dac[ 	]+sltui[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
-[ 	]+64:[ 	]+02848dac[ 	]+addi.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
-[ 	]+68:[ 	]+02c48dac[ 	]+addi.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
-[ 	]+6c:[ 	]+03048dac[ 	]+lu52i.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
+[ 	]+5c:[ 	]+02048dac[ 	]+slti[ 	]+\$t0,[ 	]+\$t1,[ 	]+291
+[ 	]+60:[ 	]+02448dac[ 	]+sltui[ 	]+\$t0,[ 	]+\$t1,[ 	]+291
+[ 	]+64:[ 	]+02848dac[ 	]+addi.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+291
+[ 	]+68:[ 	]+02c48dac[ 	]+addi.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+291
+[ 	]+6c:[ 	]+03048dac[ 	]+lu52i.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+291
 [ 	]+70:[ 	]+034009ac[ 	]+andi[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+74:[ 	]+038009ac[ 	]+ori[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+78:[ 	]+03c009ac[ 	]+xori[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
-[ 	]+7c:[ 	]+100009ac[ 	]+addu16i.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+2\(0x2\)
-[ 	]+80:[ 	]+1400246c[ 	]+lu12i.w[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+84:[ 	]+1600246c[ 	]+lu32i.d[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+88:[ 	]+1800246c[ 	]+pcaddi[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+8c:[ 	]+1a00246c[ 	]+pcalau12i[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+90:[ 	]+1c00246c[ 	]+pcaddu12i[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+94:[ 	]+1e00246c[ 	]+pcaddu18i[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+7c:[ 	]+100009ac[ 	]+addu16i.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+2
+[ 	]+80:[ 	]+1400246c[ 	]+lu12i.w[ 	]+\$t0,[ 	]+291
+[ 	]+84:[ 	]+1600246c[ 	]+lu32i.d[ 	]+\$t0,[ 	]+291
+[ 	]+88:[ 	]+1800246c[ 	]+pcaddi[ 	]+\$t0,[ 	]+291
+[ 	]+8c:[ 	]+1a00246c[ 	]+pcalau12i[ 	]+\$t0,[ 	]+291
+[ 	]+90:[ 	]+1c00246c[ 	]+pcaddu12i[ 	]+\$t0,[ 	]+291
+[ 	]+94:[ 	]+1e00246c[ 	]+pcaddu18i[ 	]+\$t0,[ 	]+291
 [ 	]+98:[ 	]+04048c0c[ 	]+csrrd[ 	]+\$t0,[ 	]+0x123
 [ 	]+9c:[ 	]+04048c2c[ 	]+csrwr[ 	]+\$t0,[ 	]+0x123
 [ 	]+a0:[ 	]+040009ac[ 	]+csrxchg[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
-[ 	]+a4:[ 	]+060009a2[ 	]+cacop[ 	]+0x2,[ 	]+\$t1,[ 	]+2\(0x2\)
+[ 	]+a4:[ 	]+060009a2[ 	]+cacop[ 	]+0x2,[ 	]+\$t1,[ 	]+2
 [ 	]+a8:[ 	]+064009ac[ 	]+lddir[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+ac:[ 	]+06440980[ 	]+ldpte[ 	]+\$t0,[ 	]+0x2
 [ 	]+b0:[ 	]+0649b9a2[ 	]+invtlb[ 	]+0x2,[ 	]+\$t1,[ 	]+\$t2
-[ 	]+b4:[ 	]+200101ac[ 	]+ll.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+b8:[ 	]+210101ac[ 	]+sc.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+bc:[ 	]+220101ac[ 	]+ll.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+c0:[ 	]+230101ac[ 	]+sc.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+c4:[ 	]+240101ac[ 	]+ldptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+c8:[ 	]+250101ac[ 	]+stptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+cc:[ 	]+260101ac[ 	]+ldptr.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+d0:[ 	]+270101ac[ 	]+stptr.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+d4:[ 	]+280401ac[ 	]+ld.b[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+d8:[ 	]+284401ac[ 	]+ld.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+dc:[ 	]+288401ac[ 	]+ld.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+e0:[ 	]+28c401ac[ 	]+ld.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+e4:[ 	]+290401ac[ 	]+st.b[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+e8:[ 	]+294401ac[ 	]+st.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+ec:[ 	]+298401ac[ 	]+st.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+f0:[ 	]+29c401ac[ 	]+st.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+f4:[ 	]+2a0401ac[ 	]+ld.bu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+f8:[ 	]+2a4401ac[ 	]+ld.hu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+fc:[ 	]+2a8401ac[ 	]+ld.wu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+100:[ 	]+2ac401a2[ 	]+preld[ 	]+0x2,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+b4:[ 	]+200101ac[ 	]+ll.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+b8:[ 	]+210101ac[ 	]+sc.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+bc:[ 	]+220101ac[ 	]+ll.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+c0:[ 	]+230101ac[ 	]+sc.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+c4:[ 	]+240101ac[ 	]+ldptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+c8:[ 	]+250101ac[ 	]+stptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+cc:[ 	]+260101ac[ 	]+ldptr.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+d0:[ 	]+270101ac[ 	]+stptr.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+d4:[ 	]+280401ac[ 	]+ld.b[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+d8:[ 	]+284401ac[ 	]+ld.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+dc:[ 	]+288401ac[ 	]+ld.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+e0:[ 	]+28c401ac[ 	]+ld.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+e4:[ 	]+290401ac[ 	]+st.b[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+e8:[ 	]+294401ac[ 	]+st.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+ec:[ 	]+298401ac[ 	]+st.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+f0:[ 	]+29c401ac[ 	]+st.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+f4:[ 	]+2a0401ac[ 	]+ld.bu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+f8:[ 	]+2a4401ac[ 	]+ld.hu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+fc:[ 	]+2a8401ac[ 	]+ld.wu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+100:[ 	]+2ac401a2[ 	]+preld[ 	]+0x2,[ 	]+\$t1,[ 	]+256
 [ 	]+104:[ 	]+382c39a2[ 	]+preldx[ 	]+0x2,[ 	]+\$t1,[ 	]+\$t2
-[ 	]+108:[ 	]+2b048d8a[ 	]+fld.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+10c:[ 	]+2b448d8a[ 	]+fst.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+110:[ 	]+2b848d8a[ 	]+fld.d[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+114:[ 	]+2bc48d8a[ 	]+fst.d[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+108:[ 	]+2b048d8a[ 	]+fld.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291
+[ 	]+10c:[ 	]+2b448d8a[ 	]+fst.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291
+[ 	]+110:[ 	]+2b848d8a[ 	]+fld.d[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291
+[ 	]+114:[ 	]+2bc48d8a[ 	]+fst.d[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291
diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.d b/gas/testsuite/gas/loongarch/imm_ins_32.d
index 5fd5835a342..dc2eeb9ed51 100644
--- a/gas/testsuite/gas/loongarch/imm_ins_32.d
+++ b/gas/testsuite/gas/loongarch/imm_ins_32.d
@@ -19,39 +19,39 @@ Disassembly of section .text:
 [ 	]+20:[ 	]+0044898b[ 	]+srli.w[ 	]+\$a7,[ 	]+\$t0,[ 	]+0x2
 [ 	]+24:[ 	]+004889ac[ 	]+srai.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+28:[ 	]+006209ac[ 	]+bstrins.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2,[ 	]+0x2
-[ 	]+2c:[ 	]+02048dac[ 	]+slti[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
-[ 	]+30:[ 	]+02448dac[ 	]+sltui[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
-[ 	]+34:[ 	]+02848dac[ 	]+addi.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+291\(0x123\)
+[ 	]+2c:[ 	]+02048dac[ 	]+slti[ 	]+\$t0,[ 	]+\$t1,[ 	]+291
+[ 	]+30:[ 	]+02448dac[ 	]+sltui[ 	]+\$t0,[ 	]+\$t1,[ 	]+291
+[ 	]+34:[ 	]+02848dac[ 	]+addi.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+291
 [ 	]+38:[ 	]+034009ac[ 	]+andi[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+3c:[ 	]+038009ac[ 	]+ori[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+40:[ 	]+03c009ac[ 	]+xori[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
-[ 	]+44:[ 	]+1400246c[ 	]+lu12i.w[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+48:[ 	]+1800246c[ 	]+pcaddi[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+4c:[ 	]+1a00246c[ 	]+pcalau12i[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+50:[ 	]+1c00246c[ 	]+pcaddu12i[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+54:[ 	]+1e00246c[ 	]+pcaddu18i[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+44:[ 	]+1400246c[ 	]+lu12i.w[ 	]+\$t0,[ 	]+291
+[ 	]+48:[ 	]+1800246c[ 	]+pcaddi[ 	]+\$t0,[ 	]+291
+[ 	]+4c:[ 	]+1a00246c[ 	]+pcalau12i[ 	]+\$t0,[ 	]+291
+[ 	]+50:[ 	]+1c00246c[ 	]+pcaddu12i[ 	]+\$t0,[ 	]+291
+[ 	]+54:[ 	]+1e00246c[ 	]+pcaddu18i[ 	]+\$t0,[ 	]+291
 [ 	]+58:[ 	]+04048c0c[ 	]+csrrd[ 	]+\$t0,[ 	]+0x123
 [ 	]+5c:[ 	]+04048c2c[ 	]+csrwr[ 	]+\$t0,[ 	]+0x123
 [ 	]+60:[ 	]+040009ac[ 	]+csrxchg[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
-[ 	]+64:[ 	]+060009a2[ 	]+cacop[ 	]+0x2,[ 	]+\$t1,[ 	]+2\(0x2\)
+[ 	]+64:[ 	]+060009a2[ 	]+cacop[ 	]+0x2,[ 	]+\$t1,[ 	]+2
 [ 	]+68:[ 	]+064009ac[ 	]+lddir[ 	]+\$t0,[ 	]+\$t1,[ 	]+0x2
 [ 	]+6c:[ 	]+06440980[ 	]+ldpte[ 	]+\$t0,[ 	]+0x2
 [ 	]+70:[ 	]+0649b9a2[ 	]+invtlb[ 	]+0x2,[ 	]+\$t1,[ 	]+\$t2
-[ 	]+74:[ 	]+200101ac[ 	]+ll.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+78:[ 	]+210101ac[ 	]+sc.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+7c:[ 	]+220101ac[ 	]+ll.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+80:[ 	]+230101ac[ 	]+sc.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+84:[ 	]+240101ac[ 	]+ldptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+88:[ 	]+250101ac[ 	]+stptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+8c:[ 	]+284401ac[ 	]+ld.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+90:[ 	]+288401ac[ 	]+ld.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+94:[ 	]+290401ac[ 	]+st.b[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+98:[ 	]+294401ac[ 	]+st.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+9c:[ 	]+298401ac[ 	]+st.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+a0:[ 	]+2a0401ac[ 	]+ld.bu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+a4:[ 	]+2a4401ac[ 	]+ld.hu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+a8:[ 	]+2a8401ac[ 	]+ld.wu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256\(0x100\)
-[ 	]+ac:[ 	]+2ac401a2[ 	]+preld[ 	]+0x2,[ 	]+\$t1,[ 	]+256\(0x100\)
+[ 	]+74:[ 	]+200101ac[ 	]+ll.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+78:[ 	]+210101ac[ 	]+sc.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+7c:[ 	]+220101ac[ 	]+ll.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+80:[ 	]+230101ac[ 	]+sc.d[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+84:[ 	]+240101ac[ 	]+ldptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+88:[ 	]+250101ac[ 	]+stptr.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+8c:[ 	]+284401ac[ 	]+ld.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+90:[ 	]+288401ac[ 	]+ld.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+94:[ 	]+290401ac[ 	]+st.b[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+98:[ 	]+294401ac[ 	]+st.h[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+9c:[ 	]+298401ac[ 	]+st.w[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+a0:[ 	]+2a0401ac[ 	]+ld.bu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+a4:[ 	]+2a4401ac[ 	]+ld.hu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+a8:[ 	]+2a8401ac[ 	]+ld.wu[ 	]+\$t0,[ 	]+\$t1,[ 	]+256
+[ 	]+ac:[ 	]+2ac401a2[ 	]+preld[ 	]+0x2,[ 	]+\$t1,[ 	]+256
 [ 	]+b0:[ 	]+382c39a2[ 	]+preldx[ 	]+0x2,[ 	]+\$t1,[ 	]+\$t2
-[ 	]+b4:[ 	]+2b048d8a[ 	]+fld.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
-[ 	]+b8:[ 	]+2b448d8a[ 	]+fst.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291\(0x123\)
+[ 	]+b4:[ 	]+2b048d8a[ 	]+fld.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291
+[ 	]+b8:[ 	]+2b448d8a[ 	]+fst.s[ 	]+\$ft2,[ 	]+\$t0,[ 	]+291
diff --git a/gas/testsuite/gas/loongarch/imm_op.d b/gas/testsuite/gas/loongarch/imm_op.d
index a017aaf5bf7..3d4cba45586 100644
--- a/gas/testsuite/gas/loongarch/imm_op.d
+++ b/gas/testsuite/gas/loongarch/imm_op.d
@@ -8,20 +8,20 @@ Disassembly of section .text:
 
 00000000.* <.text>:
 [ 	]+0:[ 	]+020000a4 [ 	]+slti[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+4:[ 	]+021ffca4 [ 	]+slti[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+8:[ 	]+022004a4 [ 	]+slti[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+4:[ 	]+021ffca4 [ 	]+slti[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+8:[ 	]+022004a4 [ 	]+slti[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+c:[ 	]+024000a4 [ 	]+sltui[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+10:[ 	]+025ffca4 [ 	]+sltui[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+14:[ 	]+026004a4 [ 	]+sltui[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+10:[ 	]+025ffca4 [ 	]+sltui[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+14:[ 	]+026004a4 [ 	]+sltui[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+18:[ 	]+028000a4 [ 	]+addi.w[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+1c:[ 	]+029ffca4 [ 	]+addi.w[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+20:[ 	]+02a004a4 [ 	]+addi.w[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+1c:[ 	]+029ffca4 [ 	]+addi.w[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+20:[ 	]+02a004a4 [ 	]+addi.w[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+24:[ 	]+02c000a4 [ 	]+addi.d[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+28:[ 	]+02dffca4 [ 	]+addi.d[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+2c:[ 	]+02e004a4 [ 	]+addi.d[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+28:[ 	]+02dffca4 [ 	]+addi.d[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+2c:[ 	]+02e004a4 [ 	]+addi.d[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+30:[ 	]+030000a4 [ 	]+lu52i.d[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+34:[ 	]+031ffca4 [ 	]+lu52i.d[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+38:[ 	]+032004a4 [ 	]+lu52i.d[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+34:[ 	]+031ffca4 [ 	]+lu52i.d[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+38:[ 	]+032004a4 [ 	]+lu52i.d[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+3c:[ 	]+034000a4 [ 	]+andi[ 	]+[ 	]+\$a0, \$a1, 0x0
 [ 	]+40:[ 	]+035ffca4 [ 	]+andi[ 	]+[ 	]+\$a0, \$a1, 0x7ff
 [ 	]+44:[ 	]+038000a4 [ 	]+ori[ 	]+[ 	]+\$a0, \$a1, 0x0
@@ -29,20 +29,20 @@ Disassembly of section .text:
 [ 	]+4c:[ 	]+03c000a4 [ 	]+xori[ 	]+[ 	]+\$a0, \$a1, 0x0
 [ 	]+50:[ 	]+03dffca4 [ 	]+xori[ 	]+[ 	]+\$a0, \$a1, 0x7ff
 [ 	]+54:[ 	]+100000a4 [ 	]+addu16i.d[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+58:[ 	]+11fffca4 [ 	]+addu16i.d[ 	]+[ 	]+\$a0, \$a1, 32767\(0x7fff\)
-[ 	]+5c:[ 	]+120004a4 [ 	]+addu16i.d[ 	]+[ 	]+\$a0, \$a1, -32767\(0x8001\)
+[ 	]+58:[ 	]+11fffca4 [ 	]+addu16i.d[ 	]+[ 	]+\$a0, \$a1, 32767
+[ 	]+5c:[ 	]+120004a4 [ 	]+addu16i.d[ 	]+[ 	]+\$a0, \$a1, -32767
 [ 	]+60:[ 	]+14000004 [ 	]+lu12i.w[ 	]+[ 	]+\$a0, 0
-[ 	]+64:[ 	]+14ffffe4 [ 	]+lu12i.w[ 	]+[ 	]+\$a0, 524287\(0x7ffff\)
-[ 	]+68:[ 	]+17000024 [ 	]+lu32i.d[ 	]+[ 	]+\$a0, -524287\(0x80001\)
+[ 	]+64:[ 	]+14ffffe4 [ 	]+lu12i.w[ 	]+[ 	]+\$a0, 524287
+[ 	]+68:[ 	]+17000024 [ 	]+lu32i.d[ 	]+[ 	]+\$a0, -524287
 [ 	]+6c:[ 	]+18000004 [ 	]+pcaddi[ 	]+[ 	]+\$a0, 0
-[ 	]+70:[ 	]+18ffffe4 [ 	]+pcaddi[ 	]+[ 	]+\$a0, 524287\(0x7ffff\)
-[ 	]+74:[ 	]+19000024 [ 	]+pcaddi[ 	]+[ 	]+\$a0, -524287\(0x80001\)
+[ 	]+70:[ 	]+18ffffe4 [ 	]+pcaddi[ 	]+[ 	]+\$a0, 524287
+[ 	]+74:[ 	]+19000024 [ 	]+pcaddi[ 	]+[ 	]+\$a0, -524287
 [ 	]+78:[ 	]+1a000004 [ 	]+pcalau12i[ 	]+[ 	]+\$a0, 0
-[ 	]+7c:[ 	]+1affffe4 [ 	]+pcalau12i[ 	]+[ 	]+\$a0, 524287\(0x7ffff\)
-[ 	]+80:[ 	]+1b000024 [ 	]+pcalau12i[ 	]+[ 	]+\$a0, -524287\(0x80001\)
+[ 	]+7c:[ 	]+1affffe4 [ 	]+pcalau12i[ 	]+[ 	]+\$a0, 524287
+[ 	]+80:[ 	]+1b000024 [ 	]+pcalau12i[ 	]+[ 	]+\$a0, -524287
 [ 	]+84:[ 	]+1c000004 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 0
-[ 	]+88:[ 	]+1cffffe4 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 524287\(0x7ffff\)
-[ 	]+8c:[ 	]+1d000024 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, -524287\(0x80001\)
+[ 	]+88:[ 	]+1cffffe4 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, 524287
+[ 	]+8c:[ 	]+1d000024 [ 	]+pcaddu12i[ 	]+[ 	]+\$a0, -524287
 [ 	]+90:[ 	]+1e000004 [ 	]+pcaddu18i[ 	]+[ 	]+\$a0, 0
-[ 	]+94:[ 	]+1effffe4 [ 	]+pcaddu18i[ 	]+[ 	]+\$a0, 524287\(0x7ffff\)
-[ 	]+98:[ 	]+1f000024 [ 	]+pcaddu18i[ 	]+[ 	]+\$a0, -524287\(0x80001\)
+[ 	]+94:[ 	]+1effffe4 [ 	]+pcaddu18i[ 	]+[ 	]+\$a0, 524287
+[ 	]+98:[ 	]+1f000024 [ 	]+pcaddu18i[ 	]+[ 	]+\$a0, -524287
diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loongarch/jmp_op.d
index e34660c2fd4..85512c42435 100644
--- a/gas/testsuite/gas/loongarch/jmp_op.d
+++ b/gas/testsuite/gas/loongarch/jmp_op.d
@@ -8,24 +8,24 @@ Disassembly of section .text:
 
 00000000.* <.text>:
 [ 	]+0:[ 	]+03400000[ 	]+[ 	]+nop[ 	]+
-[ 	]+4:[ 	]+63fffc04[ 	]+[ 	]+bgtz[ 	]+\$a0, -4\(0x3fffc\)[ 	]+# 0x0
-[ 	]+8:[ 	]+67fff880[ 	]+[ 	]+bgez[ 	]+\$a0, -8\(0x3fff8\)[ 	]+# 0x0
-[ 	]+c:[ 	]+67fff404[ 	]+[ 	]+blez[ 	]+\$a0, -12\(0x3fff4\)[ 	]+# 0x0
-[ 	]+10:[ 	]+43fff09f[ 	]+[ 	]+beqz[ 	]+\$a0, -16\(0x7ffff0\)[ 	]+# 0x0
-[ 	]+14:[ 	]+47ffec9f[ 	]+[ 	]+bnez[ 	]+\$a0, -20\(0x7fffec\)[ 	]+# 0x0
-[ 	]+18:[ 	]+4bffe81f[ 	]+[ 	]+bceqz[ 	]+\$fcc0, -24\(0x7fffe8\)[ 	]+# 0x0
-[ 	]+1c:[ 	]+4bffe51f[ 	]+[ 	]+bcnez[ 	]+\$fcc0, -28\(0x7fffe4\)[ 	]+# 0x0
+[ 	]+4:[ 	]+63fffc04[ 	]+[ 	]+bgtz[ 	]+\$a0, -4[ 	]+# 0x0
+[ 	]+8:[ 	]+67fff880[ 	]+[ 	]+bgez[ 	]+\$a0, -8[ 	]+# 0x0
+[ 	]+c:[ 	]+67fff404[ 	]+[ 	]+blez[ 	]+\$a0, -12[ 	]+# 0x0
+[ 	]+10:[ 	]+43fff09f[ 	]+[ 	]+beqz[ 	]+\$a0, -16[ 	]+# 0x0
+[ 	]+14:[ 	]+47ffec9f[ 	]+[ 	]+bnez[ 	]+\$a0, -20[ 	]+# 0x0
+[ 	]+18:[ 	]+4bffe81f[ 	]+[ 	]+bceqz[ 	]+\$fcc0, -24[ 	]+# 0x0
+[ 	]+1c:[ 	]+4bffe51f[ 	]+[ 	]+bcnez[ 	]+\$fcc0, -28[ 	]+# 0x0
 [ 	]+20:[ 	]+4c000080[ 	]+[ 	]+jr[ 	]+\$a0
-[ 	]+24:[ 	]+53ffdfff[ 	]+[ 	]+b[ 	]+-36\(0xfffffdc\)[ 	]+# 0x0
-[ 	]+28:[ 	]+57ffdbff[ 	]+[ 	]+bl[ 	]+-40\(0xfffffd8\)[ 	]+# 0x0
-[ 	]+2c:[ 	]+5bffd485[ 	]+[ 	]+beq[ 	]+\$a0, \$a1, -44\(0x3ffd4\)[ 	]+# 0x0
-[ 	]+30:[ 	]+5fffd085[ 	]+[ 	]+bne[ 	]+\$a0, \$a1, -48\(0x3ffd0\)[ 	]+# 0x0
-[ 	]+34:[ 	]+63ffcc85[ 	]+[ 	]+blt[ 	]+\$a0, \$a1, -52\(0x3ffcc\)[ 	]+# 0x0
-[ 	]+38:[ 	]+63ffc8a4[ 	]+[ 	]+blt[ 	]+\$a1, \$a0, -56\(0x3ffc8\)[ 	]+# 0x0
-[ 	]+3c:[ 	]+67ffc485[ 	]+[ 	]+bge[ 	]+\$a0, \$a1, -60\(0x3ffc4\)[ 	]+# 0x0
-[ 	]+40:[ 	]+67ffc0a4[ 	]+[ 	]+bge[ 	]+\$a1, \$a0, -64\(0x3ffc0\)[ 	]+# 0x0
-[ 	]+44:[ 	]+6bffbc85[ 	]+[ 	]+bltu[ 	]+\$a0, \$a1, -68\(0x3ffbc\)[ 	]+# 0x0
-[ 	]+48:[ 	]+6bffb8a4[ 	]+[ 	]+bltu[ 	]+\$a1, \$a0, -72\(0x3ffb8\)[ 	]+# 0x0
-[ 	]+4c:[ 	]+6fffb485[ 	]+[ 	]+bgeu[ 	]+\$a0, \$a1, -76\(0x3ffb4\)[ 	]+# 0x0
-[ 	]+50:[ 	]+6fffb0a4[ 	]+[ 	]+bgeu[ 	]+\$a1, \$a0, -80\(0x3ffb0\)[ 	]+# 0x0
+[ 	]+24:[ 	]+53ffdfff[ 	]+[ 	]+b[ 	]+-36[ 	]+# 0x0
+[ 	]+28:[ 	]+57ffdbff[ 	]+[ 	]+bl[ 	]+-40[ 	]+# 0x0
+[ 	]+2c:[ 	]+5bffd485[ 	]+[ 	]+beq[ 	]+\$a0, \$a1, -44[ 	]+# 0x0
+[ 	]+30:[ 	]+5fffd085[ 	]+[ 	]+bne[ 	]+\$a0, \$a1, -48[ 	]+# 0x0
+[ 	]+34:[ 	]+63ffcc85[ 	]+[ 	]+blt[ 	]+\$a0, \$a1, -52[ 	]+# 0x0
+[ 	]+38:[ 	]+63ffc8a4[ 	]+[ 	]+blt[ 	]+\$a1, \$a0, -56[ 	]+# 0x0
+[ 	]+3c:[ 	]+67ffc485[ 	]+[ 	]+bge[ 	]+\$a0, \$a1, -60[ 	]+# 0x0
+[ 	]+40:[ 	]+67ffc0a4[ 	]+[ 	]+bge[ 	]+\$a1, \$a0, -64[ 	]+# 0x0
+[ 	]+44:[ 	]+6bffbc85[ 	]+[ 	]+bltu[ 	]+\$a0, \$a1, -68[ 	]+# 0x0
+[ 	]+48:[ 	]+6bffb8a4[ 	]+[ 	]+bltu[ 	]+\$a1, \$a0, -72[ 	]+# 0x0
+[ 	]+4c:[ 	]+6fffb485[ 	]+[ 	]+bgeu[ 	]+\$a0, \$a1, -76[ 	]+# 0x0
+[ 	]+50:[ 	]+6fffb0a4[ 	]+[ 	]+bgeu[ 	]+\$a1, \$a0, -80[ 	]+# 0x0
 [ 	]+54:[ 	]+4c000020[ 	]+[ 	]+ret[ 	]+
diff --git a/gas/testsuite/gas/loongarch/load_store_op.d b/gas/testsuite/gas/loongarch/load_store_op.d
index fc15773c1f4..e1b4dea1851 100644
--- a/gas/testsuite/gas/loongarch/load_store_op.d
+++ b/gas/testsuite/gas/loongarch/load_store_op.d
@@ -8,69 +8,69 @@ Disassembly of section .text:
 
 00000000.* <.text>:
 [ 	]+0:[ 	]+200000a4 [ 	]+ll.w[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+4:[ 	]+203ffca4 [ 	]+ll.w[ 	]+[ 	]+\$a0, \$a1, 16380\(0x3ffc\)
+[ 	]+4:[ 	]+203ffca4 [ 	]+ll.w[ 	]+[ 	]+\$a0, \$a1, 16380
 [ 	]+8:[ 	]+210000a4 [ 	]+sc.w[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+c:[ 	]+213ffca4 [ 	]+sc.w[ 	]+[ 	]+\$a0, \$a1, 16380\(0x3ffc\)
+[ 	]+c:[ 	]+213ffca4 [ 	]+sc.w[ 	]+[ 	]+\$a0, \$a1, 16380
 [ 	]+10:[ 	]+220000a4 [ 	]+ll.d[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+14:[ 	]+223ffca4 [ 	]+ll.d[ 	]+[ 	]+\$a0, \$a1, 16380\(0x3ffc\)
+[ 	]+14:[ 	]+223ffca4 [ 	]+ll.d[ 	]+[ 	]+\$a0, \$a1, 16380
 [ 	]+18:[ 	]+230000a4 [ 	]+sc.d[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+1c:[ 	]+233ffca4 [ 	]+sc.d[ 	]+[ 	]+\$a0, \$a1, 16380\(0x3ffc\)
+[ 	]+1c:[ 	]+233ffca4 [ 	]+sc.d[ 	]+[ 	]+\$a0, \$a1, 16380
 [ 	]+20:[ 	]+240000a4 [ 	]+ldptr.w[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+24:[ 	]+243ffca4 [ 	]+ldptr.w[ 	]+[ 	]+\$a0, \$a1, 16380\(0x3ffc\)
+[ 	]+24:[ 	]+243ffca4 [ 	]+ldptr.w[ 	]+[ 	]+\$a0, \$a1, 16380
 [ 	]+28:[ 	]+250000a4 [ 	]+stptr.w[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+2c:[ 	]+253ffca4 [ 	]+stptr.w[ 	]+[ 	]+\$a0, \$a1, 16380\(0x3ffc\)
+[ 	]+2c:[ 	]+253ffca4 [ 	]+stptr.w[ 	]+[ 	]+\$a0, \$a1, 16380
 [ 	]+30:[ 	]+260000a4 [ 	]+ldptr.d[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+34:[ 	]+263ffca4 [ 	]+ldptr.d[ 	]+[ 	]+\$a0, \$a1, 16380\(0x3ffc\)
+[ 	]+34:[ 	]+263ffca4 [ 	]+ldptr.d[ 	]+[ 	]+\$a0, \$a1, 16380
 [ 	]+38:[ 	]+270000a4 [ 	]+stptr.d[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+3c:[ 	]+273ffca4 [ 	]+stptr.d[ 	]+[ 	]+\$a0, \$a1, 16380\(0x3ffc\)
+[ 	]+3c:[ 	]+273ffca4 [ 	]+stptr.d[ 	]+[ 	]+\$a0, \$a1, 16380
 [ 	]+40:[ 	]+280000a4 [ 	]+ld.b[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+44:[ 	]+281ffca4 [ 	]+ld.b[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+48:[ 	]+282004a4 [ 	]+ld.b[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+44:[ 	]+281ffca4 [ 	]+ld.b[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+48:[ 	]+282004a4 [ 	]+ld.b[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+4c:[ 	]+284000a4 [ 	]+ld.h[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+50:[ 	]+285ffca4 [ 	]+ld.h[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+54:[ 	]+286004a4 [ 	]+ld.h[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+50:[ 	]+285ffca4 [ 	]+ld.h[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+54:[ 	]+286004a4 [ 	]+ld.h[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+58:[ 	]+288000a4 [ 	]+ld.w[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+5c:[ 	]+289ffca4 [ 	]+ld.w[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+60:[ 	]+28a004a4 [ 	]+ld.w[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+5c:[ 	]+289ffca4 [ 	]+ld.w[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+60:[ 	]+28a004a4 [ 	]+ld.w[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+64:[ 	]+28c000a4 [ 	]+ld.d[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+68:[ 	]+28dffca4 [ 	]+ld.d[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+6c:[ 	]+28e004a4 [ 	]+ld.d[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+68:[ 	]+28dffca4 [ 	]+ld.d[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+6c:[ 	]+28e004a4 [ 	]+ld.d[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+70:[ 	]+290000a4 [ 	]+st.b[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+74:[ 	]+291ffca4 [ 	]+st.b[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+78:[ 	]+292004a4 [ 	]+st.b[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+74:[ 	]+291ffca4 [ 	]+st.b[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+78:[ 	]+292004a4 [ 	]+st.b[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+7c:[ 	]+294000a4 [ 	]+st.h[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+80:[ 	]+295ffca4 [ 	]+st.h[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+84:[ 	]+296004a4 [ 	]+st.h[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+80:[ 	]+295ffca4 [ 	]+st.h[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+84:[ 	]+296004a4 [ 	]+st.h[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+88:[ 	]+298000a4 [ 	]+st.w[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+8c:[ 	]+299ffca4 [ 	]+st.w[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+90:[ 	]+29a004a4 [ 	]+st.w[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+8c:[ 	]+299ffca4 [ 	]+st.w[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+90:[ 	]+29a004a4 [ 	]+st.w[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+94:[ 	]+29c000a4 [ 	]+st.d[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+98:[ 	]+29dffca4 [ 	]+st.d[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+9c:[ 	]+29e004a4 [ 	]+st.d[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+98:[ 	]+29dffca4 [ 	]+st.d[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+9c:[ 	]+29e004a4 [ 	]+st.d[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+a0:[ 	]+2a0000a4 [ 	]+ld.bu[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+a4:[ 	]+2a1ffca4 [ 	]+ld.bu[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+a8:[ 	]+2a2004a4 [ 	]+ld.bu[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+a4:[ 	]+2a1ffca4 [ 	]+ld.bu[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+a8:[ 	]+2a2004a4 [ 	]+ld.bu[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+ac:[ 	]+2a4000a4 [ 	]+ld.hu[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+b0:[ 	]+2a5ffca4 [ 	]+ld.hu[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+b4:[ 	]+2a6004a4 [ 	]+ld.hu[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+b0:[ 	]+2a5ffca4 [ 	]+ld.hu[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+b4:[ 	]+2a6004a4 [ 	]+ld.hu[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+b8:[ 	]+2a8000a4 [ 	]+ld.wu[ 	]+[ 	]+\$a0, \$a1, 0
-[ 	]+bc:[ 	]+2a9ffca4 [ 	]+ld.wu[ 	]+[ 	]+\$a0, \$a1, 2047\(0x7ff\)
-[ 	]+c0:[ 	]+2aa004a4 [ 	]+ld.wu[ 	]+[ 	]+\$a0, \$a1, -2047\(0x801\)
+[ 	]+bc:[ 	]+2a9ffca4 [ 	]+ld.wu[ 	]+[ 	]+\$a0, \$a1, 2047
+[ 	]+c0:[ 	]+2aa004a4 [ 	]+ld.wu[ 	]+[ 	]+\$a0, \$a1, -2047
 [ 	]+c4:[ 	]+2ac000a0 [ 	]+preld[ 	]+[ 	]+0x0, \$a1, 0
-[ 	]+c8:[ 	]+2adffcbf [ 	]+preld[ 	]+[ 	]+0x1f, \$a1, 2047\(0x7ff\)
-[ 	]+cc:[ 	]+2ae004bf [ 	]+preld[ 	]+[ 	]+0x1f, \$a1, -2047\(0x801\)
+[ 	]+c8:[ 	]+2adffcbf [ 	]+preld[ 	]+[ 	]+0x1f, \$a1, 2047
+[ 	]+cc:[ 	]+2ae004bf [ 	]+preld[ 	]+[ 	]+0x1f, \$a1, -2047
 [ 	]+d0:[ 	]+2b0000a0 [ 	]+fld.s[ 	]+[ 	]+\$fa0, \$a1, 0
-[ 	]+d4:[ 	]+2b1ffca0 [ 	]+fld.s[ 	]+[ 	]+\$fa0, \$a1, 2047\(0x7ff\)
-[ 	]+d8:[ 	]+2b2004a0 [ 	]+fld.s[ 	]+[ 	]+\$fa0, \$a1, -2047\(0x801\)
+[ 	]+d4:[ 	]+2b1ffca0 [ 	]+fld.s[ 	]+[ 	]+\$fa0, \$a1, 2047
+[ 	]+d8:[ 	]+2b2004a0 [ 	]+fld.s[ 	]+[ 	]+\$fa0, \$a1, -2047
 [ 	]+dc:[ 	]+2b4000a0 [ 	]+fst.s[ 	]+[ 	]+\$fa0, \$a1, 0
-[ 	]+e0:[ 	]+2b5ffca0 [ 	]+fst.s[ 	]+[ 	]+\$fa0, \$a1, 2047\(0x7ff\)
-[ 	]+e4:[ 	]+2b6004a0 [ 	]+fst.s[ 	]+[ 	]+\$fa0, \$a1, -2047\(0x801\)
+[ 	]+e0:[ 	]+2b5ffca0 [ 	]+fst.s[ 	]+[ 	]+\$fa0, \$a1, 2047
+[ 	]+e4:[ 	]+2b6004a0 [ 	]+fst.s[ 	]+[ 	]+\$fa0, \$a1, -2047
 [ 	]+e8:[ 	]+2b8000a0 [ 	]+fld.d[ 	]+[ 	]+\$fa0, \$a1, 0
-[ 	]+ec:[ 	]+2b9ffca0 [ 	]+fld.d[ 	]+[ 	]+\$fa0, \$a1, 2047\(0x7ff\)
-[ 	]+f0:[ 	]+2ba004a0 [ 	]+fld.d[ 	]+[ 	]+\$fa0, \$a1, -2047\(0x801\)
+[ 	]+ec:[ 	]+2b9ffca0 [ 	]+fld.d[ 	]+[ 	]+\$fa0, \$a1, 2047
+[ 	]+f0:[ 	]+2ba004a0 [ 	]+fld.d[ 	]+[ 	]+\$fa0, \$a1, -2047
 [ 	]+f4:[ 	]+2bc000a0 [ 	]+fst.d[ 	]+[ 	]+\$fa0, \$a1, 0
-[ 	]+f8:[ 	]+2bdffca0 [ 	]+fst.d[ 	]+[ 	]+\$fa0, \$a1, 2047\(0x7ff\)
-[ 	]+fc:[ 	]+2be004a0 [ 	]+fst.d[ 	]+[ 	]+\$fa0, \$a1, -2047\(0x801\)
+[ 	]+f8:[ 	]+2bdffca0 [ 	]+fst.d[ 	]+[ 	]+\$fa0, \$a1, 2047
+[ 	]+fc:[ 	]+2be004a0 [ 	]+fst.d[ 	]+[ 	]+\$fa0, \$a1, -2047
  100:[ 	]+380018a4 [ 	]+ldx.b[ 	]+[ 	]+\$a0, \$a1, \$a2
  104:[ 	]+380418a4 [ 	]+ldx.h[ 	]+[ 	]+\$a0, \$a1, \$a2
  108:[ 	]+380818a4 [ 	]+ldx.w[ 	]+[ 	]+\$a0, \$a1, \$a2
diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d
index 7ffb3e7b9c6..8830b9d5f8f 100644
--- a/gas/testsuite/gas/loongarch/macro_op.d
+++ b/gas/testsuite/gas/loongarch/macro_op.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
 
 00000000.* <.text>:
 [ 	]+0:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+4:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1\(0xfff\)
+[ 	]+4:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1
 [ 	]+8:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+c:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1\(0xfff\)
+[ 	]+c:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1
 [ 	]+10:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+10:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
 [ 	]+14:[ 	]+28c00084[ 	]+ld.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d
index 145d852b2be..d1a652c0bcc 100644
--- a/gas/testsuite/gas/loongarch/macro_op_32.d
+++ b/gas/testsuite/gas/loongarch/macro_op_32.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
 
 00000000.* <.text>:
 [ 	]+0:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+4:[ 	]+02bffc04[ 	]+addi.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1\(0xfff\)
+[ 	]+4:[ 	]+02bffc04[ 	]+addi.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1
 [ 	]+8:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+c:[ 	]+02bffc04[ 	]+addi.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1\(0xfff\)
+[ 	]+c:[ 	]+02bffc04[ 	]+addi.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1
 [ 	]+10:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+10:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.text
 [ 	]+14:[ 	]+28800084[ 	]+ld.w[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
diff --git a/gas/testsuite/gas/loongarch/privilege_op.d b/gas/testsuite/gas/loongarch/privilege_op.d
index 12d4790a027..73925f21a37 100644
--- a/gas/testsuite/gas/loongarch/privilege_op.d
+++ b/gas/testsuite/gas/loongarch/privilege_op.d
@@ -15,10 +15,10 @@ Disassembly of section .text:
 [ 	]+14:[ 	]+04fffca4 [ 	]+csrxchg[ 	]+[ 	]+\$a0, \$a1, 0x3fff
 [ 	]+18:[ 	]+060000a0 [ 	]+cacop[ 	]+[ 	]+0x0, \$a1, 0
 [ 	]+1c:[ 	]+060000bf [ 	]+cacop[ 	]+[ 	]+0x1f, \$a1, 0
-[ 	]+20:[ 	]+061ffca0 [ 	]+cacop[ 	]+[ 	]+0x0, \$a1, 2047\(0x7ff\)
-[ 	]+24:[ 	]+061ffcbf [ 	]+cacop[ 	]+[ 	]+0x1f, \$a1, 2047\(0x7ff\)
-[ 	]+28:[ 	]+062004a0 [ 	]+cacop[ 	]+[ 	]+0x0, \$a1, -2047\(0x801\)
-[ 	]+2c:[ 	]+062004bf [ 	]+cacop[ 	]+[ 	]+0x1f, \$a1, -2047\(0x801\)
+[ 	]+20:[ 	]+061ffca0 [ 	]+cacop[ 	]+[ 	]+0x0, \$a1, 2047
+[ 	]+24:[ 	]+061ffcbf [ 	]+cacop[ 	]+[ 	]+0x1f, \$a1, 2047
+[ 	]+28:[ 	]+062004a0 [ 	]+cacop[ 	]+[ 	]+0x0, \$a1, -2047
+[ 	]+2c:[ 	]+062004bf [ 	]+cacop[ 	]+[ 	]+0x1f, \$a1, -2047
 [ 	]+30:[ 	]+064000a4 [ 	]+lddir[ 	]+[ 	]+\$a0, \$a1, 0x0
 [ 	]+34:[ 	]+0643fca4 [ 	]+lddir[ 	]+[ 	]+\$a0, \$a1, 0xff
 [ 	]+38:[ 	]+064400a0 [ 	]+ldpte[ 	]+[ 	]+\$a1, 0x0
diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d
index d646c75fce0..17410aba21a 100644
--- a/ld/testsuite/ld-loongarch-elf/jmp_op.d
+++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d
@@ -8,24 +8,24 @@ Disassembly of section .text:
 
 00000000.* <.text>:
 [ 	]+0:[ 	]+03400000[ 	]+[ 	]+andi[ 	]+\$zero, \$zero, 0x0
-[ 	]+4:[ 	]+63fffc04[ 	]+[ 	]+blt[ 	]+\$zero, \$a0, -4\(0x3fffc\)[ 	]+# 0x0
-[ 	]+8:[ 	]+67fff880[ 	]+[ 	]+bge[ 	]+\$a0, \$zero, -8\(0x3fff8\)[ 	]+# 0x0
-[ 	]+c:[ 	]+67fff404[ 	]+[ 	]+bge[ 	]+\$zero, \$a0, -12\(0x3fff4\)[ 	]+# 0x0
-[ 	]+10:[ 	]+43fff09f[ 	]+[ 	]+beqz[ 	]+\$a0, -16\(0x7ffff0\)[ 	]+# 0x0
-[ 	]+14:[ 	]+47ffec9f[ 	]+[ 	]+bnez[ 	]+\$a0, -20\(0x7fffec\)[ 	]+# 0x0
-[ 	]+18:[ 	]+4bffe81f[ 	]+[ 	]+bceqz[ 	]+\$fcc0, -24\(0x7fffe8\)[ 	]+# 0x0
-[ 	]+1c:[ 	]+4bffe51f[ 	]+[ 	]+bcnez[ 	]+\$fcc0, -28\(0x7fffe4\)[ 	]+# 0x0
+[ 	]+4:[ 	]+63fffc04[ 	]+[ 	]+blt[ 	]+\$zero, \$a0, -4[ 	]+# 0x0
+[ 	]+8:[ 	]+67fff880[ 	]+[ 	]+bge[ 	]+\$a0, \$zero, -8[ 	]+# 0x0
+[ 	]+c:[ 	]+67fff404[ 	]+[ 	]+bge[ 	]+\$zero, \$a0, -12[ 	]+# 0x0
+[ 	]+10:[ 	]+43fff09f[ 	]+[ 	]+beqz[ 	]+\$a0, -16[ 	]+# 0x0
+[ 	]+14:[ 	]+47ffec9f[ 	]+[ 	]+bnez[ 	]+\$a0, -20[ 	]+# 0x0
+[ 	]+18:[ 	]+4bffe81f[ 	]+[ 	]+bceqz[ 	]+\$fcc0, -24[ 	]+# 0x0
+[ 	]+1c:[ 	]+4bffe51f[ 	]+[ 	]+bcnez[ 	]+\$fcc0, -28[ 	]+# 0x0
 [ 	]+20:[ 	]+4c000080[ 	]+[ 	]+jirl[ 	]+\$zero, \$a0, 0
-[ 	]+24:[ 	]+53ffdfff[ 	]+[ 	]+b[ 	]+-36\(0xfffffdc\)[ 	]+# 0x0
-[ 	]+28:[ 	]+57ffdbff[ 	]+[ 	]+bl[ 	]+-40\(0xfffffd8\)[ 	]+# 0x0
-[ 	]+2c:[ 	]+5bffd485[ 	]+[ 	]+beq[ 	]+\$a0, \$a1, -44\(0x3ffd4\)[ 	]+# 0x0
-[ 	]+30:[ 	]+5fffd085[ 	]+[ 	]+bne[ 	]+\$a0, \$a1, -48\(0x3ffd0\)[ 	]+# 0x0
-[ 	]+34:[ 	]+63ffcc85[ 	]+[ 	]+blt[ 	]+\$a0, \$a1, -52\(0x3ffcc\)[ 	]+# 0x0
-[ 	]+38:[ 	]+63ffc8a4[ 	]+[ 	]+blt[ 	]+\$a1, \$a0, -56\(0x3ffc8\)[ 	]+# 0x0
-[ 	]+3c:[ 	]+67ffc485[ 	]+[ 	]+bge[ 	]+\$a0, \$a1, -60\(0x3ffc4\)[ 	]+# 0x0
-[ 	]+40:[ 	]+67ffc0a4[ 	]+[ 	]+bge[ 	]+\$a1, \$a0, -64\(0x3ffc0\)[ 	]+# 0x0
-[ 	]+44:[ 	]+6bffbc85[ 	]+[ 	]+bltu[ 	]+\$a0, \$a1, -68\(0x3ffbc\)[ 	]+# 0x0
-[ 	]+48:[ 	]+6bffb8a4[ 	]+[ 	]+bltu[ 	]+\$a1, \$a0, -72\(0x3ffb8\)[ 	]+# 0x0
-[ 	]+4c:[ 	]+6fffb485[ 	]+[ 	]+bgeu[ 	]+\$a0, \$a1, -76\(0x3ffb4\)[ 	]+# 0x0
-[ 	]+50:[ 	]+6fffb0a4[ 	]+[ 	]+bgeu[ 	]+\$a1, \$a0, -80\(0x3ffb0\)[ 	]+# 0x0
+[ 	]+24:[ 	]+53ffdfff[ 	]+[ 	]+b[ 	]+-36[ 	]+# 0x0
+[ 	]+28:[ 	]+57ffdbff[ 	]+[ 	]+bl[ 	]+-40[ 	]+# 0x0
+[ 	]+2c:[ 	]+5bffd485[ 	]+[ 	]+beq[ 	]+\$a0, \$a1, -44[ 	]+# 0x0
+[ 	]+30:[ 	]+5fffd085[ 	]+[ 	]+bne[ 	]+\$a0, \$a1, -48[ 	]+# 0x0
+[ 	]+34:[ 	]+63ffcc85[ 	]+[ 	]+blt[ 	]+\$a0, \$a1, -52[ 	]+# 0x0
+[ 	]+38:[ 	]+63ffc8a4[ 	]+[ 	]+blt[ 	]+\$a1, \$a0, -56[ 	]+# 0x0
+[ 	]+3c:[ 	]+67ffc485[ 	]+[ 	]+bge[ 	]+\$a0, \$a1, -60[ 	]+# 0x0
+[ 	]+40:[ 	]+67ffc0a4[ 	]+[ 	]+bge[ 	]+\$a1, \$a0, -64[ 	]+# 0x0
+[ 	]+44:[ 	]+6bffbc85[ 	]+[ 	]+bltu[ 	]+\$a0, \$a1, -68[ 	]+# 0x0
+[ 	]+48:[ 	]+6bffb8a4[ 	]+[ 	]+bltu[ 	]+\$a1, \$a0, -72[ 	]+# 0x0
+[ 	]+4c:[ 	]+6fffb485[ 	]+[ 	]+bgeu[ 	]+\$a0, \$a1, -76[ 	]+# 0x0
+[ 	]+50:[ 	]+6fffb0a4[ 	]+[ 	]+bgeu[ 	]+\$a1, \$a0, -80[ 	]+# 0x0
 [ 	]+54:[ 	]+4c000020[ 	]+[ 	]+jirl[ 	]+\$zero, \$ra, 0
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
index a419c509584..4c5aea76dd0 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -8,9 +8,9 @@ Disassembly of section .text:
 
 00000000.* <.text>:
 [ 	]+0:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+4:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1\(0xfff\)
+[ 	]+4:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1
 [ 	]+8:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+c:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1\(0xfff\)
+[ 	]+c:[ 	]+02bffc04[ 	]+li.w[ 	]+\$a0,[ 	]+-1
 [ 	]+10:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+10:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.text
 [ 	]+14:[ 	]+28c00084[ 	]+ld.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 8eacea4ed94..10614a5a704 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -183,13 +183,7 @@ dis_one_arg (char esc1, char esc2, const char *bit_field,
 	  style = dis_style_immediate;
 	  break;
 	}
-      if (imm == 0)
-	info->fprintf_styled_func (info->stream, style, "%d", imm);
-      else
-	{
-	  info->fprintf_styled_func (info->stream, style, "%d", imm);
-	  info->fprintf_styled_func (info->stream, dis_style_text, "(0x%x)", u_imm);
-	}
+      info->fprintf_styled_func (info->stream, style, "%d", imm);
       switch (esc2)
 	{
 	case 'b':
-- 
2.39.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v4 6/6] opcodes/loongarch: print unrecognized insn words with the .word directive
  2023-02-15 18:02 [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks WANG Xuerui
                   ` (4 preceding siblings ...)
  2023-02-15 18:03 ` [PATCH v4 5/6] opcodes/loongarch: do not print hex notation for signed immediates WANG Xuerui
@ 2023-02-15 18:03 ` WANG Xuerui
  2023-03-02  9:23 ` [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks mengqinggang
  6 siblings, 0 replies; 8+ messages in thread
From: WANG Xuerui @ 2023-02-15 18:03 UTC (permalink / raw)
  To: binutils; +Cc: Chenghua Xu, Zhensong Liu, Qinggang Meng, Xi Ruoyao, WANG Xuerui

From: WANG Xuerui <git@xen0n.name>

For better round-trip fidelity and readability in general.
---
 gas/testsuite/gas/loongarch/raw-insn.d | 11 +++++++++++
 gas/testsuite/gas/loongarch/raw-insn.s |  7 +++++++
 opcodes/loongarch-dis.c                |  1 +
 3 files changed, 19 insertions(+)
 create mode 100644 gas/testsuite/gas/loongarch/raw-insn.d
 create mode 100644 gas/testsuite/gas/loongarch/raw-insn.s

diff --git a/gas/testsuite/gas/loongarch/raw-insn.d b/gas/testsuite/gas/loongarch/raw-insn.d
new file mode 100644
index 00000000000..64980e47f7b
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/raw-insn.d
@@ -0,0 +1,11 @@
+#as:
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+00000000[ 	]+.word[ 	]+0x00000000
+[ 	]+4:[ 	]+feedf00d[ 	]+.word[ 	]+0xfeedf00d
diff --git a/gas/testsuite/gas/loongarch/raw-insn.s b/gas/testsuite/gas/loongarch/raw-insn.s
new file mode 100644
index 00000000000..528b15263ae
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/raw-insn.s
@@ -0,0 +1,7 @@
+target:
+	.word 0
+	# Given how the LoongArch encoding space is apparently centrally-
+	# managed and sequentially allocated in chunks of prefixes, it is
+	# highly unlikely this would become a valid LoongArch instruction in
+	# the foreseeable future.
+	.word 0xfeedf00d
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 10614a5a704..c87ea569791 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -250,6 +250,7 @@ disassemble_one (insn_t insn, struct disassemble_info *info)
   if (!opc)
     {
       info->insn_type = dis_noninsn;
+      info->fprintf_styled_func (info->stream, dis_style_assembler_directive, ".word\t\t");
       info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%08x", insn);
       return;
     }
-- 
2.39.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks
  2023-02-15 18:02 [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks WANG Xuerui
                   ` (5 preceding siblings ...)
  2023-02-15 18:03 ` [PATCH v4 6/6] opcodes/loongarch: print unrecognized insn words with the .word directive WANG Xuerui
@ 2023-03-02  9:23 ` mengqinggang
  6 siblings, 0 replies; 8+ messages in thread
From: mengqinggang @ 2023-03-02  9:23 UTC (permalink / raw)
  To: WANG Xuerui, binutils; +Cc: Chenghua Xu, Zhensong Liu, Xi Ruoyao, WANG Xuerui

Hi,

Whether these patches should consider copyright issues and add
a sign-off at the of the commit message?


在 2023/2/16 上午2:02, WANG Xuerui 写道:
> From: WANG Xuerui <git@xen0n.name>
>
> Hi,
>
> This series implements colored output for LoongArch disassembly, and
> some minor tweaks to the output so there is less clutter.
>
> Changes from v3:
>
> - Fixed ld test cases (make check-gas and make check-ld both pass on
>    x86_64 and loongarch64)
> - Branch target address is now correctly printed in comment style, plus
>    code simplification as suggested
>
> Changes from v2:
>
> - Fixed test cases
> - Added the fixed "LoongArch: support disassembling certain pseudo-
>    instructions" patch into this series
> - Fixed ".insn" in the last patch to say ".word" instead (MIPS muscle
>    memory strikes back hard)
> - Fixed some commit messages
> - Added mengqinggang to Cc list
>
> WANG Xuerui (6):
>    LoongArch: support disassembling certain pseudo-instructions
>    opcodes/loongarch: remove unused code
>    opcodes/loongarch: implement style support in the disassembler
>    opcodes/loongarch: style disassembled address offsets as such
>    opcodes/loongarch: do not print hex notation for signed immediates
>    opcodes/loongarch: print unrecognized insn words with the .word
>      directive
>
>   gas/config/tc-loongarch.c                     |   3 +-
>   gas/testsuite/gas/loongarch/imm_ins.d         |  84 ++++++-------
>   gas/testsuite/gas/loongarch/imm_ins_32.d      |  54 ++++-----
>   gas/testsuite/gas/loongarch/imm_op.d          |  44 +++----
>   gas/testsuite/gas/loongarch/jmp_op.d          |  44 +++----
>   gas/testsuite/gas/loongarch/li.d              |   8 +-
>   gas/testsuite/gas/loongarch/load_store_op.d   |  80 ++++++------
>   gas/testsuite/gas/loongarch/macro_op.d        |   4 +-
>   gas/testsuite/gas/loongarch/macro_op_32.d     |   4 +-
>   .../gas/loongarch/macro_op_large_abs.d        |  14 +--
>   .../gas/loongarch/macro_op_large_pc.d         |  14 +--
>   gas/testsuite/gas/loongarch/nop.d             |   2 +-
>   gas/testsuite/gas/loongarch/privilege_op.d    |   8 +-
>   gas/testsuite/gas/loongarch/raw-insn.d        |  11 ++
>   gas/testsuite/gas/loongarch/raw-insn.s        |   7 ++
>   gas/testsuite/gas/loongarch/reloc.d           |   2 +-
>   include/opcode/loongarch.h                    |   7 +-
>   ld/testsuite/ld-loongarch-elf/jmp_op.d        |  40 +++---
>   ld/testsuite/ld-loongarch-elf/macro_op.d      |  24 ++--
>   opcodes/disassemble.c                         |   5 +
>   opcodes/loongarch-dis.c                       | 114 ++++++++----------
>   opcodes/loongarch-opc.c                       |  73 ++++++-----
>   22 files changed, 333 insertions(+), 313 deletions(-)
>   create mode 100644 gas/testsuite/gas/loongarch/raw-insn.d
>   create mode 100644 gas/testsuite/gas/loongarch/raw-insn.s
>


^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2023-03-02  9:23 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-15 18:02 [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks WANG Xuerui
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2023-02-15 18:02 ` [PATCH v4 2/6] opcodes/loongarch: remove unused code WANG Xuerui
2023-02-15 18:03 ` [PATCH v4 3/6] opcodes/loongarch: implement style support in the disassembler WANG Xuerui
2023-02-15 18:03 ` [PATCH v4 4/6] opcodes/loongarch: style disassembled address offsets as such WANG Xuerui
2023-02-15 18:03 ` [PATCH v4 5/6] opcodes/loongarch: do not print hex notation for signed immediates WANG Xuerui
2023-02-15 18:03 ` [PATCH v4 6/6] opcodes/loongarch: print unrecognized insn words with the .word directive WANG Xuerui
2023-03-02  9:23 ` [PATCH v4 0/6] LoongArch: colored disassembly and readability tweaks mengqinggang

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