From: Richard Sandiford <richard.sandiford@arm.com>
To: binutils@sourceware.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 02/31] aarch64: Add a _10 suffix to FLD_imm3
Date: Thu, 30 Mar 2023 11:26:17 +0100 [thread overview]
Message-ID: <20230330102646.3327818-3-richard.sandiford@arm.com> (raw)
In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com>
SME2 adds various new 3-bit immediate fields, so this patch adds
an lsb position suffix to the name of the field that we already have.
---
opcodes/aarch64-asm.c | 4 ++--
opcodes/aarch64-dis.c | 4 ++--
opcodes/aarch64-opc-2.c | 2 +-
opcodes/aarch64-opc.c | 2 +-
opcodes/aarch64-opc.h | 2 +-
opcodes/aarch64-tbl.h | 2 +-
6 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 7351c2417b2..5a9ca5a980d 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -943,7 +943,7 @@ aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
? AARCH64_MOD_UXTW : AARCH64_MOD_UXTX;
insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0);
/* imm3 */
- insert_field (FLD_imm3, code, info->shifter.amount, 0);
+ insert_field (FLD_imm3_10, code, info->shifter.amount, 0);
return true;
}
@@ -1016,7 +1016,7 @@ aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self,
int factor = 1 + get_operand_specific_data (self);
insert_field (self->fields[0], code, info->addr.base_regno, 0);
insert_fields (code, info->addr.offset.imm / factor, 0,
- 2, FLD_imm3, FLD_SVE_imm6);
+ 2, FLD_imm3_10, FLD_SVE_imm6);
return true;
}
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index e722514053e..49bfd46906e 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1395,7 +1395,7 @@ aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
info->shifter.kind =
aarch64_get_operand_modifier_from_value (value, true /* extend_p */);
/* imm3 */
- info->shifter.amount = extract_field (FLD_imm3, code, 0);
+ info->shifter.amount = extract_field (FLD_imm3_10, code, 0);
/* This makes the constraint checking happy. */
info->shifter.operator_present = 1;
@@ -1512,7 +1512,7 @@ aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self,
{
int offset;
- offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3);
+ offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3_10);
offset = (((offset + 256) & 511) - 256);
return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 1d59a8bd332..fe67dbc9b62 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -214,7 +214,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a 3-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3}, "an 8-bit unsigned immediate"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3_10}, "an 8-bit unsigned immediate"},
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"},
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"},
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 1a1e1bd22f3..969362a56cd 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -296,7 +296,7 @@ const aarch64_field fields[] =
{ 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
{ 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
{ 21, 2 }, /* hw: in move wide constant instructions. */
- { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
+ { 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */
{ 0, 4 }, /* imm4_0: in rmif instructions. */
{ 5, 4 }, /* imm4_5: in SME instructions. */
{ 10, 4 }, /* imm4_10: in adddg/subg instructions. */
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 3ded6ab7958..e142ae6ee76 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -124,7 +124,7 @@ enum aarch64_field_kind
FLD_cond2,
FLD_defgh,
FLD_hw,
- FLD_imm3,
+ FLD_imm3_10,
FLD_imm4_0,
FLD_imm4_5,
FLD_imm4_10,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 82f4af2839f..aa05ca0f4a9 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5863,7 +5863,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"a 7-bit unsigned immediate") \
Y(IMMEDIATE, imm, "SVE_UIMM8", 0, F(FLD_SVE_imm8), \
"an 8-bit unsigned immediate") \
- Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3), \
+ Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3_10), \
"an 8-bit unsigned immediate") \
Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \
Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register") \
--
2.25.1
next prev parent reply other threads:[~2023-03-30 10:26 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 10:26 [PATCH 00/31] aarch64: Add SME2 support Richard Sandiford
2023-03-30 10:26 ` [PATCH 01/31] aarch64: Add +sme2 Richard Sandiford
2023-03-30 10:26 ` Richard Sandiford [this message]
2023-03-30 10:26 ` [PATCH 03/31] aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array Richard Sandiford
2023-03-30 10:26 ` [PATCH 04/31] aarch64: Add support for vgx2 and vgx4 Richard Sandiford
2023-03-30 10:26 ` [PATCH 05/31] aarch64; Add support for vector offset ranges Richard Sandiford
2023-03-30 10:26 ` [PATCH 06/31] aarch64: Add support for predicate-as-counter registers Richard Sandiford
2023-03-30 10:26 ` [PATCH 07/31] aarch64: Add the SME2 MOVA instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 08/31] aarch64: Add the SME2 multivector LD1 and ST1 instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 09/31] aarch64: Add the SME2 predicate-related instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 10/31] aarch64: Add the SME2 ZT0 instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 11/31] aarch64: Add the SME2 ADD and SUB instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 12/31] aarch64: Add the SME2 maximum/minimum instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 13/31] aarch64: Add the SME2 FMLA and FMLS instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 14/31] aarch64: Add the SME2 MLAL and MLSL instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 15/31] aarch64: Add the SME2 MLALL and MLSLL instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 16/31] aarch64: Add the SME2 dot-product instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 17/31] aarch64: Add the SME2 vertical " Richard Sandiford
2023-03-30 10:26 ` [PATCH 18/31] aarch64: Add the SME2 MOPA and MOPS instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 19/31] aarch64: Add the SME2 CLAMP instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 20/31] aarch64: Add the SME2 FP<->int conversion instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 21/31] aarch64: Add the SME2 FP<->FP " Richard Sandiford
2023-03-30 10:26 ` [PATCH 22/31] aarch64: Add the SME2 saturating " Richard Sandiford
2023-03-30 10:26 ` [PATCH 23/31] aarch64: Add the SME2 shift instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 24/31] aarch64: Add the SME2 UNPK instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 25/31] aarch64: Add the SME2 UZP and ZIP instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 26/31] aarch64: Add the SVE BFMLSL instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 27/31] aarch64: Add new SVE dot-product instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 28/31] aarch64: Add new SVE saturating conversion instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 29/31] aarch64: Add new SVE shift instructions Richard Sandiford
2023-03-30 10:26 ` [PATCH 30/31] aarch64: Add the SVE FCLAMP instruction Richard Sandiford
2023-03-30 10:26 ` [PATCH 31/31] aarch64: Add the RPRFM instruction Richard Sandiford
2023-04-02 9:35 ` [PATCH 00/31] aarch64: Add SME2 support Jan Beulich
2023-04-03 8:05 ` Richard Sandiford
2023-04-03 8:14 ` Jan Beulich
2023-04-03 8:27 ` Richard Sandiford
2023-04-03 8:37 ` Jan Beulich
2023-04-03 9:31 ` Richard Sandiford
2023-04-03 7:16 ` Jan Beulich
2023-04-03 8:13 ` Richard Sandiford
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