Re: [PATCH 00/31] aarch64: Add SME2 support

[Richard Sandiford <richard.sandiford@arm.com>]

Jan Beulich <jbeulich@suse.com> writes:
> On 30.03.2023 12:26, Richard Sandiford via Binutils wrote:
>> This series of patches adds SME2 support to the AArch64 backend.
>> Details on SME2 are available here:
>> 
>>   https://developer.arm.com/documentation/ddi0602/2022-12/SME-Instructions
>> 
>> Tested on aarch64-linux-gnu, and via automatic cross-checking
>> against the architecture description and the LLVM implementation.
>> 
>> I've pushed the series under GWP, but I'm more than happy
>> to update/adjust/fix based on post-commit review, so please
>> let me know if you spot anything you think should be changed.
>> 
>> Thanks,
>> Richard
>> 
>> 
>> Richard Sandiford (31):
>>   aarch64: Add +sme2
>>   aarch64: Add a _10 suffix to FLD_imm3
>>   aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array
>>   aarch64: Add support for vgx2 and vgx4
>>   aarch64; Add support for vector offset ranges
>>   aarch64: Add support for predicate-as-counter registers
>
> Shouldn't the (alias) insn forms added here all use SME2_INSN()? It
> doesn't seem to make sense to permit them with ".arch_extension sme".

That's deliberate (and it's deliberate for the SVE instructions
like PFALSE too).  The base requirements in the table come from
the underlying architectural requirements.  In this case, the
instructions are unchanged, and so the FEAT_* requirements are
the same.  Accepting predicate-as-counter registers is just a
syntactic convenience.

It's true that, without SME2 (or SVE2p1) you might not be able to do
much with the predicate-as-counter registers except move, load and store
them.  But that doesn't make those operations invalid (and so something
that the assembler must reject).

Thanks,
Richard