From: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
To: binutils@sourceware.org
Cc: rui314@gmail.com, ruiu@bluewhale.systems, i@maskray.me,
nelson@rivosinc.com, Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Subject: [PATCH v2 3/5] RISC-V: Add assembly support for TLSDESC.
Date: Fri, 1 Sep 2023 02:13:33 +0900 [thread overview]
Message-ID: <20230831171345.49052-4-ishitatsuyuki@gmail.com> (raw)
In-Reply-To: <20230831171345.49052-1-ishitatsuyuki@gmail.com>
gas/
* tc-riscv.c (percent_op_*): Add support for %tlsdesc_hi,
%tlsdesc_load_lo, %tlsdesc_add_lo and %tlsdesc_call. percent_op_rtype
renamed to percent_op_relax_only as this matcher is extended to handle
jalr as well which is not R-type.
(riscv_ip): Apply the percent_op_relax_only rename and update comment.
(md_apply_fix): Add TLSDESC_* to relaxable list. Add TLSDESC_HI20 to
TLS relocation check list.
* testsuite/gas/riscv/tlsdesc.*: New test cases for TLSDESC relocation
generation.
opcodes/
* riscv-opc.c (riscv_opcodes): Add a new syntax for jalr with
%tlsdesc_call annotations.
---
gas/config/tc-riscv.c | 18 +++++++++++++-----
gas/testsuite/gas/riscv/tlsdesc.d | 22 ++++++++++++++++++++++
gas/testsuite/gas/riscv/tlsdesc.s | 24 ++++++++++++++++++++++++
opcodes/riscv-opc.c | 1 +
4 files changed, 60 insertions(+), 5 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/tlsdesc.d
create mode 100644 gas/testsuite/gas/riscv/tlsdesc.s
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 959cbbc32a5..0a1fac9de9d 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2195,6 +2195,7 @@ static const struct percent_op_match percent_op_utype[] =
{"tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
{"pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
{"got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
+ {"tlsdesc_hi", BFD_RELOC_RISCV_TLSDESC_HI20},
{"tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
{"tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
{"hi", BFD_RELOC_RISCV_HI20},
@@ -2206,6 +2207,8 @@ static const struct percent_op_match percent_op_itype[] =
{"lo", BFD_RELOC_RISCV_LO12_I},
{"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
{"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
+ {"tlsdesc_load_lo", BFD_RELOC_RISCV_TLSDESC_LOAD_LO12},
+ {"tlsdesc_add_lo", BFD_RELOC_RISCV_TLSDESC_ADD_LO12},
{0, 0}
};
@@ -2217,8 +2220,9 @@ static const struct percent_op_match percent_op_stype[] =
{0, 0}
};
-static const struct percent_op_match percent_op_rtype[] =
+static const struct percent_op_match percent_op_relax_only[] =
{
+ {"tlsdesc_call", BFD_RELOC_RISCV_TLSDESC_CALL},
{"tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
{0, 0}
};
@@ -3326,10 +3330,10 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
*imm_reloc = BFD_RELOC_RISCV_LO12_I;
goto load_store;
case '1':
- /* This is used for TLS, where the fourth operand is
- %tprel_add, to get a relocation applied to an add
- instruction, for relaxation to use. */
- p = percent_op_rtype;
+ /* This is used for TLS relocations that acts as relaxation
+ markers and do not change the instruction encoding,
+ i.e. %tprel_add and %tlsdesc_call. */
+ p = percent_op_relax_only;
goto alu_op;
case '0': /* AMO displacement, which must be zero. */
load_store:
@@ -4082,6 +4086,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_RISCV_TPREL_LO12_I:
case BFD_RELOC_RISCV_TPREL_LO12_S:
case BFD_RELOC_RISCV_TPREL_ADD:
+ case BFD_RELOC_RISCV_TLSDESC_HI20:
relaxable = true;
/* Fall through. */
@@ -4255,6 +4260,9 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_RISCV_CALL:
case BFD_RELOC_RISCV_CALL_PLT:
+ case BFD_RELOC_RISCV_TLSDESC_LOAD_LO12:
+ case BFD_RELOC_RISCV_TLSDESC_ADD_LO12:
+ case BFD_RELOC_RISCV_TLSDESC_CALL:
relaxable = true;
break;
diff --git a/gas/testsuite/gas/riscv/tlsdesc.d b/gas/testsuite/gas/riscv/tlsdesc.d
new file mode 100644
index 00000000000..8ba35826130
--- /dev/null
+++ b/gas/testsuite/gas/riscv/tlsdesc.d
@@ -0,0 +1,22 @@
+#as: -march=rv32ia
+#source: tlsdesc.s
+#readelf: -Wr
+
+Relocation section '.rela.text' at offset 0x[0-9a-f]+ contains 16 entries:
+ +Offset +Info +Type +Sym. Value +Symbol's Name \+ Addend
+0+ +0+a3e +R_RISCV_TLSDESC_HI20 +0+ +sg1 \+ 0
+0+ +0+33 +R_RISCV_RELAX + 0
+0+4 +0+63f +R_RISCV_TLSDESC_LOAD_LO12 0+ +\.desc1 \+ 0
+0+4 +0+33 +R_RISCV_RELAX + 0
+0+8 +0+640 +R_RISCV_TLSDESC_ADD_LO12 0+ +\.desc1 \+ 0
+0+8 +0+33 +R_RISCV_RELAX + 0
+0+c +0+641 +R_RISCV_TLSDESC_CALL +0+ +\.desc1 \+ 0
+0+c +0+33 +R_RISCV_RELAX + 0
+0+10 +0+53e +R_RISCV_TLSDESC_HI20 +0+4 +sl1 \+ 0
+0+10 +0+33 +R_RISCV_RELAX + 0
+0+14 +0+83f +R_RISCV_TLSDESC_LOAD_LO12 0+10 +\.desc2 \+ 0
+0+14 +0+33 +R_RISCV_RELAX + 0
+0+18 +0+840 +R_RISCV_TLSDESC_ADD_LO12 0+10 +\.desc2 \+ 0
+0+18 +0+33 +R_RISCV_RELAX +0
+0+1c +0+841 +R_RISCV_TLSDESC_CALL +0+10 +\.desc2 \+ 0
+0+1c +0+33 +R_RISCV_RELAX +0
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/tlsdesc.s b/gas/testsuite/gas/riscv/tlsdesc.s
new file mode 100644
index 00000000000..15468d5f947
--- /dev/null
+++ b/gas/testsuite/gas/riscv/tlsdesc.s
@@ -0,0 +1,24 @@
+ .section .tbss,"awT",@nobits
+ .global sg1
+sg1:
+ .zero 4
+sl1:
+ .zero 4
+
+ .text
+ .globl _start
+ .type _start,@function
+_start:
+.desc1:
+ auipc a0, %tlsdesc_hi(sg1)
+ lw t0, %tlsdesc_load_lo(.desc1)(a0)
+ addi a0, a0, %tlsdesc_add_lo(.desc1)
+ jalr t0, t0, %tlsdesc_call(.desc1)
+
+.desc2:
+ auipc a0, %tlsdesc_hi(sl1)
+ lw t0, %tlsdesc_load_lo(.desc2)(a0)
+ addi a0, a0, %tlsdesc_add_lo(.desc2)
+ jalr t0, t0, %tlsdesc_call(.desc2)
+
+ ret
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 067e9fdb611..467666b9805 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -370,6 +370,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"jalr", 0, INSN_CLASS_I, "s,j", MATCH_JALR|(X_RA << OP_SH_RD), MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR },
{"jalr", 0, INSN_CLASS_I, "d,s", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR },
{"jalr", 0, INSN_CLASS_I, "d,o(s)", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
+{"jalr", 0, INSN_CLASS_I, "d,s,1", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_JSR },
{"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR },
{"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH },
{"j", 0, INSN_CLASS_I, "a", MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },
--
2.42.0
next prev parent reply other threads:[~2023-08-31 17:13 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-17 18:08 [PATCH 0/4] RISC-V: Implement TLS Descriptors Tatsuyuki Ishi
2023-08-17 18:08 ` [PATCH 1/4] RISC-V: Add TLSDESC reloc definitions Tatsuyuki Ishi
2023-08-17 18:08 ` [PATCH 2/4] RISC-V: Add assembly support for TLSDESC Tatsuyuki Ishi
2023-08-17 18:08 ` [PATCH 3/4] RISC-V: Define and use GOT entry size constants for TLS Tatsuyuki Ishi
2023-08-17 18:08 ` [PATCH 4/4] RISC-V: Initial ld.bfd support for TLSDESC Tatsuyuki Ishi
2023-08-18 0:22 ` [PATCH 0/4] RISC-V: Implement TLS Descriptors Nelson Chu
2023-08-18 7:13 ` Fangrui Song
2023-08-31 17:13 ` [PATCH v2 0/5] " Tatsuyuki Ishi
2023-08-31 17:13 ` [PATCH v2 1/5] RISC-V: Fix local GOT and reloc size calculation for TLS Tatsuyuki Ishi
2024-02-21 0:49 ` Nelson Chu
2024-02-21 7:04 ` Nelson Chu
2023-08-31 17:13 ` [PATCH v2 2/5] RISC-V: Add TLSDESC reloc definitions Tatsuyuki Ishi
2023-08-31 17:13 ` Tatsuyuki Ishi [this message]
2023-08-31 17:13 ` [PATCH v2 4/5] RISC-V: Define and use GOT entry size constants for TLS Tatsuyuki Ishi
2023-08-31 17:13 ` [PATCH v2 5/5] RISC-V: Initial ld.bfd support for TLSDESC Tatsuyuki Ishi
2023-11-28 8:51 ` [PATCH v3 0/9] RISC-V: Implement TLS Descriptors Tatsuyuki Ishi
2023-11-28 8:51 ` [PATCH v3 1/9] RISC-V: Fix local GOT and reloc size calculation for TLS Tatsuyuki Ishi
2023-11-28 8:51 ` [PATCH v3 2/9] RISC-V: Add TLSDESC reloc definitions Tatsuyuki Ishi
2024-02-19 0:49 ` Nelson Chu
2024-02-20 17:28 ` Tatsuyuki Ishi
2023-11-28 8:51 ` [PATCH v3 3/9] RISC-V: Add assembly support for TLSDESC Tatsuyuki Ishi
2024-02-19 1:44 ` Nelson Chu
2024-02-20 17:29 ` Tatsuyuki Ishi
2023-11-28 8:51 ` [PATCH v3 4/9] RISC-V: Define and use GOT entry size constants for TLS Tatsuyuki Ishi
2024-02-19 1:57 ` Nelson Chu
2024-02-20 17:32 ` Tatsuyuki Ishi
2023-11-28 8:51 ` [PATCH v3 5/9] RISC-V: Initial ld.bfd support for TLSDESC Tatsuyuki Ishi
2024-02-19 4:33 ` Nelson Chu
2024-02-20 17:36 ` Tatsuyuki Ishi
2023-11-28 8:51 ` [PATCH v3 6/9] RISC-V: Move STATIC_TLS handling into record_tls_type Tatsuyuki Ishi
2023-11-28 8:51 ` [PATCH v3 7/9] RISC-V: Unify TLS handling in check_relocs Tatsuyuki Ishi
2023-11-28 8:51 ` [PATCH v3 8/9] RISC-V: Add elf_link_hash_entry to relax_func args Tatsuyuki Ishi
2023-11-28 8:51 ` [PATCH v3 9/9] RISC-V: Introduce TLSDESC relaxation Tatsuyuki Ishi
2023-12-05 16:44 ` [PATCH v3 0/9] RISC-V: Implement TLS Descriptors Tatsuyuki Ishi
2023-12-06 0:33 ` Nelson Chu
2023-12-07 3:35 ` Fangrui Song
2023-12-13 0:27 ` Palmer Dabbelt
2023-12-13 1:53 ` Tatsuyuki Ishi
2024-01-27 0:57 ` Fangrui Song
2024-02-20 17:55 ` [PATCH v4 " Tatsuyuki Ishi
2024-02-20 17:55 ` [PATCH v4 1/9] RISC-V: Fix local GOT and reloc size calculation for TLS Tatsuyuki Ishi
2024-02-20 17:55 ` [PATCH v4 2/9] RISC-V: Add TLSDESC reloc definitions Tatsuyuki Ishi
2024-02-20 17:55 ` [PATCH v4 3/9] RISC-V: Add assembly support for TLSDESC Tatsuyuki Ishi
2024-02-20 17:55 ` [PATCH v4 4/9] RISC-V: Define and use GOT entry size constants for TLS Tatsuyuki Ishi
2024-02-20 17:55 ` [PATCH v4 5/9] RISC-V: Initial ld.bfd support for TLSDESC Tatsuyuki Ishi
2024-02-20 17:55 ` [PATCH v4 6/9] RISC-V: Move STATIC_TLS handling into record_tls_type Tatsuyuki Ishi
2024-02-20 17:55 ` [PATCH v4 7/9] RISC-V: Unify TLS handling in check_relocs Tatsuyuki Ishi
2024-02-20 17:55 ` [PATCH v4 8/9] RISC-V: Add elf_link_hash_entry to relax_func args Tatsuyuki Ishi
2024-02-20 17:55 ` [PATCH v4 9/9] RISC-V: Introduce TLSDESC relaxation Tatsuyuki Ishi
2024-02-29 7:06 ` [PATCH v4 0/9] RISC-V: Implement TLS Descriptors Nelson Chu
2024-02-29 7:14 ` Tatsuyuki Ishi
2024-03-29 6:22 ` Tatsuyuki Ishi
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