[PATCH 1/3] aarch64: Add FEAT_SPECRES2 support

[PATCH 1/3] aarch64: Add FEAT_SPECRES2 support

[Andrea Corallo]

This patch add supports for FEAT_SPECRES2 "Enhanced speculation
restriction instructions" adding the "cosp" instruction.

This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+.  It is
enabled by the +predres2 march flag.
---
 gas/config/tc-aarch64.c                        |  1 +
 gas/doc/c-aarch64.texi                         |  2 ++
 gas/testsuite/gas/aarch64/illegal-predres2-1.d |  3 +++
 gas/testsuite/gas/aarch64/illegal-predres2-1.l |  5 +++++
 gas/testsuite/gas/aarch64/predres2.d           | 10 ++++++++++
 gas/testsuite/gas/aarch64/predres2.s           |  4 ++++
 include/opcode/aarch64.h                       |  5 ++++-
 opcodes/aarch64-tbl.h                          |  7 +++++++
 8 files changed, 36 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/aarch64/illegal-predres2-1.d
 create mode 100644 gas/testsuite/gas/aarch64/illegal-predres2-1.l
 create mode 100644 gas/testsuite/gas/aarch64/predres2.d
 create mode 100644 gas/testsuite/gas/aarch64/predres2.s

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 25271e0f12e..827e0436136 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10268,6 +10268,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"sha2",		AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)},
   {"sb",		AARCH64_FEATURE (SB), AARCH64_NO_FEATURES},
   {"predres",		AARCH64_FEATURE (PREDRES), AARCH64_NO_FEATURES},
+  {"predres2",		AARCH64_FEATURE (PREDRES2), AARCH64_FEATURE (PREDRES)},
   {"aes",		AARCH64_FEATURE (AES), AARCH64_FEATURE (SIMD)},
   {"sm4",		AARCH64_FEATURE (SM4), AARCH64_FEATURE (SIMD)},
   {"sha3",		AARCH64_FEATURE (SHA3), AARCH64_FEATURE (SHA2)},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index d19bc3b0030..0624c4f0bb8 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -265,6 +265,8 @@ automatically cause those extensions to be disabled.
  @tab Enable Guarded Control Stack Extension.
 @item @code{rasv2} @tab ARMv8.8-A @tab ARMv9.3-A or later
  @tab Enable the Reliability, Availability and Serviceability extension v2.
+@item @code{predres2} @tab ARMv8-A/Armv9-A @tab ARMv8.9-A/Armv9.4-A or later
+ @tab Enable Prediction instructions.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/illegal-predres2-1.d b/gas/testsuite/gas/aarch64/illegal-predres2-1.d
new file mode 100644
index 00000000000..f858afd34c9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-predres2-1.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: predres2.s
+#error_output: illegal-predres2-1.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/illegal-predres2-1.l b/gas/testsuite/gas/aarch64/illegal-predres2-1.l
new file mode 100644
index 00000000000..15f568030be
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-predres2-1.l
@@ -0,0 +1,5 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cosp rctx,x1'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cfp rctx,x1'
diff --git a/gas/testsuite/gas/aarch64/predres2.d b/gas/testsuite/gas/aarch64/predres2.d
new file mode 100644
index 00000000000..cc5ea087f26
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/predres2.d
@@ -0,0 +1,10 @@
+#as: -march=armv8-a+predres2
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d50b73c1 	cosp	rctx, x1
+.*:	d50b7381 	cfp	rctx, x1
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/predres2.s b/gas/testsuite/gas/aarch64/predres2.s
new file mode 100644
index 00000000000..3f6f88cace3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/predres2.s
@@ -0,0 +1,4 @@
+/* File to test the +predres2 option.  */
+func:
+	cosp rctx, x1
+	cfp rctx, x1
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index bb180d30ef9..ae6457597e5 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -171,6 +171,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SME2,
   /* ARMv8.9-A RAS Extensions.  */
   AARCH64_FEATURE_RASv2,
+  /* Speculation Prediction Restriction instructions.  */
+  AARCH64_FEATURE_PREDRES2,
   DUMMY1,
   DUMMY2,
   DUMMY3,
@@ -241,7 +243,8 @@ enum aarch64_feature_bit {
 #define AARCH64_ARCH_V9_1A_FEATURES(X)	AARCH64_ARCH_V8_6A_FEATURES (X)
 #define AARCH64_ARCH_V9_2A_FEATURES(X)	AARCH64_ARCH_V8_7A_FEATURES (X)
 #define AARCH64_ARCH_V9_3A_FEATURES(X)	AARCH64_ARCH_V8_8A_FEATURES (X)
-#define AARCH64_ARCH_V9_4A_FEATURES(X)	AARCH64_ARCH_V8_9A_FEATURES (X)
+#define AARCH64_ARCH_V9_4A_FEATURES(X)	(AARCH64_ARCH_V8_9A_FEATURES (X) \
+					 | AARCH64_FEATBIT (X, PREDRES2))
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8A(X)	(AARCH64_FEATBIT (X, V8) \
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 850f4c2d2af..e07836cd668 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2516,6 +2516,8 @@ static const aarch64_feature_set aarch64_feature_sb =
   AARCH64_FEATURE (SB);
 static const aarch64_feature_set aarch64_feature_predres =
   AARCH64_FEATURE (PREDRES);
+static const aarch64_feature_set aarch64_feature_predres2 =
+  AARCH64_FEATURES (2, PREDRES, PREDRES2);
 static const aarch64_feature_set aarch64_feature_memtag =
   AARCH64_FEATURE (MEMTAG);
 static const aarch64_feature_set aarch64_feature_bfloat16 =
@@ -2609,6 +2611,7 @@ static const aarch64_feature_set aarch64_feature_rasv2 =
 #define FRINTTS		&aarch64_feature_frintts
 #define SB		&aarch64_feature_sb
 #define PREDRES		&aarch64_feature_predres
+#define PREDRES2	&aarch64_feature_predres2
 #define MEMTAG		&aarch64_feature_memtag
 #define TME		&aarch64_feature_tme
 #define SVE2		&aarch64_feature_sve2
@@ -2842,6 +2845,9 @@ static const aarch64_feature_set aarch64_feature_rasv2 =
   MOPS_SET_OP1_OP2_INSN (NAME, "n", OPCODE | 0x2000, MASK, ISA), \
   MOPS_SET_OP1_OP2_INSN (NAME, "tn", OPCODE | 0x3000, MASK, ISA)
 
+#define PREDRES2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, PREDRES2, OPS, QUALS, FLAGS, 0, 0, NULL }
+
 const struct aarch64_opcode aarch64_opcode_table[] =
 {
   /* Add/subtract (with carry).  */
@@ -4173,6 +4179,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
   PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
   PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
+  PREDRES2_INSN ("cosp", 0xd50b73c0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
   /* Armv8.4-a flag setting instruction, However this encoding has an encoding clash with the msr
      below it.  Usually we can resolve this by setting an alias condition on the flags, however that
      depends on the disassembly masks to be able to quickly find the alias.  The problem is the
-- 
2.25.1

[PATCH 2/3] aarch64: Add FEAT_ECBHB support

[Andrea Corallo]

This patch add support for FEAT_ECBHB "Exploitative control using
branch history information" adding the "clrbhb" instruction.  AFAIU
the same alias was originally added as "clearbhb" before the
architecture was finalized (Mandatory v8.9-a/v9.4-a; Optional
v8.0-a+/v9.0-a+).
---
 gas/testsuite/gas/aarch64/clrbhb-1.d | 9 +++++++++
 gas/testsuite/gas/aarch64/clrbhb-1.s | 2 ++
 gas/testsuite/gas/aarch64/system.d   | 4 ++--
 opcodes/aarch64-tbl.h                | 4 ++++
 4 files changed, 17 insertions(+), 2 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/clrbhb-1.d
 create mode 100644 gas/testsuite/gas/aarch64/clrbhb-1.s

diff --git a/gas/testsuite/gas/aarch64/clrbhb-1.d b/gas/testsuite/gas/aarch64/clrbhb-1.d
new file mode 100644
index 00000000000..272ee23dfda
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/clrbhb-1.d
@@ -0,0 +1,9 @@
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+   0:	d50322df 	clrbhb
+
diff --git a/gas/testsuite/gas/aarch64/clrbhb-1.s b/gas/testsuite/gas/aarch64/clrbhb-1.s
new file mode 100644
index 00000000000..edf88466e4c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/clrbhb-1.s
@@ -0,0 +1,2 @@
+	clrbhb
+
diff --git a/gas/testsuite/gas/aarch64/system.d b/gas/testsuite/gas/aarch64/system.d
index bb1a94cb020..a1114169d55 100644
--- a/gas/testsuite/gas/aarch64/system.d
+++ b/gas/testsuite/gas/aarch64/system.d
@@ -14,7 +14,7 @@ Disassembly of section \.text:
 .*:	d503207f 	wfi
 .*:	d503209f 	sev
 .*:	d50320bf 	sevl
-.*:	d50322df 	clearbhb
+.*:	d50322df 	clrbhb
 .*:	d503201f 	nop
 .*:	d503203f 	yield
 .*:	d503205f 	wfe
@@ -37,7 +37,7 @@ Disassembly of section \.text:
 .*:	d503227f 	(hint	#0x13|gcsb	dsync)
 .*:	d503229f 	(hint	#0x14|csdb)
 .*:	d50322bf 	hint	#0x15
-.*:	d50322df 	(hint	#0x16|clearbhb)
+.*:	d50322df 	(hint	#0x16|clrbhb)
 .*:	d50322ff 	hint	#0x17
 .*:	d503231f 	(hint	#0x18|paciaz)
 .*:	d503233f 	(hint	#0x19|paciasp)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index e07836cd668..b64d94ab70f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6101,6 +6101,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   CSSC_INSN ("smin", 0x1ac06800, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
   CSSC_INSN ("umin", 0x1ac06c00, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
 
+  /* FEAT_CLRBHB part of the hint space and available without special
+     command-line flags.  */
+  CORE_INSN ("clrbhb", 0xd50322df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
+
   {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
 };
 
-- 
2.25.1

[PATCH 3/3] aarch64: Add FEAT_ITE support

[Andrea Corallo]

This patch add support for FEAT_ITE "Instrumentation Extension" adding
the "trcit" instruction.

This is enabled by the +ite march flag.
---
 gas/config/tc-aarch64.c                    | 1 +
 gas/doc/c-aarch64.texi                     | 2 ++
 gas/testsuite/gas/aarch64/illegal-ite1-1.d | 3 +++
 gas/testsuite/gas/aarch64/illegal-ite1-1.l | 2 ++
 gas/testsuite/gas/aarch64/ite1.d           | 9 +++++++++
 gas/testsuite/gas/aarch64/ite1.s           | 4 ++++
 include/opcode/aarch64.h                   | 2 ++
 opcodes/aarch64-tbl.h                      | 8 ++++++++
 8 files changed, 31 insertions(+)
 create mode 100644 gas/testsuite/gas/aarch64/illegal-ite1-1.d
 create mode 100644 gas/testsuite/gas/aarch64/illegal-ite1-1.l
 create mode 100644 gas/testsuite/gas/aarch64/ite1.d
 create mode 100644 gas/testsuite/gas/aarch64/ite1.s

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 827e0436136..84c69a8eedf 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10305,6 +10305,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"gcs",		AARCH64_FEATURE (GCS), AARCH64_NO_FEATURES},
   {"prfmslc",		AARCH64_FEATURE (PRFMSLC), AARCH64_NO_FEATURES},
   {"rasv2",		AARCH64_FEATURE (RASv2), AARCH64_NO_FEATURES},
+  {"ite",		AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 0624c4f0bb8..3c0aeeb6720 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -267,6 +267,8 @@ automatically cause those extensions to be disabled.
  @tab Enable the Reliability, Availability and Serviceability extension v2.
 @item @code{predres2} @tab ARMv8-A/Armv9-A @tab ARMv8.9-A/Armv9.4-A or later
  @tab Enable Prediction instructions.
+@item @code{ite} @tab N/A @tab no
+ @tab Enable TRCIT instruction.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/illegal-ite1-1.d b/gas/testsuite/gas/aarch64/illegal-ite1-1.d
new file mode 100644
index 00000000000..99ef4d47d7b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-ite1-1.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: ite1.s
+#error_output: illegal-ite1-1.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/illegal-ite1-1.l b/gas/testsuite/gas/aarch64/illegal-ite1-1.l
new file mode 100644
index 00000000000..1e97c9147ee
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-ite1-1.l
@@ -0,0 +1,2 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: selected processor does not support `trcit x1'
diff --git a/gas/testsuite/gas/aarch64/ite1.d b/gas/testsuite/gas/aarch64/ite1.d
new file mode 100644
index 00000000000..7c4b486ced8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ite1.d
@@ -0,0 +1,9 @@
+#as: -march=armv9.4-a+ite
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d50b72e1 	trcit	x1
diff --git a/gas/testsuite/gas/aarch64/ite1.s b/gas/testsuite/gas/aarch64/ite1.s
new file mode 100644
index 00000000000..595ecf897f2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ite1.s
@@ -0,0 +1,4 @@
+/* File to test the +ite option.  */
+func:
+	trcit x1
+	
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index ae6457597e5..fe046b9adfb 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -173,6 +173,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_RASv2,
   /* Speculation Prediction Restriction instructions.  */
   AARCH64_FEATURE_PREDRES2,
+  /* Instrumentation Extension.  */
+  AARCH64_FEATURE_ITE,
   DUMMY1,
   DUMMY2,
   DUMMY3,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index b64d94ab70f..ac21a563b3b 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2582,6 +2582,8 @@ static const aarch64_feature_set aarch64_feature_prfmslc =
   AARCH64_FEATURE (PRFMSLC);
 static const aarch64_feature_set aarch64_feature_rasv2 =
   AARCH64_FEATURE (RASv2);
+static const aarch64_feature_set aarch64_feature_ite =
+  AARCH64_FEATURE (ITE);
 
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
@@ -2645,6 +2647,7 @@ static const aarch64_feature_set aarch64_feature_rasv2 =
 #define GCS	  &aarch64_feature_gcs
 #define PRFMSLC  &aarch64_feature_prfmslc
 #define RASv2  &aarch64_feature_rasv2
+#define ITE	  &aarch64_feature_ite
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2848,6 +2851,9 @@ static const aarch64_feature_set aarch64_feature_rasv2 =
 #define PREDRES2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, PREDRES2, OPS, QUALS, FLAGS, 0, 0, NULL }
 
+#define ITE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, ITE, OPS, QUALS, FLAGS, 0, 0, NULL }
+
 const struct aarch64_opcode aarch64_opcode_table[] =
 {
   /* Add/subtract (with carry).  */
@@ -6105,6 +6111,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
      command-line flags.  */
   CORE_INSN ("clrbhb", 0xd50322df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
 
+  ITE_INSN ("trcit", 0xd50b72e0, 0xffffffe0, ic_system, OP1 (Rt), QL_I1X, F_ALIAS),
+
   {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
 };
 
-- 
2.25.1

Re: [PATCH 1/3] aarch64: Add FEAT_SPECRES2 support

[Nick Clifton]

Hi Andrea,

> This patch add supports for FEAT_SPECRES2 "Enhanced speculation
> restriction instructions" adding the "cosp" instruction.
> 
> This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+.  It is
> enabled by the +predres2 march flag.
> ---
>   gas/config/tc-aarch64.c                        |  1 +
>   gas/doc/c-aarch64.texi                         |  2 ++
>   gas/testsuite/gas/aarch64/illegal-predres2-1.d |  3 +++
>   gas/testsuite/gas/aarch64/illegal-predres2-1.l |  5 +++++
>   gas/testsuite/gas/aarch64/predres2.d           | 10 ++++++++++
>   gas/testsuite/gas/aarch64/predres2.s           |  4 ++++
>   include/opcode/aarch64.h                       |  5 ++++-
>   opcodes/aarch64-tbl.h                          |  7 +++++++
>   8 files changed, 36 insertions(+), 1 deletion(-)
>   create mode 100644 gas/testsuite/gas/aarch64/illegal-predres2-1.d
>   create mode 100644 gas/testsuite/gas/aarch64/illegal-predres2-1.l
>   create mode 100644 gas/testsuite/gas/aarch64/predres2.d
>   create mode 100644 gas/testsuite/gas/aarch64/predres2.s

Approved - please apply.

Cheers
   Nick

Re: [PATCH 2/3] aarch64: Add FEAT_ECBHB support

[Nick Clifton]

Hi Andrea,

>   gas/testsuite/gas/aarch64/clrbhb-1.d | 9 +++++++++
>   gas/testsuite/gas/aarch64/clrbhb-1.s | 2 ++
>   gas/testsuite/gas/aarch64/system.d   | 4 ++--
>   opcodes/aarch64-tbl.h                | 4 ++++

Approved - please apply.

Cheers
   Nick

Re: [PATCH 3/3] aarch64: Add FEAT_ITE support

[Nick Clifton]

Hi Andrea ,

> This patch add support for FEAT_ITE "Instrumentation Extension" adding
> the "trcit" instruction.
> 
> This is enabled by the +ite march flag.
> ---
>   gas/config/tc-aarch64.c                    | 1 +
>   gas/doc/c-aarch64.texi                     | 2 ++
>   gas/testsuite/gas/aarch64/illegal-ite1-1.d | 3 +++
>   gas/testsuite/gas/aarch64/illegal-ite1-1.l | 2 ++
>   gas/testsuite/gas/aarch64/ite1.d           | 9 +++++++++
>   gas/testsuite/gas/aarch64/ite1.s           | 4 ++++
>   include/opcode/aarch64.h                   | 2 ++
>   opcodes/aarch64-tbl.h                      | 8 ++++++++

Approved - please apply.

Cheers
   Nick

Re: [PATCH 3/3] aarch64: Add FEAT_ITE support

[Andrea Corallo]

Nick Clifton <nickc@redhat.com> writes:

> Hi Andrea ,
>
>> This patch add support for FEAT_ITE "Instrumentation Extension" adding
>> the "trcit" instruction.
>> This is enabled by the +ite march flag.
>> ---
>>   gas/config/tc-aarch64.c                    | 1 +
>>   gas/doc/c-aarch64.texi                     | 2 ++
>>   gas/testsuite/gas/aarch64/illegal-ite1-1.d | 3 +++
>>   gas/testsuite/gas/aarch64/illegal-ite1-1.l | 2 ++
>>   gas/testsuite/gas/aarch64/ite1.d           | 9 +++++++++
>>   gas/testsuite/gas/aarch64/ite1.s           | 4 ++++
>>   include/opcode/aarch64.h                   | 2 ++
>>   opcodes/aarch64-tbl.h                      | 8 ++++++++
>
> Approved - please apply.
>
> Cheers
>   Nick

Hi Nick,

sorry for the delay and thanks for having approved these three patches.
I've applied them now as d645278cdf4 db168da2e0d and 88b5a8ae138.

Best Regards

  Andrea