* [PATCH] RISC-V: Support B, Zaamo and Zalrsc extensions.
@ 2024-02-05 1:39 Nelson Chu
2024-05-08 4:37 ` Nelson Chu
0 siblings, 1 reply; 3+ messages in thread
From: Nelson Chu @ 2024-02-05 1:39 UTC (permalink / raw)
To: binutils, jim.wilson.gcc, palmer, ved, andrew, kito.cheng
Cc: nelson.rivosinc.com, Nelson Chu
* https://github.com/riscv/riscv-b/tags
Added standard B extension back, which implies Zba, Zbb and Zbs extensions.
* https://github.com/riscv/riscv-zaamo-zalrsc/tags
Splited standard A extension into two new extensions, Zaamo and Zalrsc.
The A extension implies Zaamo and Zalrsc extensions.
Not sure if we need to do the similar check as i and zicsr/zifencei.
Passed riscv[32|64]-[elf/linux] binutils testcases.
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules
for A and B extensions. The A implies Zaamo and Zalrsc, the
B implies Zba, Zbb and Zbs.
(riscv_supported_std_ext): Supported B extension with v1.0.
(riscv_supported_std_z_ext): Supported Zaamo and Zalrsc with v1.0.
(riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Updated.
include/
* opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_A, Added
INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC.
opcodes/
* riscv-opc.c (riscv_opcodes): Splited standard A extension into two
new extensions, Zaamo and Zalrsc.
gas/
* testsuite/gas/riscv/march-imply-a.d: New testcase.
* testsuite/gas/riscv/march-imply-b.d: New testcase.
* testsuite/gas/riscv/attribute-01.d: Updated.
* testsuite/gas/riscv/attribute-02.d: Updated.
* testsuite/gas/riscv/attribute-03.d: Updated.
* testsuite/gas/riscv/attribute-04.d: Updated.
* testsuite/gas/riscv/attribute-05.d: Updated.
* testsuite/gas/riscv/attribute-10.d: Updated.
* testsuite/gas/riscv/mapping-symbols.d: Updated.
* testsuite/gas/riscv/march-imply-g.d: Updated.
* testsuite/gas/riscv/march-imply-unsupported.d: Updated.
* testsuite/gas/riscv/march-ok-reorder.d: Updated.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Updated.
---
bfd/elfxx-riscv.c | 20 +-
gas/testsuite/gas/riscv/attribute-01.d | 2 +-
gas/testsuite/gas/riscv/attribute-02.d | 2 +-
gas/testsuite/gas/riscv/attribute-03.d | 2 +-
gas/testsuite/gas/riscv/attribute-04.d | 2 +-
gas/testsuite/gas/riscv/attribute-05.d | 2 +-
gas/testsuite/gas/riscv/attribute-10.d | 2 +-
gas/testsuite/gas/riscv/mapping-symbols.d | 2 +-
gas/testsuite/gas/riscv/march-imply-a.d | 6 +
gas/testsuite/gas/riscv/march-imply-b.d | 6 +
gas/testsuite/gas/riscv/march-imply-g.d | 2 +-
.../gas/riscv/march-imply-unsupported.d | 2 +-
gas/testsuite/gas/riscv/march-ok-reorder.d | 2 +-
include/opcode/riscv.h | 3 +-
.../ld-riscv-elf/attr-merge-arch-01.d | 2 +-
.../ld-riscv-elf/attr-merge-arch-02.d | 2 +-
.../ld-riscv-elf/attr-merge-arch-03.d | 2 +-
.../ld-riscv-elf/attr-merge-user-ext-01.d | 2 +-
opcodes/riscv-opc.c | 176 +++++++++---------
19 files changed, 132 insertions(+), 107 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/march-imply-a.d
create mode 100644 gas/testsuite/gas/riscv/march-imply-b.d
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 9a121b47121..d608e1a98d2 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1202,6 +1202,11 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"ssstateen", "zicsr", check_implicit_always},
{"sstc", "zicsr", check_implicit_always},
{"svadu", "zicsr", check_implicit_always},
+ {"b", "zba", check_implicit_always},
+ {"b", "zbb", check_implicit_always},
+ {"b", "zbs", check_implicit_always},
+ {"a", "zaamo", check_implicit_always},
+ {"a", "zalrsc", check_implicit_always},
{"xsfvcp", "zve32x", check_implicit_always},
{NULL, NULL, NULL}
@@ -1254,6 +1259,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
{"c", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
+ {"b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"v", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"h", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
@@ -1274,6 +1280,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2435,8 +2443,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "m");
case INSN_CLASS_ZMMUL:
return riscv_subset_supports (rps, "zmmul");
- case INSN_CLASS_A:
- return riscv_subset_supports (rps, "a");
+ case INSN_CLASS_ZAAMO:
+ return riscv_subset_supports (rps, "zaamo");
+ case INSN_CLASS_ZALRSC:
+ return riscv_subset_supports (rps, "zalrsc");
case INSN_CLASS_ZAWRS:
return riscv_subset_supports (rps, "zawrs");
case INSN_CLASS_F:
@@ -2657,8 +2667,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "m";
case INSN_CLASS_ZMMUL:
return _ ("m' or `zmmul");
- case INSN_CLASS_A:
- return "a";
+ case INSN_CLASS_ZAAMO:
+ return "zaamo";
+ case INSN_CLASS_ZALRSC:
+ return "zalrsc";
case INSN_CLASS_ZAWRS:
return "zawrs";
case INSN_CLASS_F:
diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d
index 612305765ab..5615d590866 100644
--- a/gas/testsuite/gas/riscv/attribute-01.d
+++ b/gas/testsuite/gas/riscv/attribute-01.d
@@ -3,4 +3,4 @@
#source: empty.s
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0"
+ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d
index 324fd9f2171..134cc41b825 100644
--- a/gas/testsuite/gas/riscv/attribute-02.d
+++ b/gas/testsuite/gas/riscv/attribute-02.d
@@ -3,4 +3,4 @@
#source: empty.s
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_xargle2p0"
+ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0_xargle2p0"
diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d
index 6e1c2fbc592..70e07e3b55c 100644
--- a/gas/testsuite/gas/riscv/attribute-03.d
+++ b/gas/testsuite/gas/riscv/attribute-03.d
@@ -3,4 +3,4 @@
#source: empty.s
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_xargle2p0_xfoo3p0"
+ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0_xargle2p0_xfoo3p0"
diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d
index f64494a798d..21575b4a632 100644
--- a/gas/testsuite/gas/riscv/attribute-04.d
+++ b/gas/testsuite/gas/riscv/attribute-04.d
@@ -3,4 +3,4 @@
#source: attribute-04.s
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0"
+ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
diff --git a/gas/testsuite/gas/riscv/attribute-05.d b/gas/testsuite/gas/riscv/attribute-05.d
index 9507b43976d..4a2d6ca8c9e 100644
--- a/gas/testsuite/gas/riscv/attribute-05.d
+++ b/gas/testsuite/gas/riscv/attribute-05.d
@@ -4,7 +4,7 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_stack_align: 16-bytes
- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0"
+ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
Tag_RISCV_unaligned_access: Unaligned access
Tag_RISCV_priv_spec: 1
Tag_RISCV_priv_spec_minor: 9
diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d
index f46692275f1..04c322ab1dd 100644
--- a/gas/testsuite/gas/riscv/attribute-10.d
+++ b/gas/testsuite/gas/riscv/attribute-10.d
@@ -3,4 +3,4 @@
#source: empty.s
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0"
+ Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
diff --git a/gas/testsuite/gas/riscv/mapping-symbols.d b/gas/testsuite/gas/riscv/mapping-symbols.d
index 40df3409736..6af825d8ad3 100644
--- a/gas/testsuite/gas/riscv/mapping-symbols.d
+++ b/gas/testsuite/gas/riscv/mapping-symbols.d
@@ -37,7 +37,7 @@ SYMBOL TABLE:
0+04 l .text.last.section 0+00 \$d
0+00 l d .text.section.padding 0+00 .text.section.padding
0+00 l .text.section.padding 0+00 \$xrv32i2p1_c2p0
-0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_c2p0
+0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_c2p0_zaamo1p0_zalrsc1p0
0+06 l .text.section.padding 0+00 \$d
0+00 l d .text.relax.align 0+00 .text.relax.align
0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0
diff --git a/gas/testsuite/gas/riscv/march-imply-a.d b/gas/testsuite/gas/riscv/march-imply-a.d
new file mode 100644
index 00000000000..b2cbfcf8376
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-a.d
@@ -0,0 +1,6 @@
+#as: -march=rv32ia -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0"
diff --git a/gas/testsuite/gas/riscv/march-imply-b.d b/gas/testsuite/gas/riscv/march-imply-b.d
new file mode 100644
index 00000000000..82506c9a3e1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32ib -march-attr -misa-spec=20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
diff --git a/gas/testsuite/gas/riscv/march-imply-g.d b/gas/testsuite/gas/riscv/march-imply-g.d
index 239b717fd7f..7e7a96785bf 100644
--- a/gas/testsuite/gas/riscv/march-imply-g.d
+++ b/gas/testsuite/gas/riscv/march-imply-g.d
@@ -3,4 +3,4 @@
#source: empty.s
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0"
+ Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
diff --git a/gas/testsuite/gas/riscv/march-imply-unsupported.d b/gas/testsuite/gas/riscv/march-imply-unsupported.d
index 612305765ab..5615d590866 100644
--- a/gas/testsuite/gas/riscv/march-imply-unsupported.d
+++ b/gas/testsuite/gas/riscv/march-imply-unsupported.d
@@ -3,4 +3,4 @@
#source: empty.s
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0"
+ Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
diff --git a/gas/testsuite/gas/riscv/march-ok-reorder.d b/gas/testsuite/gas/riscv/march-ok-reorder.d
index 030f8b15018..712c1bdff4d 100644
--- a/gas/testsuite/gas/riscv/march-ok-reorder.d
+++ b/gas/testsuite/gas/riscv/march-ok-reorder.d
@@ -4,4 +4,4 @@
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zba1p0_xbar2p0_xfoo2p0"
+ Tag_RISCV_arch: "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zba1p0_xbar2p0_xfoo2p0"
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index adea7dbc794..1a14a5ecba0 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -407,7 +407,6 @@ enum riscv_insn_class
INSN_CLASS_I,
INSN_CLASS_C,
- INSN_CLASS_A,
INSN_CLASS_M,
INSN_CLASS_F,
INSN_CLASS_D,
@@ -421,6 +420,8 @@ enum riscv_insn_class
INSN_CLASS_ZIHINTNTL_AND_C,
INSN_CLASS_ZIHINTPAUSE,
INSN_CLASS_ZMMUL,
+ INSN_CLASS_ZAAMO,
+ INSN_CLASS_ZALRSC,
INSN_CLASS_ZAWRS,
INSN_CLASS_F_INX,
INSN_CLASS_D_INX,
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index de87f600387..0fb655c7239 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -6,4 +6,4 @@
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p1_a2p0"
+ Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index 381ef850d97..10d01b1b7be 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -6,4 +6,4 @@
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p1_a2p0"
+ Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index 6419fe89791..9649931d937 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -6,4 +6,4 @@
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p1_a2p0_xbar2p0_xfoo2p0"
+ Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0_xbar2p0_xfoo2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d
index f4012dcf90d..d71dd56820e 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d
@@ -6,4 +6,4 @@
Attribute Section: riscv
File Attributes
- Tag_RISCV_arch: "rv32i2p1_a2p1"
+ Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0"
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index fdd05ac75dc..c3a0502f810 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -570,94 +570,94 @@ const struct riscv_opcode riscv_opcodes[] =
{"subw", 64, INSN_CLASS_I, "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 },
/* Atomic memory operation instruction subset. */
-{"lr.w", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"sc.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoadd.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoswap.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoand.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoxor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomax.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomaxu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomin.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amominu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"lr.w.aq", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQ, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"sc.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQ, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoadd.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQ, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoswap.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoand.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQ, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQ, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoxor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQ, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomax.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQ, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomaxu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomin.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQ, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amominu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"lr.w.rl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_RL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"sc.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_RL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoadd.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_RL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoswap.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_RL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoand.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_RL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_RL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoxor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_RL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomax.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_RL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomaxu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_RL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomin.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_RL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amominu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_RL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"lr.w.aqrl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQRL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"sc.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQRL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoadd.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoswap.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoand.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQRL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amoxor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomax.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomaxu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amomin.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"amominu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"lr.d", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"sc.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoadd.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoswap.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoand.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoxor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomax.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomaxu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomin.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amominu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"lr.d.aq", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQ, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"sc.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQ, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoadd.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQ, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoswap.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoand.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQ, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQ, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoxor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQ, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomax.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQ, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomaxu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomin.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQ, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amominu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"lr.d.rl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_RL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"sc.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_RL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoadd.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_RL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoswap.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_RL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoand.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_RL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_RL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoxor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_RL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomax.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_RL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomaxu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_RL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomin.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_RL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amominu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_RL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"lr.d.aqrl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQRL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"sc.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQRL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoadd.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoswap.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoand.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQRL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amoxor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomax.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomaxu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amomin.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"lr.w", 0, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_W, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"sc.w", 0, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_W, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoadd.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoswap.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoand.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoor.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoxor.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomax.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomaxu.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomin.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amominu.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"lr.w.aq", 0, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_W|MASK_AQ, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"sc.w.aq", 0, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_W|MASK_AQ, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoadd.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQ, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoswap.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoand.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQ, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoor.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQ, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoxor.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQ, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomax.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQ, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomaxu.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomin.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQ, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amominu.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"lr.w.rl", 0, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_W|MASK_RL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"sc.w.rl", 0, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_W|MASK_RL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoadd.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W|MASK_RL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoswap.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_RL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoand.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W|MASK_RL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoor.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W|MASK_RL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoxor.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W|MASK_RL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomax.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W|MASK_RL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomaxu.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_RL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomin.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W|MASK_RL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amominu.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W|MASK_RL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"lr.w.aqrl", 0, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_W|MASK_AQRL, MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"sc.w.aqrl", 0, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_W|MASK_AQRL, MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoadd.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoswap.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoand.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoor.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQRL, MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amoxor.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomax.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomaxu.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amomin.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"amominu.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"lr.d", 64, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_D, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"sc.d", 64, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_D, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoadd.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoswap.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoand.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoor.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoxor.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomax.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomaxu.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomin.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amominu.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"lr.d.aq", 64, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_D|MASK_AQ, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"sc.d.aq", 64, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_D|MASK_AQ, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoadd.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQ, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoswap.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoand.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQ, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoor.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQ, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoxor.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQ, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomax.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQ, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomaxu.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomin.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQ, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amominu.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"lr.d.rl", 64, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_D|MASK_RL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"sc.d.rl", 64, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_D|MASK_RL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoadd.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D|MASK_RL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoswap.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_RL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoand.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D|MASK_RL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoor.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D|MASK_RL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoxor.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D|MASK_RL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomax.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D|MASK_RL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomaxu.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_RL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomin.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D|MASK_RL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amominu.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D|MASK_RL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"lr.d.aqrl", 64, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_D|MASK_AQRL, MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"sc.d.aqrl", 64, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_D|MASK_AQRL, MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoadd.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoswap.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoand.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoor.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQRL, MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amoxor.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomax.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomaxu.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amomin.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"amominu.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
/* Multiply/Divide instruction subset. */
{"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS },
--
2.39.3 (Apple Git-145)
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Support B, Zaamo and Zalrsc extensions.
2024-02-05 1:39 [PATCH] RISC-V: Support B, Zaamo and Zalrsc extensions Nelson Chu
@ 2024-05-08 4:37 ` Nelson Chu
2024-05-08 14:34 ` Tom Tromey
0 siblings, 1 reply; 3+ messages in thread
From: Nelson Chu @ 2024-05-08 4:37 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 41398 bytes --]
Committed since these are ratified.
Thanks
Nelson
On Mon, Feb 5, 2024 at 9:39 AM Nelson Chu <nelson@rivosinc.com> wrote:
> * https://github.com/riscv/riscv-b/tags
> Added standard B extension back, which implies Zba, Zbb and Zbs extensions.
>
> * https://github.com/riscv/riscv-zaamo-zalrsc/tags
> Splited standard A extension into two new extensions, Zaamo and Zalrsc.
> The A extension implies Zaamo and Zalrsc extensions.
>
> Not sure if we need to do the similar check as i and zicsr/zifencei.
>
> Passed riscv[32|64]-[elf/linux] binutils testcases.
>
> bfd/
> * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules
> for A and B extensions. The A implies Zaamo and Zalrsc, the
> B implies Zba, Zbb and Zbs.
> (riscv_supported_std_ext): Supported B extension with v1.0.
> (riscv_supported_std_z_ext): Supported Zaamo and Zalrsc with v1.0.
> (riscv_multi_subset_supports, riscv_multi_subset_supports_ext):
> Updated.
> include/
> * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_A, Added
> INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC.
> opcodes/
> * riscv-opc.c (riscv_opcodes): Splited standard A extension into
> two
> new extensions, Zaamo and Zalrsc.
> gas/
> * testsuite/gas/riscv/march-imply-a.d: New testcase.
> * testsuite/gas/riscv/march-imply-b.d: New testcase.
> * testsuite/gas/riscv/attribute-01.d: Updated.
> * testsuite/gas/riscv/attribute-02.d: Updated.
> * testsuite/gas/riscv/attribute-03.d: Updated.
> * testsuite/gas/riscv/attribute-04.d: Updated.
> * testsuite/gas/riscv/attribute-05.d: Updated.
> * testsuite/gas/riscv/attribute-10.d: Updated.
> * testsuite/gas/riscv/mapping-symbols.d: Updated.
> * testsuite/gas/riscv/march-imply-g.d: Updated.
> * testsuite/gas/riscv/march-imply-unsupported.d: Updated.
> * testsuite/gas/riscv/march-ok-reorder.d: Updated.
> ld/
> * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated.
> * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Updated.
> * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Updated.
> * testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Updated.
> ---
> bfd/elfxx-riscv.c | 20 +-
> gas/testsuite/gas/riscv/attribute-01.d | 2 +-
> gas/testsuite/gas/riscv/attribute-02.d | 2 +-
> gas/testsuite/gas/riscv/attribute-03.d | 2 +-
> gas/testsuite/gas/riscv/attribute-04.d | 2 +-
> gas/testsuite/gas/riscv/attribute-05.d | 2 +-
> gas/testsuite/gas/riscv/attribute-10.d | 2 +-
> gas/testsuite/gas/riscv/mapping-symbols.d | 2 +-
> gas/testsuite/gas/riscv/march-imply-a.d | 6 +
> gas/testsuite/gas/riscv/march-imply-b.d | 6 +
> gas/testsuite/gas/riscv/march-imply-g.d | 2 +-
> .../gas/riscv/march-imply-unsupported.d | 2 +-
> gas/testsuite/gas/riscv/march-ok-reorder.d | 2 +-
> include/opcode/riscv.h | 3 +-
> .../ld-riscv-elf/attr-merge-arch-01.d | 2 +-
> .../ld-riscv-elf/attr-merge-arch-02.d | 2 +-
> .../ld-riscv-elf/attr-merge-arch-03.d | 2 +-
> .../ld-riscv-elf/attr-merge-user-ext-01.d | 2 +-
> opcodes/riscv-opc.c | 176 +++++++++---------
> 19 files changed, 132 insertions(+), 107 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/march-imply-a.d
> create mode 100644 gas/testsuite/gas/riscv/march-imply-b.d
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 9a121b47121..d608e1a98d2 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1202,6 +1202,11 @@ static struct riscv_implicit_subset
> riscv_implicit_subsets[] =
> {"ssstateen", "zicsr", check_implicit_always},
> {"sstc", "zicsr", check_implicit_always},
> {"svadu", "zicsr", check_implicit_always},
> + {"b", "zba", check_implicit_always},
> + {"b", "zbb", check_implicit_always},
> + {"b", "zbs", check_implicit_always},
> + {"a", "zaamo", check_implicit_always},
> + {"a", "zalrsc", check_implicit_always},
>
> {"xsfvcp", "zve32x", check_implicit_always},
> {NULL, NULL, NULL}
> @@ -1254,6 +1259,7 @@ static struct riscv_supported_ext
> riscv_supported_std_ext[] =
> {"c", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
> {"c", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> {"c", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
> + {"b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"v", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"h", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {NULL, 0, 0, 0, 0}
> @@ -1274,6 +1280,8 @@ static struct riscv_supported_ext
> riscv_supported_std_z_ext[] =
> {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
> {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -2435,8 +2443,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
> return riscv_subset_supports (rps, "m");
> case INSN_CLASS_ZMMUL:
> return riscv_subset_supports (rps, "zmmul");
> - case INSN_CLASS_A:
> - return riscv_subset_supports (rps, "a");
> + case INSN_CLASS_ZAAMO:
> + return riscv_subset_supports (rps, "zaamo");
> + case INSN_CLASS_ZALRSC:
> + return riscv_subset_supports (rps, "zalrsc");
> case INSN_CLASS_ZAWRS:
> return riscv_subset_supports (rps, "zawrs");
> case INSN_CLASS_F:
> @@ -2657,8 +2667,10 @@ riscv_multi_subset_supports_ext
> (riscv_parse_subset_t *rps,
> return "m";
> case INSN_CLASS_ZMMUL:
> return _ ("m' or `zmmul");
> - case INSN_CLASS_A:
> - return "a";
> + case INSN_CLASS_ZAAMO:
> + return "zaamo";
> + case INSN_CLASS_ZALRSC:
> + return "zalrsc";
> case INSN_CLASS_ZAWRS:
> return "zawrs";
> case INSN_CLASS_F:
> diff --git a/gas/testsuite/gas/riscv/attribute-01.d
> b/gas/testsuite/gas/riscv/attribute-01.d
> index 612305765ab..5615d590866 100644
> --- a/gas/testsuite/gas/riscv/attribute-01.d
> +++ b/gas/testsuite/gas/riscv/attribute-01.d
> @@ -3,4 +3,4 @@
> #source: empty.s
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0"
> + Tag_RISCV_arch:
> "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
> diff --git a/gas/testsuite/gas/riscv/attribute-02.d
> b/gas/testsuite/gas/riscv/attribute-02.d
> index 324fd9f2171..134cc41b825 100644
> --- a/gas/testsuite/gas/riscv/attribute-02.d
> +++ b/gas/testsuite/gas/riscv/attribute-02.d
> @@ -3,4 +3,4 @@
> #source: empty.s
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_xargle2p0"
> + Tag_RISCV_arch:
> "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0_xargle2p0"
> diff --git a/gas/testsuite/gas/riscv/attribute-03.d
> b/gas/testsuite/gas/riscv/attribute-03.d
> index 6e1c2fbc592..70e07e3b55c 100644
> --- a/gas/testsuite/gas/riscv/attribute-03.d
> +++ b/gas/testsuite/gas/riscv/attribute-03.d
> @@ -3,4 +3,4 @@
> #source: empty.s
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch:
> "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_xargle2p0_xfoo3p0"
> + Tag_RISCV_arch:
> "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0_xargle2p0_xfoo3p0"
> diff --git a/gas/testsuite/gas/riscv/attribute-04.d
> b/gas/testsuite/gas/riscv/attribute-04.d
> index f64494a798d..21575b4a632 100644
> --- a/gas/testsuite/gas/riscv/attribute-04.d
> +++ b/gas/testsuite/gas/riscv/attribute-04.d
> @@ -3,4 +3,4 @@
> #source: attribute-04.s
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0"
> + Tag_RISCV_arch:
> "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
> diff --git a/gas/testsuite/gas/riscv/attribute-05.d
> b/gas/testsuite/gas/riscv/attribute-05.d
> index 9507b43976d..4a2d6ca8c9e 100644
> --- a/gas/testsuite/gas/riscv/attribute-05.d
> +++ b/gas/testsuite/gas/riscv/attribute-05.d
> @@ -4,7 +4,7 @@
> Attribute Section: riscv
> File Attributes
> Tag_RISCV_stack_align: 16-bytes
> - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0"
> + Tag_RISCV_arch:
> "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
> Tag_RISCV_unaligned_access: Unaligned access
> Tag_RISCV_priv_spec: 1
> Tag_RISCV_priv_spec_minor: 9
> diff --git a/gas/testsuite/gas/riscv/attribute-10.d
> b/gas/testsuite/gas/riscv/attribute-10.d
> index f46692275f1..04c322ab1dd 100644
> --- a/gas/testsuite/gas/riscv/attribute-10.d
> +++ b/gas/testsuite/gas/riscv/attribute-10.d
> @@ -3,4 +3,4 @@
> #source: empty.s
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch:
> "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0"
> + Tag_RISCV_arch:
> "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
> diff --git a/gas/testsuite/gas/riscv/mapping-symbols.d
> b/gas/testsuite/gas/riscv/mapping-symbols.d
> index 40df3409736..6af825d8ad3 100644
> --- a/gas/testsuite/gas/riscv/mapping-symbols.d
> +++ b/gas/testsuite/gas/riscv/mapping-symbols.d
> @@ -37,7 +37,7 @@ SYMBOL TABLE:
> 0+04 l .text.last.section 0+00 \$d
> 0+00 l d .text.section.padding 0+00 .text.section.padding
> 0+00 l .text.section.padding 0+00 \$xrv32i2p1_c2p0
> -0+04 l .text.section.padding 0+00 \$xrv32i2p1_a2p1_c2p0
> +0+04 l .text.section.padding 0+00
> \$xrv32i2p1_a2p1_c2p0_zaamo1p0_zalrsc1p0
> 0+06 l .text.section.padding 0+00 \$d
> 0+00 l d .text.relax.align 0+00 .text.relax.align
> 0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0
> diff --git a/gas/testsuite/gas/riscv/march-imply-a.d
> b/gas/testsuite/gas/riscv/march-imply-a.d
> new file mode 100644
> index 00000000000..b2cbfcf8376
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-imply-a.d
> @@ -0,0 +1,6 @@
> +#as: -march=rv32ia -march-attr -misa-spec=20191213
> +#readelf: -A
> +#source: empty.s
> +Attribute Section: riscv
> +File Attributes
> + Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-b.d
> b/gas/testsuite/gas/riscv/march-imply-b.d
> new file mode 100644
> index 00000000000..82506c9a3e1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/march-imply-b.d
> @@ -0,0 +1,6 @@
> +#as: -march=rv32ib -march-attr -misa-spec=20191213
> +#readelf: -A
> +#source: empty.s
> +Attribute Section: riscv
> +File Attributes
> + Tag_RISCV_arch: "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-g.d
> b/gas/testsuite/gas/riscv/march-imply-g.d
> index 239b717fd7f..7e7a96785bf 100644
> --- a/gas/testsuite/gas/riscv/march-imply-g.d
> +++ b/gas/testsuite/gas/riscv/march-imply-g.d
> @@ -3,4 +3,4 @@
> #source: empty.s
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch:
> "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0"
> + Tag_RISCV_arch:
> "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
> diff --git a/gas/testsuite/gas/riscv/march-imply-unsupported.d
> b/gas/testsuite/gas/riscv/march-imply-unsupported.d
> index 612305765ab..5615d590866 100644
> --- a/gas/testsuite/gas/riscv/march-imply-unsupported.d
> +++ b/gas/testsuite/gas/riscv/march-imply-unsupported.d
> @@ -3,4 +3,4 @@
> #source: empty.s
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0"
> + Tag_RISCV_arch:
> "rv32i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0_zaamo1p0_zalrsc1p0"
> diff --git a/gas/testsuite/gas/riscv/march-ok-reorder.d
> b/gas/testsuite/gas/riscv/march-ok-reorder.d
> index 030f8b15018..712c1bdff4d 100644
> --- a/gas/testsuite/gas/riscv/march-ok-reorder.d
> +++ b/gas/testsuite/gas/riscv/march-ok-reorder.d
> @@ -4,4 +4,4 @@
>
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch:
> "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zba1p0_xbar2p0_xfoo2p0"
> + Tag_RISCV_arch:
> "rv32i2p0_m1p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zba1p0_xbar2p0_xfoo2p0"
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index adea7dbc794..1a14a5ecba0 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -407,7 +407,6 @@ enum riscv_insn_class
>
> INSN_CLASS_I,
> INSN_CLASS_C,
> - INSN_CLASS_A,
> INSN_CLASS_M,
> INSN_CLASS_F,
> INSN_CLASS_D,
> @@ -421,6 +420,8 @@ enum riscv_insn_class
> INSN_CLASS_ZIHINTNTL_AND_C,
> INSN_CLASS_ZIHINTPAUSE,
> INSN_CLASS_ZMMUL,
> + INSN_CLASS_ZAAMO,
> + INSN_CLASS_ZALRSC,
> INSN_CLASS_ZAWRS,
> INSN_CLASS_F_INX,
> INSN_CLASS_D_INX,
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
> b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
> index de87f600387..0fb655c7239 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
> @@ -6,4 +6,4 @@
>
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p1_a2p0"
> + Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
> b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
> index 381ef850d97..10d01b1b7be 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
> @@ -6,4 +6,4 @@
>
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p1_a2p0"
> + Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
> b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
> index 6419fe89791..9649931d937 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
> @@ -6,4 +6,4 @@
>
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p1_a2p0_xbar2p0_xfoo2p0"
> + Tag_RISCV_arch: "rv32i2p1_a2p0_zaamo1p0_zalrsc1p0_xbar2p0_xfoo2p0"
> diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d
> b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d
> index f4012dcf90d..d71dd56820e 100644
> --- a/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d
> +++ b/ld/testsuite/ld-riscv-elf/attr-merge-user-ext-01.d
> @@ -6,4 +6,4 @@
>
> Attribute Section: riscv
> File Attributes
> - Tag_RISCV_arch: "rv32i2p1_a2p1"
> + Tag_RISCV_arch: "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0"
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index fdd05ac75dc..c3a0502f810 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -570,94 +570,94 @@ const struct riscv_opcode riscv_opcodes[] =
> {"subw", 64, INSN_CLASS_I, "d,s,t", MATCH_SUBW, MASK_SUBW,
> match_opcode, 0 },
>
> /* Atomic memory operation instruction subset. */
> -{"lr.w", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W,
> MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"sc.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W,
> MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoadd.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W,
> MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoswap.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W,
> MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoand.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W,
> MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W,
> MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoxor.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W,
> MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amomax.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W,
> MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amomaxu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W,
> MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amomin.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W,
> MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amominu.w", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W,
> MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"lr.w.aq", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQ,
> MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"sc.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQ,
> MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoadd.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_AQ,
> MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoswap.w.aq", 0, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> -{"amoand.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_AQ,
> MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQ,
> MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoxor.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_AQ,
> MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amomax.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_AQ,
> MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amomaxu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> -{"amomin.w.aq", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_AQ,
> MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amominu.w.aq", 0, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> -{"lr.w.rl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_RL,
> MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"sc.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_RL,
> MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoadd.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_W|MASK_RL,
> MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoswap.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_W|MASK_RL,
> MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoand.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_W|MASK_RL,
> MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_RL,
> MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoxor.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_W|MASK_RL,
> MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amomax.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_W|MASK_RL,
> MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amomaxu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_W|MASK_RL,
> MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amomin.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_W|MASK_RL,
> MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amominu.w.rl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_W|MASK_RL,
> MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"lr.w.aqrl", 0, INSN_CLASS_A, "d,0(s)", MATCH_LR_W|MASK_AQRL,
> MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"sc.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_W|MASK_AQRL,
> MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoadd.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> -{"amoswap.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> -{"amoand.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> -{"amoor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_W|MASK_AQRL,
> MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> -{"amoxor.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> -{"amomax.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> -{"amomaxu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> -{"amomin.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> -{"amominu.w.aqrl", 0, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> -{"lr.d", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D,
> MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"sc.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D,
> MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoadd.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D,
> MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoswap.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D,
> MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoand.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D,
> MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D,
> MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoxor.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D,
> MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amomax.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D,
> MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amomaxu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D,
> MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amomin.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D,
> MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amominu.d", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D,
> MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"lr.d.aq", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQ,
> MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"sc.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQ,
> MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoadd.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_AQ,
> MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoswap.d.aq", 64, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> -{"amoand.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_AQ,
> MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQ,
> MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoxor.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_AQ,
> MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amomax.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_AQ,
> MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amomaxu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> -{"amomin.d.aq", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQ,
> MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amominu.d.aq", 64, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> -{"lr.d.rl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_RL,
> MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"sc.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_RL,
> MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoadd.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOADD_D|MASK_RL,
> MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoswap.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOSWAP_D|MASK_RL,
> MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoand.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOAND_D|MASK_RL,
> MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_RL,
> MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoxor.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOXOR_D|MASK_RL,
> MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amomax.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAX_D|MASK_RL,
> MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amomaxu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMAXU_D|MASK_RL,
> MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amomin.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_RL,
> MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amominu.d.rl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_RL,
> MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"lr.d.aqrl", 64, INSN_CLASS_A, "d,0(s)", MATCH_LR_D|MASK_AQRL,
> MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"sc.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_SC_D|MASK_AQRL,
> MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoadd.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> -{"amoswap.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> -{"amoand.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> -{"amoor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOOR_D|MASK_AQRL,
> MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> -{"amoxor.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> -{"amomax.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> -{"amomaxu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> -{"amomin.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> -{"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)",
> MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"lr.w", 0, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_W,
> MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"sc.w", 0, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_W,
> MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amoadd.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_W,
> MASK_AMOADD_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amoswap.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_W,
> MASK_AMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amoand.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_W,
> MASK_AMOAND_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amoor.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_W,
> MASK_AMOOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amoxor.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_W,
> MASK_AMOXOR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amomax.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_W,
> MASK_AMOMAX_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amomaxu.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_W,
> MASK_AMOMAXU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amomin.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_W,
> MASK_AMOMIN_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amominu.w", 0, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_W,
> MASK_AMOMINU_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"lr.w.aq", 0, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_W|MASK_AQ,
> MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"sc.w.aq", 0, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_W|MASK_AQ,
> MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amoadd.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOADD_W|MASK_AQ, MASK_AMOADD_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoswap.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOSWAP_W|MASK_AQ, MASK_AMOSWAP_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoand.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOAND_W|MASK_AQ, MASK_AMOAND_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoor.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOOR_W|MASK_AQ, MASK_AMOOR_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoxor.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOXOR_W|MASK_AQ, MASK_AMOXOR_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amomax.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAX_W|MASK_AQ, MASK_AMOMAX_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amomaxu.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAXU_W|MASK_AQ, MASK_AMOMAXU_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amomin.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMIN_W|MASK_AQ, MASK_AMOMIN_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amominu.w.aq", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMINU_W|MASK_AQ, MASK_AMOMINU_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"lr.w.rl", 0, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_W|MASK_RL,
> MASK_LR_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"sc.w.rl", 0, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_W|MASK_RL,
> MASK_SC_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
> +{"amoadd.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOADD_W|MASK_RL, MASK_AMOADD_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoswap.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOSWAP_W|MASK_RL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoand.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOAND_W|MASK_RL, MASK_AMOAND_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoor.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOOR_W|MASK_RL, MASK_AMOOR_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoxor.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOXOR_W|MASK_RL, MASK_AMOXOR_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amomax.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAX_W|MASK_RL, MASK_AMOMAX_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amomaxu.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAXU_W|MASK_RL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amomin.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMIN_W|MASK_RL, MASK_AMOMIN_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amominu.w.rl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMINU_W|MASK_RL, MASK_AMOMINU_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"lr.w.aqrl", 0, INSN_CLASS_ZALRSC,"d,0(s)",
> MATCH_LR_W|MASK_AQRL, MASK_LR_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"sc.w.aqrl", 0, INSN_CLASS_ZALRSC,"d,t,0(s)",
> MATCH_SC_W|MASK_AQRL, MASK_SC_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoadd.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOADD_W|MASK_AQRL, MASK_AMOADD_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoswap.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOSWAP_W|MASK_AQRL, MASK_AMOSWAP_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoand.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOAND_W|MASK_AQRL, MASK_AMOAND_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoor.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOOR_W|MASK_AQRL, MASK_AMOOR_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amoxor.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOXOR_W|MASK_AQRL, MASK_AMOXOR_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amomax.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAX_W|MASK_AQRL, MASK_AMOMAX_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amomaxu.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAXU_W|MASK_AQRL, MASK_AMOMAXU_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amomin.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMIN_W|MASK_AQRL, MASK_AMOMIN_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"amominu.w.aqrl", 0, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMINU_W|MASK_AQRL, MASK_AMOMINU_W|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_4_BYTE },
> +{"lr.d", 64, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_D,
> MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"sc.d", 64, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_D,
> MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"amoadd.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOADD_D,
> MASK_AMOADD_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"amoswap.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOSWAP_D,
> MASK_AMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"amoand.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOAND_D,
> MASK_AMOAND_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"amoor.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOOR_D,
> MASK_AMOOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"amoxor.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOXOR_D,
> MASK_AMOXOR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"amomax.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAX_D,
> MASK_AMOMAX_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"amomaxu.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMAXU_D,
> MASK_AMOMAXU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"amomin.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMIN_D,
> MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"amominu.d", 64, INSN_CLASS_ZAAMO, "d,t,0(s)", MATCH_AMOMINU_D,
> MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"lr.d.aq", 64, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_D|MASK_AQ,
> MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"sc.d.aq", 64, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_D|MASK_AQ,
> MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"amoadd.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOADD_D|MASK_AQ, MASK_AMOADD_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoswap.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOSWAP_D|MASK_AQ, MASK_AMOSWAP_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoand.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOAND_D|MASK_AQ, MASK_AMOAND_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoor.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOOR_D|MASK_AQ, MASK_AMOOR_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoxor.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOXOR_D|MASK_AQ, MASK_AMOXOR_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amomax.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAX_D|MASK_AQ, MASK_AMOMAX_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amomaxu.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAXU_D|MASK_AQ, MASK_AMOMAXU_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amomin.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMIN_D|MASK_AQ, MASK_AMOMIN_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amominu.d.aq", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMINU_D|MASK_AQ, MASK_AMOMINU_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"lr.d.rl", 64, INSN_CLASS_ZALRSC,"d,0(s)", MATCH_LR_D|MASK_RL,
> MASK_LR_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"sc.d.rl", 64, INSN_CLASS_ZALRSC,"d,t,0(s)", MATCH_SC_D|MASK_RL,
> MASK_SC_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
> +{"amoadd.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOADD_D|MASK_RL, MASK_AMOADD_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoswap.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOSWAP_D|MASK_RL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoand.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOAND_D|MASK_RL, MASK_AMOAND_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoor.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOOR_D|MASK_RL, MASK_AMOOR_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoxor.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOXOR_D|MASK_RL, MASK_AMOXOR_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amomax.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAX_D|MASK_RL, MASK_AMOMAX_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amomaxu.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAXU_D|MASK_RL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amomin.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMIN_D|MASK_RL, MASK_AMOMIN_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amominu.d.rl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMINU_D|MASK_RL, MASK_AMOMINU_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"lr.d.aqrl", 64, INSN_CLASS_ZALRSC,"d,0(s)",
> MATCH_LR_D|MASK_AQRL, MASK_LR_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"sc.d.aqrl", 64, INSN_CLASS_ZALRSC,"d,t,0(s)",
> MATCH_SC_D|MASK_AQRL, MASK_SC_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoadd.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOADD_D|MASK_AQRL, MASK_AMOADD_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoswap.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOSWAP_D|MASK_AQRL, MASK_AMOSWAP_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoand.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOAND_D|MASK_AQRL, MASK_AMOAND_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoor.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOOR_D|MASK_AQRL, MASK_AMOOR_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amoxor.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOXOR_D|MASK_AQRL, MASK_AMOXOR_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amomax.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAX_D|MASK_AQRL, MASK_AMOMAX_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amomaxu.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMAXU_D|MASK_AQRL, MASK_AMOMAXU_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amomin.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
> +{"amominu.d.aqrl", 64, INSN_CLASS_ZAAMO, "d,t,0(s)",
> MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode,
> INSN_DREF|INSN_8_BYTE },
>
> /* Multiply/Divide instruction subset. */
> {"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL,
> MASK_C_MUL, match_opcode, INSN_ALIAS },
> --
> 2.39.3 (Apple Git-145)
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Support B, Zaamo and Zalrsc extensions.
2024-05-08 4:37 ` Nelson Chu
@ 2024-05-08 14:34 ` Tom Tromey
0 siblings, 0 replies; 3+ messages in thread
From: Tom Tromey @ 2024-05-08 14:34 UTC (permalink / raw)
To: Nelson Chu; +Cc: binutils
>>>>> Nelson Chu <nelson@rivosinc.com> writes:
> Committed since these are ratified.
Hi. This seems to have broken the sim build:
../../binutils-gdb/sim/riscv/sim-main.c: In function ‘execute_one’:
../../binutils-gdb/sim/riscv/sim-main.c:1302:10: error: ‘INSN_CLASS_A’ undeclared (first use in this function); did you mean ‘INSN_CLASS_H’?
1302 | case INSN_CLASS_A:
| ^~~~~~~~~~~~
| INSN_CLASS_H
../../binutils-gdb/sim/riscv/sim-main.c:1302:10: note: each undeclared identifier is reported only once for each function it appears in
Tom
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-02-05 1:39 [PATCH] RISC-V: Support B, Zaamo and Zalrsc extensions Nelson Chu
2024-05-08 4:37 ` Nelson Chu
2024-05-08 14:34 ` Tom Tromey
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