From: Victor Do Nascimento <victor.donascimento@arm.com>
To: <binutils@sourceware.org>
Cc: <richard.earnshaw@arm.com>, <nickc@redhat.com>,
Victor Do Nascimento <vicdon01@e133397.arm.com>
Subject: [PATCH 1/4] aarch64: fp8 convert and scale - add feature flags and related structures
Date: Wed, 10 Apr 2024 16:29:47 +0100 [thread overview]
Message-ID: <20240410152950.1134020-2-victor.donascimento@arm.com> (raw)
In-Reply-To: <20240410152950.1134020-1-victor.donascimento@arm.com>
From: Victor Do Nascimento <vicdon01@e133397.arm.com>
---
gas/config/tc-aarch64.c | 1 +
gas/doc/c-aarch64.texi | 2 ++
include/opcode/aarch64.h | 2 ++
opcodes/aarch64-tbl.h | 18 ++++++++++++++++++
4 files changed, 23 insertions(+)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 6ad4fae8b0e..20188b9aed2 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10477,6 +10477,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
{"cpa", AARCH64_FEATURE (CPA), AARCH64_NO_FEATURES},
{"faminmax", AARCH64_FEATURE (FAMINMAX), AARCH64_FEATURE (SIMD)},
+ {"fp8", AARCH64_FEATURE (FP8), AARCH64_FEATURE (SIMD)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 3756948bfb8..4da18077f1b 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -291,6 +291,8 @@ automatically cause those extensions to be disabled.
@tab Enable the XS memory attribute extension.
@item @code{cpa} @tab
@tab Enable the Checked Pointer Arithmetic extension.
+@item @code{fp8} @tab
+ @tab Enable the Floating Point 8 (FP8) extension.
@end multitable
@multitable @columnfractions .20 .80
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 2fca9528c20..a50554a4dc7 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -232,6 +232,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_CPA,
/* FAMINMAX instructions. */
AARCH64_FEATURE_FAMINMAX,
+ /* FP8 instructions. */
+ AARCH64_FEATURE_FP8,
AARCH64_NUM_FEATURES
};
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 356d303bc1a..7e603462a37 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2669,6 +2669,13 @@ static const aarch64_feature_set aarch64_feature_faminmax_sve2 =
AARCH64_FEATURES (2, FAMINMAX, SVE2);
static const aarch64_feature_set aarch64_feature_faminmax_sme2 =
AARCH64_FEATURES (3, SVE2, FAMINMAX, SME2);
+static const aarch64_feature_set aarch64_feature_fp8 =
+ AARCH64_FEATURE (FP8);
+static const aarch64_feature_set aarch64_feature_fp8_sve2 =
+ AARCH64_FEATURES (2, FP8, SVE2);
+static const aarch64_feature_set aarch64_feature_fp8_sme2 =
+ AARCH64_FEATURES (2, FP8, SME2);
+
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2740,6 +2747,9 @@ static const aarch64_feature_set aarch64_feature_faminmax_sme2 =
#define FAMINMAX &aarch64_feature_faminmax
#define FAMINMAX_SVE2 &aarch64_feature_faminmax_sve2
#define FAMINMAX_SME2 &aarch64_feature_faminmax_sme2
+#define FP8 &aarch64_feature_fp8
+#define FP8_SVE2 &aarch64_feature_fp8_sve2
+#define FP8_SME2 &aarch64_feature_fp8_sme2
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2925,6 +2935,14 @@ static const aarch64_feature_set aarch64_feature_faminmax_sme2 =
#define FAMINMAX_SME2_INSN(NAME,OPCODE,MASK,OPS,QUALS) \
{ NAME, OPCODE, MASK, sme_size_22_hsd, 0, FAMINMAX_SME2, OPS, QUALS, \
F_STRICT | 0, 0, 1, NULL }
+#define FP8_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP8, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define FP8_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, FP8_SVE2, OPS, QUALS, \
+ FLAGS | F_STRICT, 0, TIED, NULL }
+#define FP8_SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, FP8_SME2, OPS, QUALS, \
+ F_STRICT | FLAGS, 0, TIED, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
--
2.34.1
next prev parent reply other threads:[~2024-04-10 15:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-10 15:29 [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Victor Do Nascimento
2024-04-10 15:29 ` Victor Do Nascimento [this message]
2024-04-10 15:29 ` [PATCH 2/4] aarch64: fp8 convert and scale - Add advsimd insn variants Victor Do Nascimento
2024-05-17 15:43 ` Richard Earnshaw (lists)
2024-05-20 15:36 ` Andrew Carlotti
2024-04-10 15:29 ` [PATCH 3/4] aarch64: fp8 convert and scale - add sve2 " Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 4/4] aarch64: fp8 convert and scale - add sme2 " Victor Do Nascimento
2024-04-17 9:50 ` [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Nick Clifton
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