From: Victor Do Nascimento <victor.donascimento@arm.com>
To: <binutils@sourceware.org>
Cc: <richard.earnshaw@arm.com>, <nickc@redhat.com>,
Victor Do Nascimento <vicdon01@e133397.arm.com>
Subject: [PATCH 4/4] aarch64: fp8 convert and scale - add sme2 insn variants
Date: Wed, 10 Apr 2024 16:29:50 +0100 [thread overview]
Message-ID: <20240410152950.1134020-5-victor.donascimento@arm.com> (raw)
In-Reply-To: <20240410152950.1134020-1-victor.donascimento@arm.com>
From: Victor Do Nascimento <vicdon01@e133397.arm.com>
Add the SME2 variant of the FP8 convert and scale
instructions, enabled at assembly-time using the `+sme2+fp8'
architectural extension flag. More specifically, support is
added for the following instructions:
Multi-vector floating-point convert from FP8 to
BFloat16 (in-order):
-----------------------------------------------
- bf1cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
- bf2cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from FP8 to
deinterleaved BFloat16:
-----------------------------------------------
- bf1cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
- bf2cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from BFloat16
to packed FP8 format:
-------------------------------------------------
- bfcvt <Zd>.B, { <Zn1>.H-<Zn2>.H }
Multi-vector floating-point convert from FP8 to
half-precision (in-order):
-----------------------------------------------
- f1cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
- f2cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from FP8 to
deinterleaved half-precision:
-----------------------------------------------
- f1cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
- f2cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
Multi-vector floating-point convert from half-precision
to packed FP8 format:
-------------------------------------------------------
fcvt_2h
Multi-vector floating-point convert from single-precision
to packed FP8 format:
---------------------------------------------------------
fcvt_4s
Multi-vector floating-point convert from single-precision
to interleaved FP8 format:
---------------------------------------------------------
- fcvtn <Zd>.B, { <Zn1>.S-<Zn4>.S }
Multi-vector floating-point adjust exponent by vector:
------------------------------------------------------
- fscale { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H },
<Zm>.H
- fscale { <Zdn1>.S-<Zdn2>.S }, { <Zdn1>.S-<Zdn2>.S },
<Zm>.S
- fscale { <Zdn1>.D-<Zdn2>.D }, { <Zdn1>.D-<Zdn2>.D },
<Zm>.D
Multi-vector floating-point adjust exponent:
--------------------------------------------
- fscale { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H },
{ <Zm1>.H - <Zm2>.H }
- fscale { <Zdn1>.S-<Zdn2>.S }, { <Zdn1>.S-<Zdn2>.S },
{ <Zm1>.S - <Zm2>.S }
- fscale { <Zdn1>.D-<Zdn2>.D }, { <Zdn1>.D-<Zdn2>.D },
{ <Zm1>.D - <Zm2>.D }
---
gas/testsuite/gas/aarch64/sme2-24-invalid.l | 4 +-
gas/testsuite/gas/aarch64/sme2-fp8-fail.d | 2 +
gas/testsuite/gas/aarch64/sme2-fp8-fail.l | 273 ++++++++++++
gas/testsuite/gas/aarch64/sme2-fp8-fail.s | 106 +++++
gas/testsuite/gas/aarch64/sme2-fp8.d | 128 ++++++
gas/testsuite/gas/aarch64/sme2-fp8.s | 112 +++++
opcodes/aarch64-dis-2.c | 448 ++++++++++++++------
opcodes/aarch64-tbl.h | 16 +
8 files changed, 951 insertions(+), 138 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.d
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.l
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8-fail.s
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8.d
create mode 100644 gas/testsuite/gas/aarch64/sme2-fp8.s
diff --git a/gas/testsuite/gas/aarch64/sme2-24-invalid.l b/gas/testsuite/gas/aarch64/sme2-24-invalid.l
index c44a582979d..82dd0fb1308 100644
--- a/gas/testsuite/gas/aarch64/sme2-24-invalid.l
+++ b/gas/testsuite/gas/aarch64/sme2-24-invalid.l
@@ -9,10 +9,10 @@
[^ :]+:[0-9]+: Info: bfcvtn z0\.h, {z0\.s-z3\.s}
[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt z0\.s,{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: bfcvt z0\.h, {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Info: bfcvt z0\.b, {z0\.h-z3\.h}
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvt z0\.s,{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: fcvt z0\.h, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info: fcvt z0\.b, {z0\.h-z1\.h}
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvt z0\.s,{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvt z0\.h, {z0\.s-z1\.s}
diff --git a/gas/testsuite/gas/aarch64/sme2-fp8-fail.d b/gas/testsuite/gas/aarch64/sme2-fp8-fail.d
new file mode 100644
index 00000000000..79f139c2353
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8-fail.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.5-a+fp8+sme2 -mno-verbose-error
+#error_output: sme2-fp8-fail.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sme2-fp8-fail.l b/gas/testsuite/gas/aarch64/sme2-fp8-fail.l
new file mode 100644
index 00000000000..f25fd60b1bd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8-fail.l
@@ -0,0 +1,273 @@
+[^:]+: Assembler messages:
+[^:]+:7: Error: operand mismatch -- `bf1cvt {z0.h-z1.h},z2.h'
+[^:]+:19: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf1cvt {z0.h-z1.h},z2.s'
+[^:]+:19: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf1cvt {z0.h-z1.h},z2.d'
+[^:]+:19: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf1cvt {z0.b-z1.b},z2.b'
+[^:]+:19: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf1cvt {z0.s-z1.s},z2.b'
+[^:]+:19: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf1cvt {z0.d-z1.d},z2.b'
+[^:]+:19: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `bf1cvt {z1.h-z2.h},z2.b'
+[^:]+:19: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `bf2cvt {z0.h-z1.h},z2.h'
+[^:]+:20: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf2cvt {z0.h-z1.h},z2.s'
+[^:]+:20: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf2cvt {z0.h-z1.h},z2.d'
+[^:]+:20: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf2cvt {z0.b-z1.b},z2.b'
+[^:]+:20: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf2cvt {z0.s-z1.s},z2.b'
+[^:]+:20: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf2cvt {z0.d-z1.d},z2.b'
+[^:]+:20: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `bf2cvt {z1.h-z2.h},z2.b'
+[^:]+:20: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `bf1cvtl {z0.h-z1.h},z2.h'
+[^:]+:21: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf1cvtl {z0.h-z1.h},z2.s'
+[^:]+:21: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf1cvtl {z0.h-z1.h},z2.d'
+[^:]+:21: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf1cvtl {z0.b-z1.b},z2.b'
+[^:]+:21: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf1cvtl {z0.s-z1.s},z2.b'
+[^:]+:21: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf1cvtl {z0.d-z1.d},z2.b'
+[^:]+:21: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `bf1cvtl {z1.h-z2.h},z2.b'
+[^:]+:21: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `bf2cvtl {z0.h-z1.h},z2.h'
+[^:]+:22: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf2cvtl {z0.h-z1.h},z2.s'
+[^:]+:22: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf2cvtl {z0.h-z1.h},z2.d'
+[^:]+:22: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf2cvtl {z0.b-z1.b},z2.b'
+[^:]+:22: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf2cvtl {z0.s-z1.s},z2.b'
+[^:]+:22: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf2cvtl {z0.d-z1.d},z2.b'
+[^:]+:22: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `bf2cvtl {z1.h-z2.h},z2.b'
+[^:]+:22: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `f1cvt {z0.h-z1.h},z2.h'
+[^:]+:23: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f1cvt {z0.h-z1.h},z2.s'
+[^:]+:23: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f1cvt {z0.h-z1.h},z2.d'
+[^:]+:23: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f1cvt {z0.b-z1.b},z2.b'
+[^:]+:23: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f1cvt {z0.s-z1.s},z2.b'
+[^:]+:23: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f1cvt {z0.d-z1.d},z2.b'
+[^:]+:23: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `f1cvt {z1.h-z2.h},z2.b'
+[^:]+:23: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `f2cvt {z0.h-z1.h},z2.h'
+[^:]+:24: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f2cvt {z0.h-z1.h},z2.s'
+[^:]+:24: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f2cvt {z0.h-z1.h},z2.d'
+[^:]+:24: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f2cvt {z0.b-z1.b},z2.b'
+[^:]+:24: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f2cvt {z0.s-z1.s},z2.b'
+[^:]+:24: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f2cvt {z0.d-z1.d},z2.b'
+[^:]+:24: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `f2cvt {z1.h-z2.h},z2.b'
+[^:]+:24: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `f1cvtl {z0.h-z1.h},z2.h'
+[^:]+:25: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f1cvtl {z0.h-z1.h},z2.s'
+[^:]+:25: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f1cvtl {z0.h-z1.h},z2.d'
+[^:]+:25: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f1cvtl {z0.b-z1.b},z2.b'
+[^:]+:25: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f1cvtl {z0.s-z1.s},z2.b'
+[^:]+:25: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f1cvtl {z0.d-z1.d},z2.b'
+[^:]+:25: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `f1cvtl {z1.h-z2.h},z2.b'
+[^:]+:25: Info: macro invoked from here
+[^:]+:7: Error: operand mismatch -- `f2cvtl {z0.h-z1.h},z2.h'
+[^:]+:26: Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f2cvtl {z0.h-z1.h},z2.s'
+[^:]+:26: Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f2cvtl {z0.h-z1.h},z2.d'
+[^:]+:26: Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f2cvtl {z0.b-z1.b},z2.b'
+[^:]+:26: Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f2cvtl {z0.s-z1.s},z2.b'
+[^:]+:26: Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f2cvtl {z0.d-z1.d},z2.b'
+[^:]+:26: Info: macro invoked from here
+[^:]+:16: Error: start register out of range at operand 1 -- `f2cvtl {z1.h-z2.h},z2.b'
+[^:]+:26: Info: macro invoked from here
+[^:]+:31: Error: operand mismatch -- `bfcvt z2.h,{z0.h-z1.h}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:32: Error: operand mismatch -- `bfcvt z2.s,{z0.h-z1.h}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:33: Error: operand mismatch -- `bfcvt z2.d,{z0.h-z1.h}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:35: Error: operand mismatch -- `bfcvt z2.b,{z0.b-z1.b}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:37: Error: operand mismatch -- `bfcvt z2.b,{z0.s-z1.s}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `bfcvt z2.b,{z0.d-z1.d}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:40: Error: start register out of range at operand 2 -- `bfcvt z2.b,{z1.h-z2.h}'
+[^:]+:43: Info: macro invoked from here
+[^:]+:31: Error: operand mismatch -- `fcvt z2.h,{z0.h-z1.h}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:32: Error: operand mismatch -- `fcvt z2.s,{z0.h-z1.h}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:33: Error: operand mismatch -- `fcvt z2.d,{z0.h-z1.h}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:35: Error: operand mismatch -- `fcvt z2.b,{z0.b-z1.b}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:37: Error: expected a list of 4 registers at operand 2 -- `fcvt z2.b,{z0.s-z1.s}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `fcvt z2.b,{z0.d-z1.d}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:40: Error: start register out of range at operand 2 -- `fcvt z2.b,{z1.h-z2.h}'
+[^:]+:44: Info: macro invoked from here
+[^:]+:49: Error: expected a list of 2 registers at operand 2 -- `fcvtn z4.h,{z0.s-z3.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `fcvtn z4.s,{z0.s-z3.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `fcvtn z4.d,{z0.s-z3.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:53: Error: operand mismatch -- `fcvtn z4.b,{z0.b-z3.b}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:54: Error: expected a list of 2 registers at operand 2 -- `fcvtn z4.b,{z0.h-z3.h}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:56: Error: operand mismatch -- `fcvtn z4.b,{z0.d-z3.d}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:58: Error: start register out of range at operand 2 -- `fcvtn z4.b,{z1.s-z4.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:59: Error: start register out of range at operand 2 -- `fcvtn z4.b,{z2.s-z5.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:60: Error: start register out of range at operand 2 -- `fcvtn z4.b,{z3.s-z6.s}'
+[^:]+:63: Info: macro invoked from here
+[^:]+:49: Error: expected a list of 2 registers at operand 2 -- `fcvt z4.h,{z0.s-z3.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `fcvt z4.s,{z0.s-z3.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `fcvt z4.d,{z0.s-z3.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:53: Error: operand mismatch -- `fcvt z4.b,{z0.b-z3.b}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:54: Error: expected a list of 2 registers at operand 2 -- `fcvt z4.b,{z0.h-z3.h}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:56: Error: operand mismatch -- `fcvt z4.b,{z0.d-z3.d}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:58: Error: start register out of range at operand 2 -- `fcvt z4.b,{z1.s-z4.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:59: Error: start register out of range at operand 2 -- `fcvt z4.b,{z2.s-z5.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:60: Error: start register out of range at operand 2 -- `fcvt z4.b,{z3.s-z6.s}'
+[^:]+:64: Info: macro invoked from here
+[^:]+:69: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.h-z1.h},{z2.h-z3.h},z2.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:71: Error: start register out of range at operand 1 -- `fscale {z1.h-z2.h},{z1.h-z2.h},z3.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:74: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.h-z3.h},{z1.h-z4.h},z4.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:76: Error: start register out of range at operand 1 -- `fscale {z1.h-z4.h},{z1.h-z4.h},z4.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:77: Error: start register out of range at operand 1 -- `fscale {z2.h-z5.h},{z2.h-z5.h},z4.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:78: Error: start register out of range at operand 1 -- `fscale {z3.h-z6.h},{z3.h-z6.h},z4.h'
+[^:]+:81: Info: macro invoked from here
+[^:]+:69: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.s-z1.s},{z2.s-z3.s},z2.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:71: Error: start register out of range at operand 1 -- `fscale {z1.s-z2.s},{z1.s-z2.s},z3.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:74: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.s-z3.s},{z1.s-z4.s},z4.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:76: Error: start register out of range at operand 1 -- `fscale {z1.s-z4.s},{z1.s-z4.s},z4.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:77: Error: start register out of range at operand 1 -- `fscale {z2.s-z5.s},{z2.s-z5.s},z4.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:78: Error: start register out of range at operand 1 -- `fscale {z3.s-z6.s},{z3.s-z6.s},z4.s'
+[^:]+:82: Info: macro invoked from here
+[^:]+:69: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.d-z1.d},{z2.d-z3.d},z2.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:71: Error: start register out of range at operand 1 -- `fscale {z1.d-z2.d},{z1.d-z2.d},z3.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:74: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.d-z3.d},{z1.d-z4.d},z4.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:76: Error: start register out of range at operand 1 -- `fscale {z1.d-z4.d},{z1.d-z4.d},z4.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:77: Error: start register out of range at operand 1 -- `fscale {z2.d-z5.d},{z2.d-z5.d},z4.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:78: Error: start register out of range at operand 1 -- `fscale {z3.d-z6.d},{z3.d-z6.d},z4.d'
+[^:]+:83: Info: macro invoked from here
+[^:]+:88: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.h-z1.h},{z1.h-z2.h},{z2.h-z3.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:90: Error: start register out of range at operand 1 -- `fscale {z1.h-z2.h},{z1.h-z2.h},{z2.h-z3.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:91: Error: start register out of range at operand 1 -- `fscale {z1.h-z2.h},{z1.h-z2.h},{z3.h-z4.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:94: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.h-z3.h},{z1.h-z4.h},{z4.h-z7.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:96: Error: start register out of range at operand 1 -- `fscale {z1.h-z4.h},{z1.h-z4.h},{z4.h-z7.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:97: Error: start register out of range at operand 1 -- `fscale {z2.h-z5.h},{z2.h-z5.h},{z4.h-z7.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:98: Error: start register out of range at operand 1 -- `fscale {z3.h-z6.h},{z3.h-z6.h},{z4.h-z7.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:99: Error: start register out of range at operand 3 -- `fscale {z0.h-z3.h},{z0.h-z3.h},{z5.h-z8.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:100: Error: start register out of range at operand 3 -- `fscale {z0.h-z3.h},{z0.h-z3.h},{z6.h-z9.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:101: Error: start register out of range at operand 3 -- `fscale {z0.h-z3.h},{z0.h-z3.h},{z7.h-z10.h}'
+[^:]+:104: Info: macro invoked from here
+[^:]+:88: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.s-z1.s},{z1.s-z2.s},{z2.s-z3.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:90: Error: start register out of range at operand 1 -- `fscale {z1.s-z2.s},{z1.s-z2.s},{z2.s-z3.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:91: Error: start register out of range at operand 1 -- `fscale {z1.s-z2.s},{z1.s-z2.s},{z3.s-z4.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:94: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.s-z3.s},{z1.s-z4.s},{z4.s-z7.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:96: Error: start register out of range at operand 1 -- `fscale {z1.s-z4.s},{z1.s-z4.s},{z4.s-z7.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:97: Error: start register out of range at operand 1 -- `fscale {z2.s-z5.s},{z2.s-z5.s},{z4.s-z7.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:98: Error: start register out of range at operand 1 -- `fscale {z3.s-z6.s},{z3.s-z6.s},{z4.s-z7.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:99: Error: start register out of range at operand 3 -- `fscale {z0.s-z3.s},{z0.s-z3.s},{z5.s-z8.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:100: Error: start register out of range at operand 3 -- `fscale {z0.s-z3.s},{z0.s-z3.s},{z6.s-z9.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:101: Error: start register out of range at operand 3 -- `fscale {z0.s-z3.s},{z0.s-z3.s},{z7.s-z10.s}'
+[^:]+:105: Info: macro invoked from here
+[^:]+:88: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.d-z1.d},{z1.d-z2.d},{z2.d-z3.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:90: Error: start register out of range at operand 1 -- `fscale {z1.d-z2.d},{z1.d-z2.d},{z2.d-z3.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:91: Error: start register out of range at operand 1 -- `fscale {z1.d-z2.d},{z1.d-z2.d},{z3.d-z4.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:94: Error: operand 2 must be the same register as operand 1 -- `fscale {z0.d-z3.d},{z1.d-z4.d},{z4.d-z7.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:96: Error: start register out of range at operand 1 -- `fscale {z1.d-z4.d},{z1.d-z4.d},{z4.d-z7.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:97: Error: start register out of range at operand 1 -- `fscale {z2.d-z5.d},{z2.d-z5.d},{z4.d-z7.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:98: Error: start register out of range at operand 1 -- `fscale {z3.d-z6.d},{z3.d-z6.d},{z4.d-z7.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:99: Error: start register out of range at operand 3 -- `fscale {z0.d-z3.d},{z0.d-z3.d},{z5.d-z8.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:100: Error: start register out of range at operand 3 -- `fscale {z0.d-z3.d},{z0.d-z3.d},{z6.d-z9.d}'
+[^:]+:106: Info: macro invoked from here
+[^:]+:101: Error: start register out of range at operand 3 -- `fscale {z0.d-z3.d},{z0.d-z3.d},{z7.d-z10.d}'
+[^:]+:106: Info: macro invoked from here
diff --git a/gas/testsuite/gas/aarch64/sme2-fp8-fail.s b/gas/testsuite/gas/aarch64/sme2-fp8-fail.s
new file mode 100644
index 00000000000..612710fdda8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8-fail.s
@@ -0,0 +1,106 @@
+ /* sme-fp8-fail.s Test file for error-checking AArch64 SME 8-bit
+ floating-point vector instructions. */
+
+ .macro cvt_pat1, op
+ /* Check element width qualifier for source register. */
+ \op {z0.h-z1.h}, z2.b /* Valid. */
+ \op {z0.h-z1.h}, z2.h
+ \op {z0.h-z1.h}, z2.s
+ \op {z0.h-z1.h}, z2.d
+ /* Check element width qualifier for destination register pair. */
+ \op {z0.b-z1.b}, z2.b
+ \op {z0.h-z1.h}, z2.b /* Valid. */
+ \op {z0.s-z1.s}, z2.b
+ \op {z0.d-z1.d}, z2.b
+ /* Check whether destination register range starts at even register. */
+ \op {z1.h-z2.h}, z2.b
+ .endm
+
+ cvt_pat1 bf1cvt
+ cvt_pat1 bf2cvt
+ cvt_pat1 bf1cvtl
+ cvt_pat1 bf2cvtl
+ cvt_pat1 f1cvt
+ cvt_pat1 f2cvt
+ cvt_pat1 f1cvtl
+ cvt_pat1 f2cvtl
+
+ .macro cvt_pat2, op
+ /* Check element width qualifier for destination register. */
+ \op z2.b, {z0.h-z1.h} /* Valid. */
+ \op z2.h, {z0.h-z1.h}
+ \op z2.s, {z0.h-z1.h}
+ \op z2.d, {z0.h-z1.h}
+ /* Check element width qualifier for source register pair. */
+ \op z2.b, {z0.b-z1.b}
+ \op z2.b, {z0.h-z1.h} /* Valid. */
+ \op z2.b, {z0.s-z1.s}
+ \op z2.b, {z0.d-z1.d}
+ /* Check whether source register range starts at even register. */
+ \op z2.b, {z1.h-z2.h}
+ .endm
+
+ cvt_pat2 bfcvt
+ cvt_pat2 fcvt
+
+ .macro cvt_pat3, op
+ /* Check element width qualifier for destination register. */
+ \op z4.b, {z0.s-z3.s} /* Valid. */
+ \op z4.h, {z0.s-z3.s}
+ \op z4.s, {z0.s-z3.s}
+ \op z4.d, {z0.s-z3.s}
+ /* Check element width qualifier for source register pair. */
+ \op z4.b, {z0.b-z3.b}
+ \op z4.b, {z0.h-z3.h}
+ \op z4.b, {z0.s-z3.s} /* Valid. */
+ \op z4.b, {z0.d-z3.d}
+ /* Check whether start of source register range is multiple of 4. */
+ \op z4.b, {z1.s-z4.s}
+ \op z4.b, {z2.s-z5.s}
+ \op z4.b, {z3.s-z6.s}
+ .endm
+
+ cvt_pat3 fcvtn
+ cvt_pat3 fcvt
+
+ .macro fscale_single, w
+ /* pair. */
+ /* Ensure the two multi-vector groups are tied. */
+ fscale { z0.\w - z1.\w }, { z2.\w - z3.\w }, z2.\w
+ /* Check first source multi-vector group starts at even register. */
+ fscale { z1.\w - z2.\w }, { z1.\w - z2.\w }, z3.\w
+ /* quad. */
+ /* Ensure the two multi-vector groups are tied. */
+ fscale { z0.\w-z3.\w }, { z1.\w-z4.\w }, z4.\w
+ /* Check start of first source multi-vector group is multiple of 4. */
+ fscale { z1.\w-z4.\w }, { z1.\w-z4.\w }, z4.\w
+ fscale { z2.\w-z5.\w }, { z2.\w-z5.\w }, z4.\w
+ fscale { z3.\w-z6.\w }, { z3.\w-z6.\w }, z4.\w
+ .endm
+
+ fscale_single h
+ fscale_single s
+ fscale_single d
+
+ .macro fscale_multi, w
+ /* pair. */
+ /* Ensure the two multi-vector groups are tied. */
+ fscale { z0.\w - z1.\w }, { z1.\w - z2.\w }, { z2.\w-z3.\w }
+ /* Check multi-vector groups start at even register. */
+ fscale { z1.\w - z2.\w }, { z1.\w - z2.\w }, { z2.\w-z3.\w }
+ fscale { z1.\w - z2.\w }, { z1.\w - z2.\w }, { z3.\w-z4.\w }
+ /* quad. */
+ /* Ensure the two multi-vector groups are tied. */
+ fscale { z0.\w-z3.\w }, { z1.\w-z4.\w }, { z4.\w-z7.\w }
+ /* Check the start of multi-vector group ranges is multiple of 4. */
+ fscale { z1.\w-z4.\w }, { z1.\w-z4.\w }, { z4.\w-z7.\w }
+ fscale { z2.\w-z5.\w }, { z2.\w-z5.\w }, { z4.\w-z7.\w }
+ fscale { z3.\w-z6.\w }, { z3.\w-z6.\w }, { z4.\w-z7.\w }
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, { z5.\w-z8.\w }
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, { z6.\w-z9.\w }
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, { z7.\w-z10.\w }
+ .endm
+
+ fscale_multi h
+ fscale_multi s
+ fscale_multi d
diff --git a/gas/testsuite/gas/aarch64/sme2-fp8.d b/gas/testsuite/gas/aarch64/sme2-fp8.d
new file mode 100644
index 00000000000..8d952d4b8ad
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8.d
@@ -0,0 +1,128 @@
+#as: -march=armv8.5-a+fp8+sme2
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[ ]*[0-9a-f]+: c166e040 bf1cvt {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c166e080 bf1cvt {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c166e042 bf1cvt {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c166e082 bf1cvt {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c166e3dc bf1cvt {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c1e6e040 bf2cvt {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c1e6e080 bf2cvt {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c1e6e042 bf2cvt {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c1e6e082 bf2cvt {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c1e6e3dc bf2cvt {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c166e041 bf1cvtl {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c166e081 bf1cvtl {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c166e043 bf1cvtl {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c166e083 bf1cvtl {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c166e3dd bf1cvtl {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c1e6e041 bf2cvtl {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c1e6e081 bf2cvtl {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c1e6e043 bf2cvtl {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c1e6e083 bf2cvtl {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c1e6e3dd bf2cvtl {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c126e040 f1cvt {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c126e080 f1cvt {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c126e042 f1cvt {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c126e082 f1cvt {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c126e3dc f1cvt {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c1a6e040 f2cvt {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c1a6e080 f2cvt {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c1a6e042 f2cvt {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c1a6e082 f2cvt {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c1a6e3dc f2cvt {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c126e041 f1cvtl {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c126e081 f1cvtl {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c126e043 f1cvtl {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c126e083 f1cvtl {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c126e3dd f1cvtl {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c1a6e041 f2cvtl {z0.h-z1.h}, z2.b
+[ ]*[0-9a-f]+: c1a6e081 f2cvtl {z0.h-z1.h}, z4.b
+[ ]*[0-9a-f]+: c1a6e043 f2cvtl {z2.h-z3.h}, z2.b
+[ ]*[0-9a-f]+: c1a6e083 f2cvtl {z2.h-z3.h}, z4.b
+[ ]*[0-9a-f]+: c1a6e3dd f2cvtl {z28.h-z29.h}, z30.b
+[ ]*[0-9a-f]+: c164e002 bfcvt z2.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: c164e004 bfcvt z4.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: c164e042 bfcvt z2.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c164e044 bfcvt z4.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c164e39e bfcvt z30.b, {z28.h-z29.h}
+[ ]*[0-9a-f]+: c124e002 fcvt z2.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: c124e004 fcvt z4.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+: c124e042 fcvt z2.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c124e044 fcvt z4.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c124e39e fcvt z30.b, {z28.h-z29.h}
+[ ]*[0-9a-f]+: c134e024 fcvtn z4.b, {z0.s-z3.s}
+[ ]*[0-9a-f]+: c134e028 fcvtn z8.b, {z0.s-z3.s}
+[ ]*[0-9a-f]+: c134e0a4 fcvtn z4.b, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c134e0a8 fcvtn z8.b, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c134e33c fcvtn z28.b, {z24.s-z27.s}
+[ ]*[0-9a-f]+: c134e004 fcvt z4.b, {z0.s-z3.s}
+[ ]*[0-9a-f]+: c134e008 fcvt z8.b, {z0.s-z3.s}
+[ ]*[0-9a-f]+: c134e084 fcvt z4.b, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c134e088 fcvt z8.b, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c134e31c fcvt z28.b, {z24.s-z27.s}
+[ ]*[0-9a-f]+: c162a180 fscale {z0.h-z1.h}, {z0.h-z1.h}, z2.h
+[ ]*[0-9a-f]+: c162a182 fscale {z2.h-z3.h}, {z2.h-z3.h}, z2.h
+[ ]*[0-9a-f]+: c164a180 fscale {z0.h-z1.h}, {z0.h-z1.h}, z4.h
+[ ]*[0-9a-f]+: c164a182 fscale {z2.h-z3.h}, {z2.h-z3.h}, z4.h
+[ ]*[0-9a-f]+: c16fa198 fscale {z24.h-z25.h}, {z24.h-z25.h}, z15.h
+[ ]*[0-9a-f]+: c164a980 fscale {z0.h-z3.h}, {z0.h-z3.h}, z4.h
+[ ]*[0-9a-f]+: c164a984 fscale {z4.h-z7.h}, {z4.h-z7.h}, z4.h
+[ ]*[0-9a-f]+: c168a980 fscale {z0.h-z3.h}, {z0.h-z3.h}, z8.h
+[ ]*[0-9a-f]+: c168a984 fscale {z4.h-z7.h}, {z4.h-z7.h}, z8.h
+[ ]*[0-9a-f]+: c16fa998 fscale {z24.h-z27.h}, {z24.h-z27.h}, z15.h
+[ ]*[0-9a-f]+: c1a2a180 fscale {z0.s-z1.s}, {z0.s-z1.s}, z2.s
+[ ]*[0-9a-f]+: c1a2a182 fscale {z2.s-z3.s}, {z2.s-z3.s}, z2.s
+[ ]*[0-9a-f]+: c1a4a180 fscale {z0.s-z1.s}, {z0.s-z1.s}, z4.s
+[ ]*[0-9a-f]+: c1a4a182 fscale {z2.s-z3.s}, {z2.s-z3.s}, z4.s
+[ ]*[0-9a-f]+: c1afa198 fscale {z24.s-z25.s}, {z24.s-z25.s}, z15.s
+[ ]*[0-9a-f]+: c1a4a980 fscale {z0.s-z3.s}, {z0.s-z3.s}, z4.s
+[ ]*[0-9a-f]+: c1a4a984 fscale {z4.s-z7.s}, {z4.s-z7.s}, z4.s
+[ ]*[0-9a-f]+: c1a8a980 fscale {z0.s-z3.s}, {z0.s-z3.s}, z8.s
+[ ]*[0-9a-f]+: c1a8a984 fscale {z4.s-z7.s}, {z4.s-z7.s}, z8.s
+[ ]*[0-9a-f]+: c1afa998 fscale {z24.s-z27.s}, {z24.s-z27.s}, z15.s
+[ ]*[0-9a-f]+: c1e2a180 fscale {z0.d-z1.d}, {z0.d-z1.d}, z2.d
+[ ]*[0-9a-f]+: c1e2a182 fscale {z2.d-z3.d}, {z2.d-z3.d}, z2.d
+[ ]*[0-9a-f]+: c1e4a180 fscale {z0.d-z1.d}, {z0.d-z1.d}, z4.d
+[ ]*[0-9a-f]+: c1e4a182 fscale {z2.d-z3.d}, {z2.d-z3.d}, z4.d
+[ ]*[0-9a-f]+: c1efa198 fscale {z24.d-z25.d}, {z24.d-z25.d}, z15.d
+[ ]*[0-9a-f]+: c1e4a980 fscale {z0.d-z3.d}, {z0.d-z3.d}, z4.d
+[ ]*[0-9a-f]+: c1e4a984 fscale {z4.d-z7.d}, {z4.d-z7.d}, z4.d
+[ ]*[0-9a-f]+: c1e8a980 fscale {z0.d-z3.d}, {z0.d-z3.d}, z8.d
+[ ]*[0-9a-f]+: c1e8a984 fscale {z4.d-z7.d}, {z4.d-z7.d}, z8.d
+[ ]*[0-9a-f]+: c1efa998 fscale {z24.d-z27.d}, {z24.d-z27.d}, z15.d
+[ ]*[0-9a-f]+: c162b180 fscale {z0.h-z1.h}, {z0.h-z1.h}, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c162b182 fscale {z2.h-z3.h}, {z2.h-z3.h}, {z2.h-z3.h}
+[ ]*[0-9a-f]+: c164b180 fscale {z0.h-z1.h}, {z0.h-z1.h}, {z4.h-z5.h}
+[ ]*[0-9a-f]+: c164b182 fscale {z2.h-z3.h}, {z2.h-z3.h}, {z4.h-z5.h}
+[ ]*[0-9a-f]+: c176b194 fscale {z20.h-z21.h}, {z20.h-z21.h}, {z22.h-z23.h}
+[ ]*[0-9a-f]+: c164b980 fscale {z0.h-z3.h}, {z0.h-z3.h}, {z4.h-z7.h}
+[ ]*[0-9a-f]+: c164b984 fscale {z4.h-z7.h}, {z4.h-z7.h}, {z4.h-z7.h}
+[ ]*[0-9a-f]+: c168b980 fscale {z0.h-z3.h}, {z0.h-z3.h}, {z8.h-z11.h}
+[ ]*[0-9a-f]+: c168b984 fscale {z4.h-z7.h}, {z4.h-z7.h}, {z8.h-z11.h}
+[ ]*[0-9a-f]+: c178b994 fscale {z20.h-z23.h}, {z20.h-z23.h}, {z24.h-z27.h}
+[ ]*[0-9a-f]+: c1a2b180 fscale {z0.s-z1.s}, {z0.s-z1.s}, {z2.s-z3.s}
+[ ]*[0-9a-f]+: c1a2b182 fscale {z2.s-z3.s}, {z2.s-z3.s}, {z2.s-z3.s}
+[ ]*[0-9a-f]+: c1a4b180 fscale {z0.s-z1.s}, {z0.s-z1.s}, {z4.s-z5.s}
+[ ]*[0-9a-f]+: c1a4b182 fscale {z2.s-z3.s}, {z2.s-z3.s}, {z4.s-z5.s}
+[ ]*[0-9a-f]+: c1b6b194 fscale {z20.s-z21.s}, {z20.s-z21.s}, {z22.s-z23.s}
+[ ]*[0-9a-f]+: c1a4b980 fscale {z0.s-z3.s}, {z0.s-z3.s}, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c1a4b984 fscale {z4.s-z7.s}, {z4.s-z7.s}, {z4.s-z7.s}
+[ ]*[0-9a-f]+: c1a8b980 fscale {z0.s-z3.s}, {z0.s-z3.s}, {z8.s-z11.s}
+[ ]*[0-9a-f]+: c1a8b984 fscale {z4.s-z7.s}, {z4.s-z7.s}, {z8.s-z11.s}
+[ ]*[0-9a-f]+: c1b8b994 fscale {z20.s-z23.s}, {z20.s-z23.s}, {z24.s-z27.s}
+[ ]*[0-9a-f]+: c1e2b180 fscale {z0.d-z1.d}, {z0.d-z1.d}, {z2.d-z3.d}
+[ ]*[0-9a-f]+: c1e2b182 fscale {z2.d-z3.d}, {z2.d-z3.d}, {z2.d-z3.d}
+[ ]*[0-9a-f]+: c1e4b180 fscale {z0.d-z1.d}, {z0.d-z1.d}, {z4.d-z5.d}
+[ ]*[0-9a-f]+: c1e4b182 fscale {z2.d-z3.d}, {z2.d-z3.d}, {z4.d-z5.d}
+[ ]*[0-9a-f]+: c1f6b194 fscale {z20.d-z21.d}, {z20.d-z21.d}, {z22.d-z23.d}
+[ ]*[0-9a-f]+: c1e4b980 fscale {z0.d-z3.d}, {z0.d-z3.d}, {z4.d-z7.d}
+[ ]*[0-9a-f]+: c1e4b984 fscale {z4.d-z7.d}, {z4.d-z7.d}, {z4.d-z7.d}
+[ ]*[0-9a-f]+: c1e8b980 fscale {z0.d-z3.d}, {z0.d-z3.d}, {z8.d-z11.d}
+[ ]*[0-9a-f]+: c1e8b984 fscale {z4.d-z7.d}, {z4.d-z7.d}, {z8.d-z11.d}
+[ ]*[0-9a-f]+: c1f8b994 fscale {z20.d-z23.d}, {z20.d-z23.d}, {z24.d-z27.d}
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sme2-fp8.s b/gas/testsuite/gas/aarch64/sme2-fp8.s
new file mode 100644
index 00000000000..ca2a4b4d20a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8.s
@@ -0,0 +1,112 @@
+ /* sme-fp8.s Test file for AArch64 SME 8-bit floating-point
+ vector instructions. */
+
+ .macro cvt_pat1, op
+ \op {z0.h-z1.h}, z2.b
+ \op {z0.h-z1.h}, z4.b
+ \op {z2.h-z3.h}, z2.b
+ \op {z2.h-z3.h}, z4.b
+ \op {z28.h-z29.h}, z30.b
+ .endm
+
+ /* Multi-vector floating-point convert from 8-bit floating-point. */
+
+ /* To BFloat16 (in-order) 2^-UInt(FPMR.LSCALE{2}[5:0]). */
+ cvt_pat1 bf1cvt
+ cvt_pat1 bf2cvt
+
+ /* To deinterleaved BFloat16 (in-order) 2^-UInt(FPMR.LSCALE{2}[5:0]). */
+ cvt_pat1 bf1cvtl
+ cvt_pat1 bf2cvtl
+
+ /* To half-precision (in-order) 2^-UInt(FPMR.LSCALE{2}[3:0]). */
+ cvt_pat1 f1cvt
+ cvt_pat1 f2cvt
+
+ /* To deinterleaved half-precision 2^-UInt(FPMR.LSCALE{2}[3:0]). */
+ cvt_pat1 f1cvtl
+ cvt_pat1 f2cvtl
+
+ .macro cvt_pat2, op
+ \op z2.b, {z0.h-z1.h}
+ \op z4.b, {z0.h-z1.h}
+ \op z2.b, {z2.h-z3.h}
+ \op z4.b, {z2.h-z3.h}
+ \op z30.b, {z28.h-z29.h}
+ .endm
+
+ /* Multi-vector floating-point convert to packed 8-bit floating-point
+ format. */
+
+ /* From BFloat16 with 2^SInt(FPMR.NSCALE) scaling. */
+ cvt_pat2 bfcvt
+
+ /* From half-precision with 2^SInt(FPMR.NSCALE[4:0]) scaling. */
+ cvt_pat2 fcvt
+
+ .macro cvt_pat3, op
+ \op z4.b, {z0.s-z3.s}
+ \op z8.b, {z0.s-z3.s}
+ \op z4.b, {z4.s-z7.s}
+ \op z8.b, {z4.s-z7.s}
+ \op z28.b, {z24.s-z27.s}
+ .endm
+
+ /* Multi-vector floating-point convert from single-precision to
+ {interleaved|packed} 8-bit floating-point format with
+ 2^SInt(FPMR.NSCALE) scaling. */
+
+ cvt_pat3 fcvtn /* interleaved. */
+ cvt_pat3 fcvt /* packed. */
+
+ .macro fscale_single, w
+ /* pair. */
+ fscale { z0.\w - z1.\w }, { z0.\w - z1.\w }, z2.\w
+ fscale { z2.\w - z3.\w }, { z2.\w - z3.\w }, z2.\w
+ fscale { z0.\w - z1.\w }, { z0.\w - z1.\w }, z4.\w
+ fscale { z2.\w - z3.\w }, { z2.\w - z3.\w }, z4.\w
+ fscale { z24.\w-z25.\w }, { z24.\w-z25.\w }, z15.\w
+ /* quad. */
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, z4.\w
+ fscale { z4.\w-z7.\w }, { z4.\w-z7.\w }, z4.\w
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, z8.\w
+ fscale { z4.\w-z7.\w }, { z4.\w-z7.\w }, z8.\w
+ fscale { z24.\w-z27.\w }, { z24.\w-z27.\w }, z15.\w
+ .endm
+
+ /* Multi-vector floating-point adjust exponent by vector.
+
+ Multiply floating-point elements of the 2 or 4 first source vecs by
+ 2.0^SInt(vals in the corresponding elements of 2nd source vector)
+ and destructively place results in corresponding elements of 2 or 4
+ first source vectors. */
+
+ fscale_single h
+ fscale_single s
+ fscale_single d
+
+ .macro fscale_multi, w
+ /* pair. */
+ fscale { z0.\w - z1.\w }, { z0.\w - z1.\w }, { z2.\w-z3.\w }
+ fscale { z2.\w - z3.\w }, { z2.\w - z3.\w }, { z2.\w-z3.\w }
+ fscale { z0.\w - z1.\w }, { z0.\w - z1.\w }, { z4.\w-z5.\w }
+ fscale { z2.\w - z3.\w }, { z2.\w - z3.\w }, { z4.\w-z5.\w }
+ fscale { z20.\w-z21.\w }, { z20.\w-z21.\w }, { z22.\w-z23.\w }
+ /* quad. */
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, { z4.\w-z7.\w }
+ fscale { z4.\w-z7.\w }, { z4.\w-z7.\w }, { z4.\w-z7.\w }
+ fscale { z0.\w-z3.\w }, { z0.\w-z3.\w }, { z8.\w-z11.\w }
+ fscale { z4.\w-z7.\w }, { z4.\w-z7.\w }, { z8.\w-z11.\w }
+ fscale { z20.\w-z23.\w }, { z20.\w-z23.\w }, { z24.\w-z27.\w }
+ .endm
+
+ /* Multi-vector floating-point adjust exponent.
+
+ Multiply floating-point elements of the 2 or 4 first source vecs by
+ 2.0^SInt(vals in the corresponding elements of the 2 or 4 2nd source
+ vectors) and destructively place results in corresponding elements
+ of 2 or 4 first source vectors. */
+
+ fscale_multi h
+ fscale_multi s
+ fscale_multi d
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 36d474403e2..46f4e2ff1fa 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -4465,33 +4465,44 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 5) & 0x1) == 0)
{
- if (((word >> 8) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx101000x0xx0xxxx0
- smax. */
- return 2710;
- }
- else
+ if (((word >> 7) & 0x1) == 0)
{
- if (((word >> 9) & 0x1) == 0)
+ if (((word >> 8) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxxx10100001xx0xxxx0
- fmax. */
- return 2545;
+ x1000001xx1xxxxx101000x00x0xxxx0
+ smax. */
+ return 2710;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx10100011xx0xxxx0
- add. */
- return 2499;
+ if (((word >> 9) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx101000010x0xxxx0
+ fmax. */
+ return 2545;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx101000110x0xxxx0
+ add. */
+ return 2499;
+ }
}
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx101000xx1x0xxxx0
+ fscale. */
+ return 3370;
+ }
}
else
{
@@ -4581,9 +4592,9 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 16) & 0x1) == 0)
{
- if (((word >> 5) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 5) & 0x1) == 0)
{
if (((word >> 18) & 0x1) == 0)
{
@@ -4627,46 +4638,35 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
}
else
- {
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx10x100111000xxxx0xxxxx
- frinta. */
- return 2589;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11x100111000xxxx0xxxxx
- frinta. */
- return 2590;
- }
- }
- }
- else
- {
- if (((word >> 18) & 0x1) == 0)
{
if (((word >> 19) & 0x1) == 0)
{
if (((word >> 20) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx100010111000xxxx0xxxxx
- scvtf. */
- return 2694;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001x0100100111000xxxx0xxxxx
+ fcvt. */
+ return 3367;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001x1100100111000xxxx0xxxxx
+ bfcvt. */
+ return 3362;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx110010111000xxxx0xxxxx
- scvtf. */
- return 2695;
+ x1000001xx110100111000xxxx0xxxxx
+ fcvt. */
+ return 3368;
}
}
else
@@ -4675,79 +4675,222 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx101010111000xxxx0xxxxx
- frintm. */
- return 2591;
+ x1000001xx101100111000xxxx0xxxxx
+ frinta. */
+ return 2589;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx111010111000xxxx0xxxxx
- frintm. */
- return 2592;
+ x1000001xx111100111000xxxx0xxxxx
+ frinta. */
+ return 2590;
}
}
}
- else
+ }
+ else
+ {
+ if (((word >> 18) & 0x1) == 0)
{
- if (((word >> 1) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xx110111000xxxx0xxx0x
- zip. */
- return 2959;
+ x1000001x01xx000111000xxxx1xxxxx
+ fcvtn. */
+ return 2534;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xx110111000xxxx0xxx1x
- uzp. */
- return 2946;
+ x1000001x11xx000111000xxxx1xxxxx
+ bfcvtn. */
+ return 2502;
}
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xx100111000xxxx1xxxxx
+ fcvtn. */
+ return 3369;
+ }
}
}
else
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 0) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 18) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001x01xxx00111000xxxx1xxxxx
- fcvtn. */
- return 2534;
+ if (((word >> 5) & 0x1) == 0)
+ {
+ if (((word >> 19) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx100010111000xxxx0xxxx0
+ scvtf. */
+ return 2694;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx110010111000xxxx0xxxx0
+ scvtf. */
+ return 2695;
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx101010111000xxxx0xxxx0
+ frintm. */
+ return 2591;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx111010111000xxxx0xxxx0
+ frintm. */
+ return 2592;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx10x010111000xxxx1xxxx0
+ ucvtf. */
+ return 2859;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11x010111000xxxx1xxxx0
+ ucvtf. */
+ return 2860;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001x11xxx00111000xxxx1xxxxx
- bfcvtn. */
- return 2502;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010010x110111000xxxxxxxxx0
+ f1cvt. */
+ return 3363;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011010x110111000xxxxxxxxx0
+ f2cvt. */
+ return 3364;
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010110x110111000xxxxxxxxx0
+ bf1cvt. */
+ return 3358;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011110x110111000xxxxxxxxx0
+ bf2cvt. */
+ return 3359;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 1) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11x110111000xxxxxxxx00
+ zip. */
+ return 2959;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11x110111000xxxxxxxx10
+ uzp. */
+ return 2946;
+ }
+ }
}
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx10xx10111000xxxx1xxxxx
- ucvtf. */
- return 2859;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001001xxx10111000xxxxxxxxx1
+ f1cvtl. */
+ return 3365;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxx10111000xxxxxxxxx1
+ f2cvtl. */
+ return 3366;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xx10111000xxxx1xxxxx
- ucvtf. */
- return 2860;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001011xxx10111000xxxxxxxxx1
+ bf1cvtl. */
+ return 3360;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001111xxx10111000xxxxxxxxx1
+ bf2cvtl. */
+ return 3361;
+ }
}
}
}
@@ -4990,21 +5133,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 6) & 0x1) == 0)
{
- if (((word >> 8) & 0x1) == 0)
+ if (((word >> 7) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1100x0x00xxxx0
- smax. */
- return 2712;
+ if (((word >> 8) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1100x0000xxxx0
+ smax. */
+ return 2712;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1100x1000xxxx0
+ fmax. */
+ return 2547;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxxx1x1100x1x00xxxx0
- fmax. */
- return 2547;
+ x1000001xx1xxxxx1x1100xx100xxxx0
+ fscale. */
+ return 3372;
}
}
else
@@ -5120,53 +5274,75 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 6) & 0x1) == 0)
{
- if (((word >> 8) & 0x1) == 0)
+ if (((word >> 7) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1010x0x00xxxx0
- smax. */
- return 2711;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1110x0x00xxxx0
- smax. */
- return 2713;
- }
- }
- else
- {
- if (((word >> 9) & 0x1) == 0)
+ if (((word >> 8) & 0x1) == 0)
{
if (((word >> 12) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxxx1x101001x00xxxx0
- fmax. */
- return 2546;
+ x1000001xx1xxxxx1x1010x0000xxxx0
+ smax. */
+ return 2711;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxxx1x111001x00xxxx0
- fmax. */
- return 2548;
+ x1000001xx1xxxxx1x1110x0000xxxx0
+ smax. */
+ return 2713;
+ }
+ }
+ else
+ {
+ if (((word >> 9) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x101001000xxxx0
+ fmax. */
+ return 2546;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x111001000xxxx0
+ fmax. */
+ return 2548;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1x1011000xxxx0
+ add. */
+ return 2500;
}
}
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1010xx100xxxx0
+ fscale. */
+ return 3371;
+ }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xxxxx1x1x1011x00xxxx0
- add. */
- return 2500;
+ x1000001xx1xxxxx1x1110xx100xxxx0
+ fscale. */
+ return 3373;
}
}
}
@@ -10334,7 +10510,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3358;
+ return 3374;
}
else
{
@@ -10342,7 +10518,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3359;
+ return 3375;
}
}
}
@@ -11260,7 +11436,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3360;
+ return 3376;
}
else
{
@@ -11268,7 +11444,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3361;
+ return 3377;
}
}
}
@@ -11353,7 +11529,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3362;
+ return 3378;
}
else
{
@@ -11460,7 +11636,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3364;
+ return 3380;
}
else
{
@@ -11665,7 +11841,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3363;
+ return 3379;
}
else
{
@@ -11706,7 +11882,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3365;
+ return 3381;
}
else
{
@@ -13364,7 +13540,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3367;
+ return 3383;
}
}
else
@@ -13394,7 +13570,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3366;
+ return 3382;
}
}
}
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 464d9313a37..43153f41d6b 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6520,6 +6520,22 @@ const struct aarch64_opcode aarch64_opcode_table[] =
FP8_SVE2_INSN ("fcvtn", 0x650a3000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BH, 0, 0),
FP8_SVE2_INSN ("fcvtnb", 0x650a3400, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BS, 0, 0),
FP8_SVE2_INSN ("fcvtnt", 0x650a3c00, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BS, 0, 0),
+ FP8_SME2_INSN ("bf1cvt", 0xc166e000, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("bf2cvt", 0xc1e6e000, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("bf1cvtl", 0xc166e001, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("bf2cvtl", 0xc1e6e001, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("bfcvt", 0xc164e000, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BH, 0, 0),
+ FP8_SME2_INSN ("f1cvt", 0xc126e000, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("f2cvt", 0xc1a6e000, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("f1cvtl", 0xc126e001, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("f2cvtl", 0xc1a6e001, 0xfffffc01, sme_misc, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_HB, 0, 0),
+ FP8_SME2_INSN ("fcvt", 0xc124e000, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_BH, 0, 0),
+ FP8_SME2_INSN ("fcvt", 0xc134e000, 0xfffffc60, sme_misc, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_BS, 0, 0),
+ FP8_SME2_INSN ("fcvtn", 0xc134e020, 0xfffffc60, sme_misc, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_BS, 0, 0),
+ FP8_SME2_INSN ("fscale", 0xc120a180, 0xff30ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_HSD, 0, 1),
+ FP8_SME2_INSN ("fscale", 0xc120a980, 0xff30ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_HSD, 0, 1),
+ FP8_SME2_INSN ("fscale", 0xc120b180, 0xff21ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 1),
+ FP8_SME2_INSN ("fscale", 0xc120b980, 0xff23ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 1),
/* Checked Pointer Arithmetic Instructions. */
CPA_INSN ("addpt", 0x9a002000, 0xffe0e000, aarch64_misc, OP3 (Rd_SP, Rn_SP, Rm_LSL), QL_I3SAMEX),
--
2.34.1
next prev parent reply other threads:[~2024-04-10 15:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-10 15:29 [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 1/4] aarch64: fp8 convert and scale - add feature flags and related structures Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 2/4] aarch64: fp8 convert and scale - Add advsimd insn variants Victor Do Nascimento
2024-05-17 15:43 ` Richard Earnshaw (lists)
2024-05-20 15:36 ` Andrew Carlotti
2024-04-10 15:29 ` [PATCH 3/4] aarch64: fp8 convert and scale - add sve2 " Victor Do Nascimento
2024-04-10 15:29 ` Victor Do Nascimento [this message]
2024-04-17 9:50 ` [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Nick Clifton
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