From: "Richard Earnshaw (lists)" <Richard.Earnshaw@arm.com>
To: Victor Do Nascimento <victor.donascimento@arm.com>,
binutils@sourceware.org
Cc: nickc@redhat.com
Subject: Re: [PATCH 2/4] aarch64: fp8 convert and scale - Add advsimd insn variants
Date: Fri, 17 May 2024 16:43:05 +0100 [thread overview]
Message-ID: <96b1b357-94c8-4cd9-aaa6-b149cd041250@arm.com> (raw)
In-Reply-To: <20240410152950.1134020-3-victor.donascimento@arm.com>
On 10/04/2024 16:29, Victor Do Nascimento wrote:
> @@ -6459,6 +6487,19 @@ const struct aarch64_opcode
> aarch64_opcode_table[] =
> SVE2p1_INSNC("st2q",0xe4600000, 0xffe0e000, sve_misc, 0, OP3
> (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
> SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3
> (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
> SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3
> (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
> + FP8_INSN("bf1cvtl", 0x2ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V2FP8B8H, 0),
> + FP8_INSN("bf1cvtl2", 0x6ea17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V28H16B, 0),
> + FP8_INSN("bf2cvtl", 0x2ee17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V2FP8B8H, 0),
> + FP8_INSN("bf2cvtl2", 0x6ee17800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V28H16B, 0),
> + FP8_INSN("f1cvtl", 0x2e217800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V2FP8B8H, 0),
> + FP8_INSN("f1cvtl2", 0x6e217800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V28H16B, 0),
> + FP8_INSN("f2cvtl", 0x2e617800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V2FP8B8H, 0),
> + FP8_INSN("f2cvtl2", 0x6e617800, 0xfffffc00, asimdmisc, OP2 (Vd, Vn),
> QL_V28H16B, 0),
> + FP8_INSN("fcvtn", 0xe00f400, 0xffe0fc00, asimdmisc, OP3 (Vd, Vn,
> Vm), QL_V3_BSS_LOWER, 0),
Nit: The opcode in this pattern is missing the leading zero, which makes it a bit harder to verify. Please can you add that before pushing.
> + FP8_INSN("fcvtn2", 0x4e00f400, 0xffe0fc00, asimdmisc, OP3 (Vd, Vn,
> Vm), QL_V3_BSS_FULL, 0),
> + FP8_INSN("fcvtn", 0xe40f400, 0xbfe0fc00, asimdmisc, OP3 (Vd, Vn,
> Vm), QL_V3_BHH, F_SIZEQ),
Same here.
> + FP8_INSN("fscale", 0x2ec03c00, 0xbfe0fc00, asimdmisc, OP3 (Vd, Vn,
> Vm), QL_VSHIFT_H, F_SIZEQ),
> + FP8_INSN("fscale", 0x2ea0fc00, 0xbfa0fc00, asimdmisc, OP3 (Vd, Vn,
> Vm), QL_V3SAMESD, F_SIZEQ),
R.
next prev parent reply other threads:[~2024-05-17 15:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-10 15:29 [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 1/4] aarch64: fp8 convert and scale - add feature flags and related structures Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 2/4] aarch64: fp8 convert and scale - Add advsimd insn variants Victor Do Nascimento
2024-05-17 15:43 ` Richard Earnshaw (lists) [this message]
2024-05-20 15:36 ` Andrew Carlotti
2024-04-10 15:29 ` [PATCH 3/4] aarch64: fp8 convert and scale - add sve2 " Victor Do Nascimento
2024-04-10 15:29 ` [PATCH 4/4] aarch64: fp8 convert and scale - add sme2 " Victor Do Nascimento
2024-04-17 9:50 ` [PATCH 0/4] aarch64: Add armv9.5-a FP8 datatype conversion Nick Clifton
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