From: Jan Beulich <jbeulich@suse.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: binutils@sourceware.org, gdb-patches@sourceware.org,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Burgess <aburgess@redhat.com>
Subject: Re: [PATCH 0/2] RISC-V: Fix buffer overflow after long instruction support
Date: Tue, 4 Oct 2022 11:07:39 +0200 [thread overview]
Message-ID: <227e9854-f0bf-566a-42ef-5f14a145c6dc@suse.com> (raw)
In-Reply-To: <cover.1664873933.git.research_trasio@irq.a4lg.com>
On 04.10.2022 10:59, Tsukasa OI wrote:
> After commit bb996692bd9 "RISC-V/gas: allow generating up to 176-bit
> instructions with .insn", I started to see some crashes while running
> "make check-gas".
Hmm, I'm puzzled why things worked correctly for me. The extra size needed
is quite significant, so chances should be rather slim for things to work
correctly.
> The cause was simple. Some functions depended on the fact that maximum
> length returned by riscv_insn_length is 8. But since the commit above
> increased that upper limit from 64-bits (8 bytes) to 176-bits (22 bytes),
> we need to increase two buffer sizes to avoid crashes.
>
> But note that this change doesn't really support over 64-bit instructions.
> It can be said on riscv_insn::fetch_instruction because it now may return
> only a part of instruction.
> Instead of merging this, reverting that commit (for now) might be an option.
Please let's try to avoid reverting - the ability to emit wide instructions
via .insn helps testsuites beyond binutils' / gas'es.
In any event - thanks for the quick fixing of the issue. I wonder though
whether a connection (at least by way of comments) should be established so
that the same oversight won't happen again (e.g. once the spec spells out
how even wider insns would be encoded).
Jan
next prev parent reply other threads:[~2022-10-04 9:07 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-04 8:59 Tsukasa OI
2022-10-04 8:59 ` [PATCH 1/2] RISC-V: Fix buffer overflow on print_insn_riscv Tsukasa OI
2022-10-04 8:59 ` [PATCH 2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction Tsukasa OI
2022-10-04 9:04 ` Andreas Schwab
2022-10-04 9:07 ` Jan Beulich [this message]
2022-10-04 9:26 ` [PATCH 0/2] RISC-V: Fix buffer overflow after long instruction support Tsukasa OI
2022-10-04 9:44 ` Jan Beulich
2022-10-04 9:47 ` Tsukasa OI
2022-10-04 9:45 ` [PATCH v2 0/2] RISC-V: Fix buffer overflow after 176-bit " Tsukasa OI
2022-10-04 9:45 ` [PATCH v2 1/2] RISC-V: Fix buffer overflow on print_insn_riscv Tsukasa OI
2022-10-04 9:58 ` Jan Beulich
2022-10-04 10:13 ` Tsukasa OI
2022-10-04 10:16 ` Jan Beulich
2022-10-04 10:18 ` Jan Beulich
2022-10-04 9:45 ` [PATCH v2 2/2] gdb/riscv: Partial support for instructions up to 176-bits Tsukasa OI
2022-10-04 11:25 ` [PATCH v3 0/2] RISC-V: Fix buffer overflow after 176-bit instruction support Tsukasa OI
2022-10-04 11:25 ` [PATCH v3 1/2] RISC-V: Fix buffer overflow on print_insn_riscv Tsukasa OI
2022-10-04 11:25 ` [PATCH v3 2/2] gdb/riscv: Partial support for instructions up to 176-bit Tsukasa OI
2022-10-04 12:23 ` [PATCH v3 0/2] RISC-V: Fix buffer overflow after 176-bit instruction support Jan Beulich
2022-10-04 13:20 ` Nelson Chu
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