Re: [PATCH 0/1] RISC-V: Add `OP_V' to .insn named opcodes

[Tsukasa OI <research_trasio@irq.a4lg.com>]

Ping.

I noticed that LLVM (14 or later) already implements this named opcode.

sample.s:
    .attribute arch, "rv64gcv"
    # Both vadd.vv v1,v2,v3
    .insn r 0x57, 0, 1, x1, x3, x2
    .insn r OP_V, 0, 1, x1, x3, x2

$ llvm-mc -filetype=obj -triple=riscv64 -o sample.o sample.s
$ riscv64-unknown-elf-objdump -d sample.o
(...)
0000000000000000 <.text>:
   0:   022180d7                vadd.vv v1,v2,v3
   4:   022180d7                vadd.vv v1,v2,v3

Even after this patch, following assembly file generates an error
(unlike LLVM).  I'm going to raise an issue later.

sample2.s:
    .attribute arch, "rv64gcv"
    # vadd.vv v1,v2,v3 (okay on LLVM but error on Binutils)
    .insn r OP_V, 0, 1, v1, v3, v2

Thanks,
Tsukasa


On 2022/07/09 12:51, Tsukasa OI wrote:
> Hello,
> 
> This small patch adds OP_V to named opcode list for .insn directive.
> 
> Tracker on GitHub:
> <https://github.com/a4lg/binutils-gdb/wiki/riscv_gas_insn_opv>
> 
>     Sidenote:
>     I started listing my Binutils submissions on my GitHub Wiki:
>     <https://github.com/a4lg/binutils-gdb/wiki/Patch-Queue>
>     hoping that current status and conflicting patches are clear.
> 
> 
> OP-V (0x57) is an opcode for vector instructions (defined on now
> ratified V extension).  It adds OP_V to named constants of .insn directive
> (note that replacing - with _ is standard on GNU Binutils' .insn).
> 
> Although vector instruction encoding is not implemented in .insn directive,
> it will help future implementation of custom vector .insn.
> 
> If Zp* extensions are ratified, we could add OP_P (0x77) likewise.
> 
> 
> Thanks,
> Tsukasa
> 
> 
> 
> 
> Tsukasa OI (1):
>   RISC-V: Add `OP_V' to .insn named opcodes
> 
>  gas/config/tc-riscv.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> 
> base-commit: d2acd4b0c5bab349aaa152d60268bc144634a844