From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org
Subject: [PATCH 1/1] RISC-V: Add `OP_V' to .insn named opcodes
Date: Sat, 9 Jul 2022 12:51:38 +0900 [thread overview]
Message-ID: <ea76f3fb533f2084b41c9f53ababe88c6785bc1a.1657338695.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1657338695.git.research_trasio@irq.a4lg.com>
This commit adds `OP_V' (OP-V: vector instruction opcode for now
ratified `V' extension) to .insn opcode name list. Although vector
instruction encoding is not implemented in `.insn' directive, it will
help future implementation of custom vector `.insn'.
gas/ChangeLog:
* config/tc-riscv.c (opcode_name_list): Add `OP_V'.
---
gas/config/tc-riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index a0e8456a0d1..1c53e66f9f5 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -749,7 +749,7 @@ static const struct opcode_name_t opcode_name_list[] =
{"NMADD", 0x4f},
{"NMSUB", 0x4b},
{"OP_FP", 0x53},
- /*reserved 0x57. */
+ {"OP_V", 0x57},
{"CUSTOM_2", 0x5b},
/* 48b 0x5f. */
--
2.34.1
next prev parent reply other threads:[~2022-07-09 3:51 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-09 3:51 [PATCH 0/1] " Tsukasa OI
2022-07-09 3:51 ` Tsukasa OI [this message]
2022-07-28 11:46 ` Tsukasa OI
2022-07-28 12:35 ` Kito Cheng
2022-07-28 13:02 ` [PATCH v2 " Tsukasa OI
2022-07-28 13:02 ` [PATCH v2 1/1] " Tsukasa OI
2022-07-28 13:29 ` Kito Cheng
2022-07-29 1:51 ` Nelson Chu
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