From: Kito Cheng <kito.cheng@gmail.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Nelson Chu <nelson.chu@sifive.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Binutils <binutils@sourceware.org>
Subject: Re: [PATCH v2 1/1] RISC-V: Add `OP_V' to .insn named opcodes
Date: Thu, 28 Jul 2022 21:29:44 +0800 [thread overview]
Message-ID: <CA+yXCZCqHKOx8oKq5iNKdeWC6Mg1vTcCN1g_kwqDubu5EhNAVw@mail.gmail.com> (raw)
In-Reply-To: <60b65d0e0a3cde2edb6c3276a5d31b29d628c60e.1659013304.git.research_trasio@irq.a4lg.com>
LGTM
On Thu, Jul 28, 2022 at 9:03 PM Tsukasa OI via Binutils
<binutils@sourceware.org> wrote:
>
> This commit adds `OP_V' (OP-V: vector instruction opcode for now
> ratified `V' extension) to .insn opcode name list. Although vector
> instruction encoding is not implemented in `.insn' directive, it will
> help future implementation of custom vector `.insn'.
>
> gas/ChangeLog:
>
> * config/tc-riscv.c (opcode_name_list): Add `OP_V'.
> * testsuite/gas/riscv/insn.s: Add testcase.
> * testsuite/gas/riscv/insn.d: Likewise.
> * testsuite/gas/riscv/insn-dwarf.d: Reflect insn.s update.
> ---
> gas/config/tc-riscv.c | 2 +-
> gas/testsuite/gas/riscv/insn-dwarf.d | 17 +++++++++--------
> gas/testsuite/gas/riscv/insn.d | 3 ++-
> gas/testsuite/gas/riscv/insn.s | 2 ++
> 4 files changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 291d07f6d8f..ecdffbef589 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -749,7 +749,7 @@ static const struct opcode_name_t opcode_name_list[] =
> {"NMADD", 0x4f},
> {"NMSUB", 0x4b},
> {"OP_FP", 0x53},
> - /*reserved 0x57. */
> + {"OP_V", 0x57},
> {"CUSTOM_2", 0x5b},
> /* 48b 0x5f. */
>
> diff --git a/gas/testsuite/gas/riscv/insn-dwarf.d b/gas/testsuite/gas/riscv/insn-dwarf.d
> index 72d54d47acf..a975b1464c0 100644
> --- a/gas/testsuite/gas/riscv/insn-dwarf.d
> +++ b/gas/testsuite/gas/riscv/insn-dwarf.d
> @@ -60,12 +60,13 @@ insn.s +53 +0x9a.*
> insn.s +54 +0x9e.*
> insn.s +55 +0xa2.*
> insn.s +57 +0xa6.*
> -insn.s +58 +0xa8.*
> -insn.s +59 +0xac.*
> -insn.s +60 +0xb2.*
> -insn.s +61 +0xba.*
> -insn.s +62 +0xbc.*
> -insn.s +63 +0xc0.*
> -insn.s +64 +0xc6.*
> -insn.s +- +0xce
> +insn.s +59 +0xaa.*
> +insn.s +60 +0xac.*
> +insn.s +61 +0xb0.*
> +insn.s +62 +0xb6.*
> +insn.s +63 +0xbe.*
> +insn.s +64 +0xc0.*
> +insn.s +65 +0xc4.*
> +insn.s +66 +0xca.*
> +insn.s +- +0xd2
> #pass
> diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
> index b5780f42861..d177f313d23 100644
> --- a/gas/testsuite/gas/riscv/insn.d
> +++ b/gas/testsuite/gas/riscv/insn.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv32ifc
> +#as: -march=rv32ifdcv
> #objdump: -dr
>
> .*:[ ]+file format .*
> @@ -69,6 +69,7 @@ Disassembly of section .text:
> [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
> [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
> [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2
> +[^:]+:[ ]+022180d7[ ]+vadd\.vv[ ]+v1,v2,v3
> [^:]+:[ ]+0001[ ]+nop
> [^:]+:[ ]+00000013[ ]+nop
> [^:]+:[ ]+001f 0000 0000[ ].*
> diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
> index ec41acb30bd..993615eb747 100644
> --- a/gas/testsuite/gas/riscv/insn.s
> +++ b/gas/testsuite/gas/riscv/insn.s
> @@ -54,6 +54,8 @@ target:
> .insn r 0x33, 0, 0, a0, fa1, fa2
> .insn r 0x33, 0, 0, fa0, fa1, fa2
>
> + .insn r OP_V, 0, 1, x1, x3, x2
> +
> .insn 0x0001
> .insn 0x00000013
> .insn 0x0000001f
> --
> 2.34.1
>
next prev parent reply other threads:[~2022-07-28 13:29 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-09 3:51 [PATCH 0/1] " Tsukasa OI
2022-07-09 3:51 ` [PATCH 1/1] " Tsukasa OI
2022-07-28 11:46 ` [PATCH 0/1] " Tsukasa OI
2022-07-28 12:35 ` Kito Cheng
2022-07-28 13:02 ` [PATCH v2 " Tsukasa OI
2022-07-28 13:02 ` [PATCH v2 1/1] " Tsukasa OI
2022-07-28 13:29 ` Kito Cheng [this message]
2022-07-29 1:51 ` Nelson Chu
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