Re: [PATCH] RISC-V: move various alias entries

[Jan Beulich <jbeulich@suse.com>]

On 05.08.2023 03:40, Tsukasa OI wrote:
> On 2023/08/04 21:00, Jan Beulich via Binutils wrote:
>> For disassembly to only use spec-mandated aliases, respective non-alias
>> entries need to come ahead of their alias ones. Since identical
>> mnemonics need to stay together, whole groups are moved up where
>> necessary.
>>
>> This partly reverts 839189bc932e ("RISC-V: re-arrange opcode table for
>> consistent alias handling"), but then also goes beyond a plain revert.
>> ---
>> I did not adjust JAL back, to continue to match JALR. The spec doesn't
>> spell out how operands are to be specified, and hence it also doesn't
>> mention how many explicit ones there are supposed to be.
>>
>> What about NEG, NEGW, and RET (and perhaps more)? The spec doesn't know
>> of those afaics.
> 
> I think JAL, NEG, NEGW and RET are okay as is.
> 
> For JAL, I support Jan's opinion.
> 
> For all instructions Jan pointed out (including JAL with one operand),
> they are listed in the RISC-V Assembly Programmer's Manual:
> <https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md>
> and should be considered safe
> (unlike "add rd, rs1, IMM" == "addi rd, rs1, IMM").
> 
> I support merging this patch without modification (or perhaps, with
> minor modification to the commit message?).
> 
> Reviewed-by: Tsukasa OI <research_trasio@irq.a4lg.com>

Arch maintainers - any view? I guess I'll wait another week or so and
commit if I don't hear anything to the contrary.

Jan