From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
"H . Peter Anvin" <hpa@zytor.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Nelson Chu <nelson@rivosinc.com>
Cc: binutils@sourceware.org
Subject: [PATCH v8 6/7] RISC-V: Clarify that `wide' is only used for ADDIW
Date: Sat, 27 Aug 2022 00:11:03 +0000 [thread overview]
Message-ID: <36c06f57eb5507dd19b63f8f3bd0163f69349fef.1661559056.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1661559056.git.research_trasio@irq.a4lg.com>
The `wide' parameter on the `maybe_print_address' function is only used
for the ADDIW/C.ADDIW instructions and there's no reasonable usecases except
those two.
This commit renames the parameter from `wide' to `is_addiw' to clarify that
this parameter is only used for ADDIW instructions.
opcodes/ChangeLog:
* riscv-dis.c (maybe_print_address): Clarify and rename the last
parameter so that this is only used for ADDIW instructions.
---
opcodes/riscv-dis.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 160cc40f865..7322db10d24 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -172,7 +172,7 @@ arg_print (struct disassemble_info *info, unsigned long val,
static void
maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
- int wide)
+ int is_addiw)
{
if (pd->hi_addr[base_reg] != (bfd_vma)-1)
{
@@ -187,8 +187,8 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
return; /* Don't print the address. */
pd->to_print_addr = true;
- /* Sign-extend a 32-bit value to a 64-bit value. */
- if (wide)
+ /* On ADDIW, sign-extend a 32-bit value to a 64-bit value. */
+ if (is_addiw)
pd->print_addr = (bfd_vma)(int32_t) pd->print_addr;
/* Fit into a 32-bit value on RV32. */
--
2.34.1
next prev parent reply other threads:[~2022-08-27 0:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-27 0:10 [PATCH v8 0/7] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-27 0:10 ` [PATCH v8 1/7] RISC-V: Add address printer tests with ADDIW Tsukasa OI
2022-08-27 0:10 ` [PATCH v8 2/7] RISC-V: Fix JALR target address computation Tsukasa OI
2022-08-27 0:11 ` [PATCH v8 3/7] RISC-V: Fix RV32 disassembler " Tsukasa OI
2022-08-27 0:11 ` [PATCH v8 4/7] RISC-V: Print highest address on the disassembler Tsukasa OI
2022-08-27 0:11 ` [PATCH v8 5/7] RISC-V: Print top GP-relative addresses " Tsukasa OI
2022-08-27 0:11 ` Tsukasa OI [this message]
2022-08-27 0:11 ` [PATCH v8 7/7] RISC-V: Make `is_addiw' parameter bool Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 0/7] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 1/7] RISC-V: Add address printer tests with ADDIW Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 2/7] RISC-V: Fix JALR target address computation Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 3/7] RISC-V: Fix RV32 disassembler " Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 4/7] RISC-V: Print highest address on the disassembler Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 5/7] RISC-V: Print top GP-relative addresses " Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 6/7] RISC-V: Clarify that `wide' is only used for ADDIW Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 7/7] RISC-V: Make `is_addiw' parameter bool Tsukasa OI
2022-08-27 0:28 ` [PATCH v8 0/7] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-09-02 6:18 ` Nelson Chu
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