From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
"H . Peter Anvin" <hpa@zytor.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Nelson Chu <nelson@rivosinc.com>
Cc: binutils@sourceware.org
Subject: [PATCH v8 7/7] RISC-V: Make `is_addiw' parameter bool
Date: Sat, 27 Aug 2022 00:11:04 +0000 [thread overview]
Message-ID: <361a8dd8cc5396b708b5cbfae842881bb4bf2224.1661559056.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1661559056.git.research_trasio@irq.a4lg.com>
Because we widely use `bool' type, this commit makes this parameter `bool'
in the process of tidying.
opcodes/ChangeLog:
* riscv-dis.c (maybe_print_address): Change `is_addiw' type from
`int' to `bool'. (print_insn_args): Use boolean values.
---
opcodes/riscv-dis.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 7322db10d24..d4c1a5505b1 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -172,7 +172,7 @@ arg_print (struct disassemble_info *info, unsigned long val,
static void
maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
- int is_addiw)
+ bool is_addiw)
{
if (pd->hi_addr[base_reg] != (bfd_vma)-1)
{
@@ -243,10 +243,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
case 'o':
case 'j':
if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0)
- maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0);
+ maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), false);
if (info->mach == bfd_mach_riscv64
&& ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0)
- maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1);
+ maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), true);
print (info->stream, dis_style_immediate, "%d",
(int)EXTRACT_CITYPE_IMM (l));
break;
@@ -406,7 +406,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
case 'b':
case 's':
if ((l & MASK_JALR) == MATCH_JALR)
- maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
print (info->stream, dis_style_register, "%s", riscv_gpr_names[rs1]);
break;
@@ -436,21 +436,21 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
break;
case 'o':
- maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
/* Fall through. */
case 'j':
if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
|| (l & MASK_JALR) == MATCH_JALR)
- maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0);
+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), false);
if (info->mach == bfd_mach_riscv64
&& ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0)
- maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1);
+ maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), true);
print (info->stream, dis_style_immediate, "%d",
(int)EXTRACT_ITYPE_IMM (l));
break;
case 'q':
- maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), 0);
+ maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l), false);
print (info->stream, dis_style_address_offset, "%d",
(int)EXTRACT_STYPE_IMM (l));
break;
--
2.34.1
next prev parent reply other threads:[~2022-08-27 0:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-27 0:10 [PATCH v8 0/7] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-27 0:10 ` [PATCH v8 1/7] RISC-V: Add address printer tests with ADDIW Tsukasa OI
2022-08-27 0:10 ` [PATCH v8 2/7] RISC-V: Fix JALR target address computation Tsukasa OI
2022-08-27 0:11 ` [PATCH v8 3/7] RISC-V: Fix RV32 disassembler " Tsukasa OI
2022-08-27 0:11 ` [PATCH v8 4/7] RISC-V: Print highest address on the disassembler Tsukasa OI
2022-08-27 0:11 ` [PATCH v8 5/7] RISC-V: Print top GP-relative addresses " Tsukasa OI
2022-08-27 0:11 ` [PATCH v8 6/7] RISC-V: Clarify that `wide' is only used for ADDIW Tsukasa OI
2022-08-27 0:11 ` Tsukasa OI [this message]
2022-08-27 0:22 ` [PATCH v8 0/7] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 1/7] RISC-V: Add address printer tests with ADDIW Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 2/7] RISC-V: Fix JALR target address computation Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 3/7] RISC-V: Fix RV32 disassembler " Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 4/7] RISC-V: Print highest address on the disassembler Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 5/7] RISC-V: Print top GP-relative addresses " Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 6/7] RISC-V: Clarify that `wide' is only used for ADDIW Tsukasa OI
2022-08-27 0:22 ` [PATCH v8 7/7] RISC-V: Make `is_addiw' parameter bool Tsukasa OI
2022-08-27 0:28 ` [PATCH v8 0/7] RISC-V: Fix address printer on the disassembler Tsukasa OI
2022-09-02 6:18 ` Nelson Chu
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