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From: Jan Beulich <jbeulich@suse.com>
To: "Cui, Lili" <lili.cui@intel.com>
Cc: hongjiu.lu@intel.com, "Hu, Lin1" <lin1.hu@intel.com>,
	binutils@sourceware.org
Subject: Re: [PATCH V5 8/9] Support APX NDD optimized encoding.
Date: Fri, 5 Jan 2024 15:36:03 +0100	[thread overview]
Message-ID: <416c0efb-8cc0-4f5b-9bbe-177a21226a77@suse.com> (raw)
In-Reply-To: <20231228012714.2989658-9-lili.cui@intel.com>

On 28.12.2023 02:27, Cui, Lili wrote:
> @@ -7754,6 +7804,60 @@ match_template (char mnem_suffix)
>  	  i.memshift = memshift;
>  	}
>  
> +      /* If we can optimize a NDD insn to legacy insn, like
> +	 add %r16, %r8, %r8 -> add %r16, %r8,
> +	 add  %r8, %r16, %r8 -> add %r16, %r8, then rematch template.
> +	 Note that the semantics have not been changed.  */
> +      if (optimize
> +	  && !i.no_optimize
> +	  && i.vec_encoding != vex_encoding_evex
> +	  && t + 1 < current_templates.end
> +	  && !t[1].opcode_modifier.evex
> +	  && t[1].opcode_space <= SPACE_0F38
> +	  && t->opcode_modifier.vexvvvv == VexVVVV_DST
> +	  && (i.types[i.operands - 1].bitfield.dword
> +	      || i.types[i.operands - 1].bitfield.qword))

While you check the last operand's type here, ...

> +	{
> +	  unsigned int match_dest_op = can_convert_NDD_to_legacy (t);
> +
> +	  if (match_dest_op != (unsigned int) ~0)
> +	    {
> +	      size_match = true;
> +	      /* We ensure that the next template has the same input
> +		 operands as the original matching template by the first
> +		 opernd (ATT). To avoid someone support new NDD insns and
> +		 put it in the wrong position.  */
> +	      overlap0 = operand_type_and (i.types[0],
> +					   t[1].operand_types[0]);
> +	      if (t->opcode_modifier.d)
> +		overlap1 = operand_type_and (i.types[0],
> +					     t[1].operand_types[1]);
> +	      if (!operand_type_match (overlap0, i.types[0])
> +		  && (!t->opcode_modifier.d
> +		      || !operand_type_match (overlap1, i.types[0])))
> +		size_match = false;

.. why is it the first one's here? That may be a memory operand, which
in AT&T mode cannot possibly have a size.

Jan

  parent reply	other threads:[~2024-01-05 14:36 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-28  1:27 [PATCH V5 0/9] Support Intel APX EGPR Cui, Lili
2023-12-28  1:27 ` [PATCH V5 1/9] Support APX GPR32 with rex2 prefix Cui, Lili
2023-12-28  1:53   ` H.J. Lu
2024-01-04  8:02     ` Jan Beulich
2024-01-04 11:27       ` Cui, Lili
2024-01-05 14:45   ` Jan Beulich
2024-01-08  3:41     ` Cui, Lili
2023-12-28  1:27 ` [PATCH V5 2/9] Created an empty EVEX_MAP4_ sub-table for EVEX instructions Cui, Lili
2023-12-28  1:54   ` H.J. Lu
2023-12-28  1:27 ` [PATCH V5 3/9] Support APX GPR32 with extend evex prefix Cui, Lili
2023-12-28  1:54   ` H.J. Lu
2023-12-28 13:48     ` Cui, Lili
2023-12-28  1:27 ` [PATCH V5 4/9] Add tests for " Cui, Lili
2023-12-28  1:54   ` H.J. Lu
2023-12-28  1:27 ` [PATCH V5 5/9] Support APX NDD Cui, Lili
2023-12-28  1:55   ` H.J. Lu
2023-12-28  1:27 ` [PATCH V5 6/9] Support APX Push2/Pop2 Cui, Lili
2023-12-28  1:55   ` H.J. Lu
2023-12-28  1:27 ` [PATCH V5 7/9] Support APX pushp/popp Cui, Lili
2023-12-28  1:56   ` H.J. Lu
2023-12-28  1:27 ` [PATCH V5 8/9] Support APX NDD optimized encoding Cui, Lili
2023-12-28  1:56   ` H.J. Lu
2024-01-05 14:36   ` Jan Beulich [this message]
2024-01-08  2:49     ` Hu, Lin1
2023-12-28  1:27 ` [PATCH V5 9/9] Support APX JMPABS for disassembler Cui, Lili
2023-12-28  1:56   ` H.J. Lu
2024-01-05 12:08   ` Jan Beulich
2024-01-08  2:32     ` Hu, Lin1
2024-01-08  7:41       ` Jan Beulich
2024-01-08  7:44         ` Hu, Lin1

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