From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson.chu@sifive.com>,
Vineet Gupta <vineetg@rivosinc.com>
Cc: binutils@sourceware.org
Subject: [PATCH v2 3/3] RISC-V: Add Privileged Architecture version 1.12
Date: Fri, 24 Dec 2021 12:22:56 +0900 [thread overview]
Message-ID: <56d5f2df38d4c85cba359c5dc036f3c168954e09.1640316166.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1640316166.git.research_trasio@irq.a4lg.com>
This commit adds Privileged Architecture version 1.12.
bfd/ChangeLog:
* cpu-riscv.c (riscv_priv_specs): Add version 1.12.
* cpu-riscv.h (enum riscv_spec_class): Add PRIV_SPEC_CLASS_1P12
for Privileged Architecture version 1.12.
gas/ChangeLog:
* config/tc-riscv.c (md_show_usage): Change help string.
* testsuite/gas/riscv/csr-dw-regnums.d: Use -mpriv-spec=1.12
to test latest specification.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p12.d: New test that is
to be modified for Privileged Architecture version 1.12.
* testsuite/gas/riscv/priv-reg-fail-version-1p12.d: New test
that is to be modified for Privileged Architecture version 1.12.
* testsuite/gas/riscv/priv-reg-fail-version-1p12.l: Likewise.
---
bfd/cpu-riscv.c | 1 +
bfd/cpu-riscv.h | 1 +
gas/config/tc-riscv.c | 2 +-
gas/testsuite/gas/riscv/csr-dw-regnums.d | 2 +-
.../gas/riscv/priv-reg-fail-read-only-02.d | 2 +-
.../gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
.../gas/riscv/priv-reg-fail-version-1p12.d | 11 +
.../gas/riscv/priv-reg-fail-version-1p12.l | 24 ++
.../gas/riscv/priv-reg-version-1p12.d | 275 ++++++++++++++++++
9 files changed, 316 insertions(+), 4 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p12.d
diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c
index 813f2c3df8d..5038029ce01 100644
--- a/bfd/cpu-riscv.c
+++ b/bfd/cpu-riscv.c
@@ -117,6 +117,7 @@ const struct riscv_spec riscv_priv_specs[] =
{"1.9.1", PRIV_SPEC_CLASS_1P9P1},
{"1.10", PRIV_SPEC_CLASS_1P10},
{"1.11", PRIV_SPEC_CLASS_1P11},
+ {"1.12", PRIV_SPEC_CLASS_1P12},
};
/* Get the corresponding CSR version class by giving privilege
diff --git a/bfd/cpu-riscv.h b/bfd/cpu-riscv.h
index ed5ee7e60d5..b251d6312b8 100644
--- a/bfd/cpu-riscv.h
+++ b/bfd/cpu-riscv.h
@@ -32,6 +32,7 @@ enum riscv_spec_class
PRIV_SPEC_CLASS_1P9P1,
PRIV_SPEC_CLASS_1P10,
PRIV_SPEC_CLASS_1P11,
+ PRIV_SPEC_CLASS_1P12,
PRIV_SPEC_CLASS_DRAFT,
};
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index e8061217e7c..8bc48d77747 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -4167,7 +4167,7 @@ RISC-V options:\n\
-fno-pic don't generate position-independent code (default)\n\
-march=ISA set the RISC-V architecture\n\
-misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
- -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11)\n\
+ -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\
-mabi=ABI set the RISC-V ABI\n\
-mrelax enable relax (default)\n\
-mno-relax disable relax\n\
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index de17ad81fbd..efcbdc6d5fb 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mpriv-spec=1.11
+#as: -march=rv32if -mpriv-spec=1.12
#objdump: --dwarf=frames
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
index ec206e4d6d1..aaf1206cc39 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
@@ -1,3 +1,3 @@
-#as: -march=rv32if -mcsr-check -mpriv-spec=1.11
+#as: -march=rv32if -mcsr-check -mpriv-spec=1.12
#source: priv-reg-fail-read-only-02.s
#warning_output: priv-reg-fail-read-only-02.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
index a1f27ec0622..3edf5e0d5ee 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
@@ -1,3 +1,3 @@
-#as: -I$srcdir/$subdir -march=rv64if -mcsr-check
+#as: -I$srcdir/$subdir -march=rv64if -mcsr-check -mpriv-spec=1.12
#source: priv-reg.s
#warning_output: priv-reg-fail-rv32-only.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
new file mode 100644
index 00000000000..97b04d1ee6c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
@@ -0,0 +1,11 @@
+#as: -I$srcdir/$subdir -march=rv32ifv_zkr -mcsr-check -mpriv-spec=1.12 -march-attr
+#source: priv-reg.s
+#warning_output: priv-reg-fail-version-1p12.l
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: 1
+ Tag_RISCV_priv_spec_minor: 12
+#...
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
new file mode 100644
index 00000000000..9b9c9aa2f3e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
@@ -0,0 +1,24 @@
+.*Assembler messages:
+.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.12'
+.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.12'
+.*Warning: invalid CSR `sptbr' for the privileged spec `1.12'
+.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.12'
+.*Warning: invalid CSR `mucounteren' for the privileged spec `1.12'
+.*Warning: invalid CSR `hstatus' for the privileged spec `1.12'
+.*Warning: invalid CSR `hedeleg' for the privileged spec `1.12'
+.*Warning: invalid CSR `hideleg' for the privileged spec `1.12'
+.*Warning: invalid CSR `hie' for the privileged spec `1.12'
+.*Warning: invalid CSR `htvec' for the privileged spec `1.12'
+.*Warning: invalid CSR `hscratch' for the privileged spec `1.12'
+.*Warning: invalid CSR `hepc' for the privileged spec `1.12'
+.*Warning: invalid CSR `hcause' for the privileged spec `1.12'
+.*Warning: invalid CSR `hbadaddr' for the privileged spec `1.12'
+.*Warning: invalid CSR `hip' for the privileged spec `1.12'
+.*Warning: invalid CSR `mbase' for the privileged spec `1.12'
+.*Warning: invalid CSR `mbound' for the privileged spec `1.12'
+.*Warning: invalid CSR `mibase' for the privileged spec `1.12'
+.*Warning: invalid CSR `mibound' for the privileged spec `1.12'
+.*Warning: invalid CSR `mdbase' for the privileged spec `1.12'
+.*Warning: invalid CSR `mdbound' for the privileged spec `1.12'
+.*Warning: invalid CSR `mscounteren' for the privileged spec `1.12'
+.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.12'
diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p12.d b/gas/testsuite/gas/riscv/priv-reg-version-1p12.d
new file mode 100644
index 00000000000..87af71dd65d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-version-1p12.d
@@ -0,0 +1,275 @@
+#as: -I$srcdir/$subdir -march=rv32if -mpriv-spec=1.12
+#source: priv-reg.s
+#objdump: -dr -Mpriv-spec=1.12
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
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--
2.32.0
next prev parent reply other threads:[~2021-12-24 3:24 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-24 3:22 [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 1/3] RISC-V: Make testcase indentation consistent Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 2/3] RISC-V: Unify "access all CSRs" testcases Tsukasa OI
2021-12-24 3:22 ` Tsukasa OI [this message]
2022-02-21 13:21 ` [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Jan Beulich
2022-02-21 13:38 ` Tsukasa OI
2022-02-21 13:49 ` Tsukasa OI
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