From: Jan Beulich <jbeulich@suse.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson.chu@sifive.com>
Cc: binutils@sourceware.org, Vineet Gupta <vineetg@rivosinc.com>
Subject: Re: [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12
Date: Mon, 21 Feb 2022 14:21:45 +0100 [thread overview]
Message-ID: <77d4e5d6-5059-3f44-1ee9-8e2a6bfd3af3@suse.com> (raw)
In-Reply-To: <cover.1640316166.git.research_trasio@irq.a4lg.com>
On 24.12.2021 04:22, Tsukasa OI via Binutils wrote:
> Tsukasa OI (3):
> RISC-V: Make testcase indentation consistent
> RISC-V: Unify "access all CSRs" testcases
> RISC-V: Add Privileged Architecture version 1.12
>
> bfd/cpu-riscv.c | 1 +
> bfd/cpu-riscv.h | 1 +
> gas/config/tc-riscv.c | 2 +-
> gas/testsuite/gas/riscv/csr-dw-regnums.d | 2 +-
> gas/testsuite/gas/riscv/option-arch-01a.d | 8 +-
> gas/testsuite/gas/riscv/priv-reg-access-all.s | 292 ++++++++++
> gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 2 +-
> .../gas/riscv/priv-reg-fail-read-only-01.d | 2 +-
> .../gas/riscv/priv-reg-fail-read-only-01.s | 267 +--------
> .../gas/riscv/priv-reg-fail-read-only-02.d | 2 +-
> .../gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
> .../gas/riscv/priv-reg-fail-version-1p10.d | 2 +-
> .../gas/riscv/priv-reg-fail-version-1p11.d | 2 +-
> .../gas/riscv/priv-reg-fail-version-1p12.d | 11 +
> .../gas/riscv/priv-reg-fail-version-1p12.l | 24 +
> .../gas/riscv/priv-reg-fail-version-1p9p1.d | 2 +-
> gas/testsuite/gas/riscv/priv-reg-fail-zkr.d | 2 +-
> .../gas/riscv/priv-reg-version-1p10.d | 534 +++++++++---------
> .../gas/riscv/priv-reg-version-1p11.d | 534 +++++++++---------
> .../gas/riscv/priv-reg-version-1p12.d | 275 +++++++++
Comparing with the spec I find SCONTEXT still is numbered 0x7aa in here,
when the doc says 0x5a8. Was this overlooked? Or is the doc wrong?
Jan
> .../gas/riscv/priv-reg-version-1p9p1.d | 534 +++++++++---------
> gas/testsuite/gas/riscv/priv-reg.s | 294 +---------
> 22 files changed, 1421 insertions(+), 1374 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-access-all.s
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p12.d
>
>
> base-commit: d20236e748ab70e9243960850eef64838f1b9721
next prev parent reply other threads:[~2022-02-21 13:21 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-24 3:22 Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 1/3] RISC-V: Make testcase indentation consistent Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 2/3] RISC-V: Unify "access all CSRs" testcases Tsukasa OI
2021-12-24 3:22 ` [PATCH v2 3/3] RISC-V: Add Privileged Architecture version 1.12 Tsukasa OI
2022-02-21 13:21 ` Jan Beulich [this message]
2022-02-21 13:38 ` [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12 Tsukasa OI
2022-02-21 13:49 ` Tsukasa OI
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