From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH 2/4] x86: have insns acting on segment selector values allow for consistent operands
Date: Fri, 10 Feb 2023 09:49:18 +0100 [thread overview]
Message-ID: <623497d9-1367-d446-1cce-f9b0fe177699@suse.com> (raw)
In-Reply-To: <306b5fa2-9007-a4a1-bff5-f013e2c2c26a@suse.com>
While MOV to/from segment register as well as selector storing insns
already permit 32- and 64-bit GPR operands, selector loading insns and
ARPL do not. Split templates accordingly.
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -694,7 +694,8 @@ i386_intel_operand (char *operand_string
if (got_a_float == 2) /* "fi..." */
suffix = SHORT_MNEM_SUFFIX;
else if (current_templates->start->mnem_off != MN_lar
- && current_templates->start->mnem_off != MN_lsl)
+ && current_templates->start->mnem_off != MN_lsl
+ && current_templates->start->mnem_off != MN_arpl)
suffix = WORD_MNEM_SUFFIX;
break;
--- a/gas/testsuite/gas/i386/i386.d
+++ b/gas/testsuite/gas/i386/i386.d
@@ -61,24 +61,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%eax\),%eax
[ ]*[a-f0-9]+: 0f b7 00 movzwl \(%eax\),%eax
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%eax\)
+[ ]*[a-f0-9]+: 63 ca arpl %cx,%dx
+[ ]*[a-f0-9]+: 63 ca arpl %cx,%dx
+[ ]*[a-f0-9]+: 63 0a arpl %cx,\(%edx\)
+[ ]*[a-f0-9]+: 63 0a arpl %cx,\(%edx\)
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%edx\),%edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%edx\),%edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\)
+[ ]*[a-f0-9]+: 63 d1 arpl %dx,%cx
+[ ]*[a-f0-9]+: 63 d1 arpl %dx,%cx
+[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
+[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
+[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
+[ ]*[a-f0-9]+: 63 11 arpl %dx,\(%ecx\)
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%edx\),%edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%edx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%edx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%edx\),%edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\)
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%edx\)
#pass
--- a/gas/testsuite/gas/i386/i386.s
+++ b/gas/testsuite/gas/i386/i386.s
@@ -68,25 +68,75 @@ movzx eax, word ptr [eax]
movnti dword ptr [eax], eax
.att_syntax
+ arpl %cx,%dx
+ arpl %ecx,%edx
+ arpl %cx,(%edx)
+ arpl %ecx,(%edx)
+
lar %dx,%dx
lar %dx,%edx
lar %edx,%edx
lar (%edx),%dx
lar (%edx),%edx
+
+ lldt %dx
+ lldt %edx
+ lldt (%edx)
+
lsl %dx,%dx
lsl %dx,%edx
lsl %edx,%edx
lsl (%edx),%dx
lsl (%edx),%edx
+ ltr %dx
+ ltr %edx
+ ltr (%edx)
+
+ verr %dx
+ verr %edx
+ verr (%edx)
+
+ verw %dx
+ verw %edx
+ verw (%edx)
+
.intel_syntax noprefix
+ arpl cx,dx
+ arpl ecx,edx
+ arpl [ecx],dx
+ arpl [ecx],edx
+ arpl word ptr [ecx],dx
+ arpl word ptr [ecx],edx
+
lar dx,dx
lar edx,dx
lar edx,edx
lar dx,WORD PTR [edx]
lar edx,WORD PTR [edx]
+
+ lldt dx
+ lldt edx
+ lldt [edx]
+ lldt word ptr [edx]
+
lsl dx,dx
lsl edx,dx
lsl edx,edx
lsl dx,WORD PTR [edx]
lsl edx,WORD PTR [edx]
+
+ ltr dx
+ ltr edx
+ ltr [edx]
+ ltr word ptr [edx]
+
+ verr dx
+ verr edx
+ verr [edx]
+ verr word ptr [edx]
+
+ verw dx
+ verw edx
+ verw [edx]
+ verw word ptr [edx]
--- a/gas/testsuite/gas/i386/i386-intel.d
+++ b/gas/testsuite/gas/i386/i386-intel.d
@@ -62,24 +62,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f b6 00 movzx eax,BYTE PTR \[eax\]
[ ]*[a-f0-9]+: 0f b7 00 movzx eax,WORD PTR \[eax\]
[ ]*[a-f0-9]+: 0f c3 00 movnti DWORD PTR \[eax\],eax
+[ ]*[a-f0-9]+: 63 ca arpl dx,cx
+[ ]*[a-f0-9]+: 63 ca arpl dx,cx
+[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],cx
+[ ]*[a-f0-9]+: 63 0a arpl (WORD PTR )?\[edx\],cx
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[edx\]
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[edx\]
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 63 d1 arpl cx,dx
+[ ]*[a-f0-9]+: 63 d1 arpl cx,dx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
+[ ]*[a-f0-9]+: 63 11 arpl (WORD PTR )?\[ecx],dx
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[edx\]
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[edx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[edx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[edx\]
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\]
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[edx\]
#pass
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -266,6 +266,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
@@ -274,6 +278,18 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\)
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
@@ -282,6 +298,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt %dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 12 lldt \(%rdx\)
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
@@ -290,4 +311,19 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 da ltr %dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 1a ltr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr %dx
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 22 verr \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 ea verw %dx
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\)
+[ ]*[a-f0-9]+: 0f 00 2a verw \(%rdx\)
#pass
--- a/gas/testsuite/gas/i386/x86_64.s
+++ b/gas/testsuite/gas/i386/x86_64.s
@@ -320,6 +320,12 @@ mov tr0, rcx
lar (%rdx),%dx
lar (%rdx),%edx
lar (%rdx),%rdx
+
+ lldt %dx
+ lldt %edx
+ lldt %rdx
+ lldt (%rdx)
+
lsl %dx,%dx
lsl %dx,%edx
lsl %dx,%rdx
@@ -329,6 +335,21 @@ mov tr0, rcx
lsl (%rdx),%edx
lsl (%rdx),%rdx
+ ltr %dx
+ ltr %edx
+ ltr %rdx
+ ltr (%rdx)
+
+ verr %dx
+ verr %edx
+ verr %rdx
+ verr (%rdx)
+
+ verw %dx
+ verw %edx
+ verw %rdx
+ verw (%rdx)
+
.intel_syntax noprefix
lar dx,dx
lar edx,dx
@@ -338,6 +359,13 @@ mov tr0, rcx
lar dx,WORD PTR [rdx]
lar edx,WORD PTR [rdx]
lar rdx,WORD PTR [rdx]
+
+ lldt dx
+ lldt edx
+ lldt rdx
+ lldt [rdx]
+ lldt word ptr [rdx]
+
lsl dx,dx
lsl edx,dx
lsl rdx,dx
@@ -346,3 +374,21 @@ mov tr0, rcx
lsl dx,WORD PTR [rdx]
lsl edx,WORD PTR [rdx]
lsl rdx,WORD PTR [rdx]
+
+ ltr dx
+ ltr edx
+ ltr rdx
+ ltr [rdx]
+ ltr word ptr [rdx]
+
+ verr dx
+ verr edx
+ verr rdx
+ verr [rdx]
+ verr word ptr [rdx]
+
+ verw dx
+ verw edx
+ verw rdx
+ verw [rdx]
+ verw word ptr [rdx]
--- a/gas/testsuite/gas/i386/x86_64-intel.d
+++ b/gas/testsuite/gas/i386/x86_64-intel.d
@@ -266,6 +266,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
@@ -274,6 +278,18 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
@@ -282,6 +298,11 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 d2 lldt dx
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 12 lldt (WORD PTR )?\[rdx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
@@ -290,4 +311,19 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 da ltr dx
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 1a ltr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 e2 verr dx
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 22 verr (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 ea verw dx
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\]
+[ ]*[a-f0-9]+: 0f 00 2a verw (WORD PTR )?\[rdx\]
#pass
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -566,18 +566,21 @@ nop, 0xf1f/0, Nop, Modrm|No_bSuf|No_sSuf
nop, 0x90, 0, NoSuf|RepPrefixOk, {}
// Protection control.
-arpl, 0x63, i286|No64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
+arpl, 0x63, i286|No64, RegMem|CheckOperandSize|IgnoreSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Reg16|Reg32 }
+arpl, 0x63, i286|No64, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Word|Unspecified|BaseIndex }
lar, 0xf02, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
lgdt, 0xf01/2, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
lgdt, 0xf01/2, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
lidt, 0xf01/3, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
lidt, 0xf01/3, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
lmsw, 0xf01/6, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
lsl, 0xf03, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
sgdt, 0xf01/0, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
sgdt, 0xf01/0, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
@@ -590,8 +593,10 @@ smsw, 0xf01/4, i286, Modrm|IgnoreSize|No
str, 0xf00/1, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
str, 0xf00/1, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-verr, 0xf00/4, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-verw, 0xf00/5, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+verr, 0xf00/4, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+verr, 0xf00/4, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+verw, 0xf00/5, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+verw, 0xf00/5, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
// Floating point instructions.
next prev parent reply other threads:[~2023-02-10 8:49 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-10 8:47 [PATCH 0/4] x86: misc CPU type related assembler adjustments Jan Beulich
2023-02-10 8:48 ` [PATCH 1/4] x86-64: LAR and LSL don't need REX.W Jan Beulich
2023-02-10 8:49 ` Jan Beulich [this message]
2023-02-10 8:50 ` [PATCH 3/4] x86-64: don't permit LAHF/SAHF with "generic64" Jan Beulich
2023-02-10 8:51 ` [PATCH 4/4] x86: MONITOR/MWAIT are not SSE3 insns Jan Beulich
2023-02-10 17:02 ` H.J. Lu
2023-02-13 8:08 ` Jan Beulich
2023-02-13 17:40 ` H.J. Lu
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