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From: "H.J. Lu" <hjl.tools@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Binutils <binutils@sourceware.org>
Subject: Re: [PATCH 4/4] x86: MONITOR/MWAIT are not SSE3 insns
Date: Mon, 13 Feb 2023 09:40:30 -0800	[thread overview]
Message-ID: <CAMe9rOqKDPKW-cwpCqq6iqSSivoYzfXnSnKyf82bTPWCqouzpQ@mail.gmail.com> (raw)
In-Reply-To: <effcf27c-83d6-5aa1-9a35-b6505afd9e0d@suse.com>

On Mon, Feb 13, 2023 at 12:08 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 10.02.2023 18:02, H.J. Lu wrote:
> > Since they used to be in SSE3, should they be also allowed with SSE3?
>
> In order to answer the question, can you please clarify what you mean
> by "used to be in SSE3"? I'm not aware of a spec ever marking them as
> SSE3 insns. And not allowing their use in e.g. generic32+sse3 is one
> of the purposes of this change, because that was simply wrong.
>

I checked 2005 Intel SDM which has a separate CPUID bit for MONITOR/MWAIT.
No need for SSE3 then.

Thanks.

-- 
H.J.

      reply	other threads:[~2023-02-13 17:41 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-10  8:47 [PATCH 0/4] x86: misc CPU type related assembler adjustments Jan Beulich
2023-02-10  8:48 ` [PATCH 1/4] x86-64: LAR and LSL don't need REX.W Jan Beulich
2023-02-10  8:49 ` [PATCH 2/4] x86: have insns acting on segment selector values allow for consistent operands Jan Beulich
2023-02-10  8:50 ` [PATCH 3/4] x86-64: don't permit LAHF/SAHF with "generic64" Jan Beulich
2023-02-10  8:51 ` [PATCH 4/4] x86: MONITOR/MWAIT are not SSE3 insns Jan Beulich
2023-02-10 17:02   ` H.J. Lu
2023-02-13  8:08     ` Jan Beulich
2023-02-13 17:40       ` H.J. Lu [this message]

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