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* [PATCH 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
@ 2022-08-12  3:20 Tsukasa OI
  2022-08-12  3:20 ` [PATCH 1/2] RISC-V: Assign DWARF " Tsukasa OI
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Tsukasa OI @ 2022-08-12  3:20 UTC (permalink / raw)
  To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils

Hi!

Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF
register numbers.  RISC-V ABIs Specification (riscv-elf-psabi-doc) is not
ratified yet but at least frozen.  So, I consider it's stable to upstream
it.  According to the documentation, it has register numbers 96 (v0) -
127 (v31).

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_psabi_dwarf_vector_regs>

RISC-V ABIs Specification Version 1.0-rc3: Frozen
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc3>


I also added DWARF register number tests not just for CSRs (existing) and
vector registers (I just added), but also for GPRs (0-31) and FPRs (32-63).


[REQUEST FOR COMMENTS]

Is "v0.t" should be assigned a DWARF register number 96 (same as "v0")?  I
did not add this but adding it might be an option.


Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: Assign DWARF numbers to vector registers
  RISC-V: Add testcase for DWARF register numbers

 binutils/dwarf.c                     |  28 ++--
 gas/config/tc-riscv.c                |   3 +
 gas/testsuite/gas/riscv/dw-regnums.d | 180 ++++++++++++++++++++++++++
 gas/testsuite/gas/riscv/dw-regnums.s | 184 +++++++++++++++++++++++++++
 4 files changed, 385 insertions(+), 10 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/dw-regnums.d
 create mode 100644 gas/testsuite/gas/riscv/dw-regnums.s


base-commit: 906dca17d429f468d49a6cc4753993581c51a899
-- 
2.34.1


^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-08-12  3:41 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-08-12  3:20 [PATCH 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Tsukasa OI
2022-08-12  3:20 ` [PATCH 1/2] RISC-V: Assign DWARF " Tsukasa OI
2022-08-12  3:20 ` [PATCH 2/2] RISC-V: Add testcase for DWARF register numbers Tsukasa OI
2022-08-12  3:40 ` [PATCH v2 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Tsukasa OI
2022-08-12  3:40   ` [PATCH v2 1/2] RISC-V: Assign DWARF " Tsukasa OI
2022-08-12  3:40   ` [PATCH v2 2/2] RISC-V: Add testcase for DWARF register numbers Tsukasa OI

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