From: Indu Bhagat <indu.bhagat@oracle.com>
To: Jan Beulich <jbeulich@suse.com>, Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: Re: [PATCH] x86: change type of Dwarf2 register numbers in register table
Date: Tue, 6 Feb 2024 15:15:03 -0800 [thread overview]
Message-ID: <8c584403-2d51-44e7-9eb7-45a971e6694c@oracle.com> (raw)
In-Reply-To: <2384ac80-6530-4097-8d60-d37336aaa341@suse.com>
Hi Jan,
On 2/2/24 02:25, Jan Beulich wrote:
> Already the %bnd<N> registers used numbers beyond 127, and eGPR ones are
> all out of reach for "signed char", at least when CHAR_BITS=8. Switch to
> "unsigned char", covering appropriately in places where the value
> returned for "none" actually matters (in tc_x86_parse_to_dw2regnum()
> this is actually achieved by altering how X_op is set).
> ---
> I question the use of flag_code here, btw: Imo the choice ought to be
> tied to object format, not present assembly mode. Thoughts?
>
I dont claim to have a full grasp of the matter yet.
IIUC, we need to use flag_code as DWARF register number will differ for
32-bit reg vs 64-bit reg? We do the other set of conditional
assignments (to x86_dwarf2_return_column, x86_cie_data_alignment) in
md_begin (). What I do not understand is why are the assignments
(x86_dwarf2_return_column, x86_cie_data_alignment) not re-done in
set_code_flag () as well ? (Consider user/compiler may pass a
.code16/.code16gcc..)
(..And orthogonal to this, I see that SCFI needs to fail elegantly if
.code16/.code32 appear ,i.e., when flag_code != CODE_64BIT.)
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -5395,10 +5395,8 @@ ginsn_opsize_prefix_p (void)
> static unsigned int
> ginsn_dw2_regnum (const reg_entry *ireg)
> {
> - /* PS: Note the data type here as int32_t, because of Dw2Inval (-1). */
> - int32_t dwarf_reg = Dw2Inval;
> const reg_entry *temp = ireg;
> - unsigned int idx = 0;
> + unsigned int dwarf_reg = Dw2Inval, idx = 0;
>
> /* ginsn creation is available for AMD64 abi only ATM. Other flag_code
> are not expected. */
> @@ -5441,7 +5439,7 @@ ginsn_dw2_regnum (const reg_entry *ireg)
>
> /* Sanity check - failure may indicate state corruption, bad ginsn or
> perhaps the i386-reg table and the current function got out of sync. */
> - gas_assert (dwarf_reg >= 0);
> + gas_assert (dwarf_reg < Dw2Inval);
>
> return (unsigned int) dwarf_reg;
This cast can be removed.
Thanks for the patch.
> }
> @@ -17459,14 +17457,14 @@ tc_x86_parse_to_dw2regnum (expressionS *
>
> if (exp->X_op == O_register && exp->X_add_number >= 0)
> {
> + exp->X_op = O_illegal;
> if ((addressT) exp->X_add_number < i386_regtab_size)
> {
> - exp->X_op = O_constant;
> exp->X_add_number = i386_regtab[exp->X_add_number]
> .dw2_regnum[flag_code >> 1];
> + if (exp->X_add_number != Dw2Inval)
> + exp->X_op = O_constant;
> }
> - else
> - exp->X_op = O_illegal;
> }
> }
>
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -1051,7 +1051,7 @@ typedef struct
> #define RegIZ (RegIP - 1)
> /* FLAT is a fake segment register (Intel mode). */
> #define RegFlat ((unsigned char) ~0)
> - signed char dw2_regnum[2];
> -#define Dw2Inval (-1)
> + unsigned char dw2_regnum[2];
> +#define Dw2Inval 0xff
> }
> reg_entry;
next prev parent reply other threads:[~2024-02-06 23:15 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-02 10:25 Jan Beulich
2024-02-06 23:15 ` Indu Bhagat [this message]
2024-02-07 7:29 ` Jan Beulich
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