* [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)
@ 2022-02-04 0:13 Philipp Tomsich
2022-02-04 4:15 ` Tsukasa OI
0 siblings, 1 reply; 6+ messages in thread
From: Philipp Tomsich @ 2022-02-04 0:13 UTC (permalink / raw)
To: binutils
Cc: Kito Cheng, Paul Donahue, Nelson Chu, Vineet Gupta, Philipp Tomsich
The mtinst and mtval2 CSRs (defined in priv-spec 1.12) are currently
unsupported and missing even when priv-spec is set to 1.12.
Adding those together with their testcases.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/csr-dw-regnums.d: Add mtinst and mtval2.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/csr.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h: Add mtinst and mtval2 CSRs (defined in
priv-spec 1.12).
---
gas/testsuite/gas/riscv/csr-dw-regnums.d | 4 +++-
gas/testsuite/gas/riscv/csr-dw-regnums.s | 2 ++
gas/testsuite/gas/riscv/csr-version-1p10.d | 4 ++++
gas/testsuite/gas/riscv/csr-version-1p10.l | 4 ++++
gas/testsuite/gas/riscv/csr-version-1p11.d | 4 ++++
gas/testsuite/gas/riscv/csr-version-1p11.l | 4 ++++
gas/testsuite/gas/riscv/csr-version-1p12.d | 4 ++++
gas/testsuite/gas/riscv/csr-version-1p9p1.d | 4 ++++
gas/testsuite/gas/riscv/csr-version-1p9p1.l | 4 ++++
gas/testsuite/gas/riscv/csr.s | 2 ++
include/opcode/riscv-opc.h | 4 ++++
11 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index ea0a445c39c..33c6c3c9153 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -1,4 +1,4 @@
-#as: -march=rv32if -mpriv-spec=1.11
+#as: -march=rv32if -mpriv-spec=1.12
#objdump: --dwarf=frames
@@ -117,6 +117,8 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r4930 \(mcause\) at cfa\+3336
DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
DW_CFA_offset_extended_sf: r4932 \(mip\) at cfa\+3344
+ DW_CFA_offset_extended_sf: r4938 \(mtinst\) at cfa\+3368
+ DW_CFA_offset_extended_sf: r4939 \(mtval2\) at cfa\+3372
DW_CFA_offset_extended_sf: r5024 \(pmpcfg0\) at cfa\+3712
DW_CFA_offset_extended_sf: r5025 \(pmpcfg1\) at cfa\+3716
DW_CFA_offset_extended_sf: r5026 \(pmpcfg2\) at cfa\+3720
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index 549475d650e..ee9b03c8699 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -107,6 +107,8 @@ _start:
.cfi_offset mcause, 3336
.cfi_offset mtval, 3340
.cfi_offset mip, 3344
+ .cfi_offset mtinst, 3368
+ .cfi_offset mtval2, 3372
.cfi_offset pmpcfg0, 3712
.cfi_offset pmpcfg1, 3716
.cfi_offset pmpcfg2, 3720
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index 88da7240a78..51cc34c609d 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -209,6 +209,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mtval,a1
[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
[ ]+[0-9a-f]+:[ ]+34459073[ ]+csrw[ ]+mip,a1
+[ ]+[0-9a-f]+:[ ]+34a02573[ ]+csrr[ ]+a0,0x34a
+[ ]+[0-9a-f]+:[ ]+34a59073[ ]+csrw[ ]+0x34a,a1
+[ ]+[0-9a-f]+:[ ]+34b02573[ ]+csrr[ ]+a0,0x34b
+[ ]+[0-9a-f]+:[ ]+34b59073[ ]+csrw[ ]+0x34b,a1
[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
[ ]+[0-9a-f]+:[ ]+3a059073[ ]+csrw[ ]+pmpcfg0,a1
[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index ed6773e637c..61abcabef56 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -131,6 +131,10 @@
.*Warning: read-only CSR is written `csrw marchid,a1'
.*Warning: read-only CSR is written `csrw mimpid,a1'
.*Warning: read-only CSR is written `csrw mhartid,a1'
+.*Warning: invalid CSR `mtinst' for the privileged spec `1.10'
+.*Warning: invalid CSR `mtinst' for the privileged spec `1.10'
+.*Warning: invalid CSR `mtval2' for the privileged spec `1.10'
+.*Warning: invalid CSR `mtval2' for the privileged spec `1.10'
.*Warning: invalid CSR `pmpcfg1' for the current ISA
.*Warning: invalid CSR `pmpcfg1' for the current ISA
.*Warning: invalid CSR `pmpcfg3' for the current ISA
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index b40c1d5d6b9..33bcf7abb55 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -209,6 +209,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mtval,a1
[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
[ ]+[0-9a-f]+:[ ]+34459073[ ]+csrw[ ]+mip,a1
+[ ]+[0-9a-f]+:[ ]+34a02573[ ]+csrr[ ]+a0,0x34a
+[ ]+[0-9a-f]+:[ ]+34a59073[ ]+csrw[ ]+0x34a,a1
+[ ]+[0-9a-f]+:[ ]+34b02573[ ]+csrr[ ]+a0,0x34b
+[ ]+[0-9a-f]+:[ ]+34b59073[ ]+csrw[ ]+0x34b,a1
[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
[ ]+[0-9a-f]+:[ ]+3a059073[ ]+csrw[ ]+pmpcfg0,a1
[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index 44d9611fe49..09db0bd457f 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -131,6 +131,10 @@
.*Warning: read-only CSR is written `csrw marchid,a1'
.*Warning: read-only CSR is written `csrw mimpid,a1'
.*Warning: read-only CSR is written `csrw mhartid,a1'
+.*Warning: invalid CSR `mtinst' for the privileged spec `1.11'
+.*Warning: invalid CSR `mtinst' for the privileged spec `1.11'
+.*Warning: invalid CSR `mtval2' for the privileged spec `1.11'
+.*Warning: invalid CSR `mtval2' for the privileged spec `1.11'
.*Warning: invalid CSR `pmpcfg1' for the current ISA
.*Warning: invalid CSR `pmpcfg1' for the current ISA
.*Warning: invalid CSR `pmpcfg3' for the current ISA
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index fbc30ee2fcc..ec19bab5550 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -209,6 +209,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mtval,a1
[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
[ ]+[0-9a-f]+:[ ]+34459073[ ]+csrw[ ]+mip,a1
+[ ]+[0-9a-f]+:[ ]+34a02573[ ]+csrr[ ]+a0,mtinst
+[ ]+[0-9a-f]+:[ ]+34a59073[ ]+csrw[ ]+mtinst,a1
+[ ]+[0-9a-f]+:[ ]+34b02573[ ]+csrr[ ]+a0,mtval2
+[ ]+[0-9a-f]+:[ ]+34b59073[ ]+csrw[ ]+mtval2,a1
[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
[ ]+[0-9a-f]+:[ ]+3a059073[ ]+csrw[ ]+pmpcfg0,a1
[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
index a96e8c9dbec..46bc465f8f7 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
@@ -209,6 +209,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mbadaddr,a1
[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
[ ]+[0-9a-f]+:[ ]+34459073[ ]+csrw[ ]+mip,a1
+[ ]+[0-9a-f]+:[ ]+34a02573[ ]+csrr[ ]+a0,0x34a
+[ ]+[0-9a-f]+:[ ]+34a59073[ ]+csrw[ ]+0x34a,a1
+[ ]+[0-9a-f]+:[ ]+34b02573[ ]+csrr[ ]+a0,0x34b
+[ ]+[0-9a-f]+:[ ]+34b59073[ ]+csrw[ ]+0x34b,a1
[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,0x3a0
[ ]+[0-9a-f]+:[ ]+3a059073[ ]+csrw[ ]+0x3a0,a1
[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,0x3a1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
index 00d46f509de..ac505eae3f8 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
@@ -143,6 +143,10 @@
.*Warning: invalid CSR `mcounteren' for the privileged spec `1.9.1'
.*Warning: invalid CSR `mtval' for the privileged spec `1.9.1'
.*Warning: invalid CSR `mtval' for the privileged spec `1.9.1'
+.*Warning: invalid CSR `mtinst' for the privileged spec `1.9.1'
+.*Warning: invalid CSR `mtinst' for the privileged spec `1.9.1'
+.*Warning: invalid CSR `mtval2' for the privileged spec `1.9.1'
+.*Warning: invalid CSR `mtval2' for the privileged spec `1.9.1'
.*Warning: invalid CSR `pmpcfg0' for the privileged spec `1.9.1'
.*Warning: invalid CSR `pmpcfg0' for the privileged spec `1.9.1'
.*Warning: invalid CSR `pmpcfg1' for the current ISA
diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index 568328d70d9..423d97ba37c 100644
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -122,6 +122,8 @@
csr mcause
csr mtval # Added in 1.10
csr mip
+ csr mtinst # Added in 1.12
+ csr mtval2 # Added in 1.12
# Machine Memory Protection
csr pmpcfg0 # Added in 1.10
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index cc5287f9872..c9b69f151ec 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2156,6 +2156,8 @@
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
+#define CSR_MTINST 0x34A
+#define CSR_MTVAL2 0x34B
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
#define CSR_PMPCFG2 0x3a2
@@ -2773,6 +2775,8 @@ DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_
DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mtinst, CSR_MTINST, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(mtval2, CSR_MTVAL2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)
2022-02-04 0:13 [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12) Philipp Tomsich
@ 2022-02-04 4:15 ` Tsukasa OI
2022-02-04 8:43 ` Philipp Tomsich
0 siblings, 1 reply; 6+ messages in thread
From: Tsukasa OI @ 2022-02-04 4:15 UTC (permalink / raw)
To: Philipp Tomsich, binutils; +Cc: Kito Cheng, Vineet Gupta, Paul Donahue
Hi Philipp,
I submitted similar changes in a larger patchset. If the review of mine
takes too much time, it would be good to apply yours first.
Also, it would be always happy to see that we solve the same problem the
same way (the only difference between ours I see is letter casing).
<https://sourceware.org/pipermail/binutils/2022-January/119282.html> (PATCH 0/6)
<https://sourceware.org/pipermail/binutils/2022-January/119284.html> (PATCH 2/6)
<https://sourceware.org/pipermail/binutils/2022-January/119285.html> (PATCH 3/6)
Thanks,
Tsukasa
On 2022/02/04 9:13, Philipp Tomsich wrote:
> The mtinst and mtval2 CSRs (defined in priv-spec 1.12) are currently
> unsupported and missing even when priv-spec is set to 1.12.
>
> Adding those together with their testcases.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/csr-dw-regnums.d: Add mtinst and mtval2.
> * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
> * testsuite/gas/riscv/csr-version-1p10.d: Likewise.
> * testsuite/gas/riscv/csr-version-1p10.l: Likewise.
> * testsuite/gas/riscv/csr-version-1p11.d: Likewise.
> * testsuite/gas/riscv/csr-version-1p11.l: Likewise.
> * testsuite/gas/riscv/csr-version-1p12.d: Likewise.
> * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
> * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
> * testsuite/gas/riscv/csr.s: Likewise.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h: Add mtinst and mtval2 CSRs (defined in
> priv-spec 1.12).
>
> ---
>
> gas/testsuite/gas/riscv/csr-dw-regnums.d | 4 +++-
> gas/testsuite/gas/riscv/csr-dw-regnums.s | 2 ++
> gas/testsuite/gas/riscv/csr-version-1p10.d | 4 ++++
> gas/testsuite/gas/riscv/csr-version-1p10.l | 4 ++++
> gas/testsuite/gas/riscv/csr-version-1p11.d | 4 ++++
> gas/testsuite/gas/riscv/csr-version-1p11.l | 4 ++++
> gas/testsuite/gas/riscv/csr-version-1p12.d | 4 ++++
> gas/testsuite/gas/riscv/csr-version-1p9p1.d | 4 ++++
> gas/testsuite/gas/riscv/csr-version-1p9p1.l | 4 ++++
> gas/testsuite/gas/riscv/csr.s | 2 ++
> include/opcode/riscv-opc.h | 4 ++++
> 11 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> index ea0a445c39c..33c6c3c9153 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv32if -mpriv-spec=1.11
> +#as: -march=rv32if -mpriv-spec=1.12
> #objdump: --dwarf=frames
>
>
> @@ -117,6 +117,8 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r4930 \(mcause\) at cfa\+3336
> DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
> DW_CFA_offset_extended_sf: r4932 \(mip\) at cfa\+3344
> + DW_CFA_offset_extended_sf: r4938 \(mtinst\) at cfa\+3368
> + DW_CFA_offset_extended_sf: r4939 \(mtval2\) at cfa\+3372
> DW_CFA_offset_extended_sf: r5024 \(pmpcfg0\) at cfa\+3712
> DW_CFA_offset_extended_sf: r5025 \(pmpcfg1\) at cfa\+3716
> DW_CFA_offset_extended_sf: r5026 \(pmpcfg2\) at cfa\+3720
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> index 549475d650e..ee9b03c8699 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> @@ -107,6 +107,8 @@ _start:
> .cfi_offset mcause, 3336
> .cfi_offset mtval, 3340
> .cfi_offset mip, 3344
> + .cfi_offset mtinst, 3368
> + .cfi_offset mtval2, 3372
> .cfi_offset pmpcfg0, 3712
> .cfi_offset pmpcfg1, 3716
> .cfi_offset pmpcfg2, 3720
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
> index 88da7240a78..51cc34c609d 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p10.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
> @@ -209,6 +209,10 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mtval,a1
> [ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
> [ ]+[0-9a-f]+:[ ]+34459073[ ]+csrw[ ]+mip,a1
> +[ ]+[0-9a-f]+:[ ]+34a02573[ ]+csrr[ ]+a0,0x34a
> +[ ]+[0-9a-f]+:[ ]+34a59073[ ]+csrw[ ]+0x34a,a1
> +[ ]+[0-9a-f]+:[ ]+34b02573[ ]+csrr[ ]+a0,0x34b
> +[ ]+[0-9a-f]+:[ ]+34b59073[ ]+csrw[ ]+0x34b,a1
> [ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
> [ ]+[0-9a-f]+:[ ]+3a059073[ ]+csrw[ ]+pmpcfg0,a1
> [ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
> index ed6773e637c..61abcabef56 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p10.l
> +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
> @@ -131,6 +131,10 @@
> .*Warning: read-only CSR is written `csrw marchid,a1'
> .*Warning: read-only CSR is written `csrw mimpid,a1'
> .*Warning: read-only CSR is written `csrw mhartid,a1'
> +.*Warning: invalid CSR `mtinst' for the privileged spec `1.10'
> +.*Warning: invalid CSR `mtinst' for the privileged spec `1.10'
> +.*Warning: invalid CSR `mtval2' for the privileged spec `1.10'
> +.*Warning: invalid CSR `mtval2' for the privileged spec `1.10'
> .*Warning: invalid CSR `pmpcfg1' for the current ISA
> .*Warning: invalid CSR `pmpcfg1' for the current ISA
> .*Warning: invalid CSR `pmpcfg3' for the current ISA
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
> index b40c1d5d6b9..33bcf7abb55 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p11.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
> @@ -209,6 +209,10 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mtval,a1
> [ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
> [ ]+[0-9a-f]+:[ ]+34459073[ ]+csrw[ ]+mip,a1
> +[ ]+[0-9a-f]+:[ ]+34a02573[ ]+csrr[ ]+a0,0x34a
> +[ ]+[0-9a-f]+:[ ]+34a59073[ ]+csrw[ ]+0x34a,a1
> +[ ]+[0-9a-f]+:[ ]+34b02573[ ]+csrr[ ]+a0,0x34b
> +[ ]+[0-9a-f]+:[ ]+34b59073[ ]+csrw[ ]+0x34b,a1
> [ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
> [ ]+[0-9a-f]+:[ ]+3a059073[ ]+csrw[ ]+pmpcfg0,a1
> [ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
> index 44d9611fe49..09db0bd457f 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p11.l
> +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
> @@ -131,6 +131,10 @@
> .*Warning: read-only CSR is written `csrw marchid,a1'
> .*Warning: read-only CSR is written `csrw mimpid,a1'
> .*Warning: read-only CSR is written `csrw mhartid,a1'
> +.*Warning: invalid CSR `mtinst' for the privileged spec `1.11'
> +.*Warning: invalid CSR `mtinst' for the privileged spec `1.11'
> +.*Warning: invalid CSR `mtval2' for the privileged spec `1.11'
> +.*Warning: invalid CSR `mtval2' for the privileged spec `1.11'
> .*Warning: invalid CSR `pmpcfg1' for the current ISA
> .*Warning: invalid CSR `pmpcfg1' for the current ISA
> .*Warning: invalid CSR `pmpcfg3' for the current ISA
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
> index fbc30ee2fcc..ec19bab5550 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p12.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
> @@ -209,6 +209,10 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mtval,a1
> [ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
> [ ]+[0-9a-f]+:[ ]+34459073[ ]+csrw[ ]+mip,a1
> +[ ]+[0-9a-f]+:[ ]+34a02573[ ]+csrr[ ]+a0,mtinst
> +[ ]+[0-9a-f]+:[ ]+34a59073[ ]+csrw[ ]+mtinst,a1
> +[ ]+[0-9a-f]+:[ ]+34b02573[ ]+csrr[ ]+a0,mtval2
> +[ ]+[0-9a-f]+:[ ]+34b59073[ ]+csrw[ ]+mtval2,a1
> [ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
> [ ]+[0-9a-f]+:[ ]+3a059073[ ]+csrw[ ]+pmpcfg0,a1
> [ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
> index a96e8c9dbec..46bc465f8f7 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
> +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
> @@ -209,6 +209,10 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+34359073[ ]+csrw[ ]+mbadaddr,a1
> [ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
> [ ]+[0-9a-f]+:[ ]+34459073[ ]+csrw[ ]+mip,a1
> +[ ]+[0-9a-f]+:[ ]+34a02573[ ]+csrr[ ]+a0,0x34a
> +[ ]+[0-9a-f]+:[ ]+34a59073[ ]+csrw[ ]+0x34a,a1
> +[ ]+[0-9a-f]+:[ ]+34b02573[ ]+csrr[ ]+a0,0x34b
> +[ ]+[0-9a-f]+:[ ]+34b59073[ ]+csrw[ ]+0x34b,a1
> [ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,0x3a0
> [ ]+[0-9a-f]+:[ ]+3a059073[ ]+csrw[ ]+0x3a0,a1
> [ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,0x3a1
> diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
> index 00d46f509de..ac505eae3f8 100644
> --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l
> +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
> @@ -143,6 +143,10 @@
> .*Warning: invalid CSR `mcounteren' for the privileged spec `1.9.1'
> .*Warning: invalid CSR `mtval' for the privileged spec `1.9.1'
> .*Warning: invalid CSR `mtval' for the privileged spec `1.9.1'
> +.*Warning: invalid CSR `mtinst' for the privileged spec `1.9.1'
> +.*Warning: invalid CSR `mtinst' for the privileged spec `1.9.1'
> +.*Warning: invalid CSR `mtval2' for the privileged spec `1.9.1'
> +.*Warning: invalid CSR `mtval2' for the privileged spec `1.9.1'
> .*Warning: invalid CSR `pmpcfg0' for the privileged spec `1.9.1'
> .*Warning: invalid CSR `pmpcfg0' for the privileged spec `1.9.1'
> .*Warning: invalid CSR `pmpcfg1' for the current ISA
> diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
> index 568328d70d9..423d97ba37c 100644
> --- a/gas/testsuite/gas/riscv/csr.s
> +++ b/gas/testsuite/gas/riscv/csr.s
> @@ -122,6 +122,8 @@
> csr mcause
> csr mtval # Added in 1.10
> csr mip
> + csr mtinst # Added in 1.12
> + csr mtval2 # Added in 1.12
>
> # Machine Memory Protection
> csr pmpcfg0 # Added in 1.10
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index cc5287f9872..c9b69f151ec 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2156,6 +2156,8 @@
> #define CSR_MCAUSE 0x342
> #define CSR_MTVAL 0x343
> #define CSR_MIP 0x344
> +#define CSR_MTINST 0x34A
> +#define CSR_MTVAL2 0x34B
> #define CSR_PMPCFG0 0x3a0
> #define CSR_PMPCFG1 0x3a1
> #define CSR_PMPCFG2 0x3a2
> @@ -2773,6 +2775,8 @@ DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_
> DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
> DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mtinst, CSR_MTINST, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
> +DECLARE_CSR(mtval2, CSR_MTVAL2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
> DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
> DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)
2022-02-04 4:15 ` Tsukasa OI
@ 2022-02-04 8:43 ` Philipp Tomsich
2022-02-04 23:23 ` Hans-Peter Nilsson
0 siblings, 1 reply; 6+ messages in thread
From: Philipp Tomsich @ 2022-02-04 8:43 UTC (permalink / raw)
To: Tsukasa OI; +Cc: binutils, Kito Cheng, Vineet Gupta, Paul Donahue
Tsukasa,
Last time I heard, you did not have copyright assignments in place.
Until this is resolved, I can not look at your patches to not lose the
ability to independently develop if needed (our community has been
burnt in this regard before).
It feels like our entire community fell short on the current 2.38
release, as we are missing support for some of the Priv 1.12 (i.e.,
Ss1-12 and Sm1-12, as the official nomenclature for these extensions
is) content. Given that Priv 1.12 was ratified last year, it is pity
that it will not be contained in a full release for another half year.
I created and sent this patch in response to an issue reported by a DV
team — this is a strong reminder that every time upstream enablement
lags behind, many members of the RISC-V ecosystem will be tracking
issues and spend time on maintaining forks.
On Fri, 4 Feb 2022 at 05:15, Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> I submitted similar changes in a larger patchset. If the review of mine
> takes too much time, it would be good to apply yours first.
>
> Also, it would be always happy to see that we solve the same problem the
> same way (the only difference between ours I see is letter casing).
With the addition of opcodes and CSRs, there's really only one way to
do it (except for insignificant changes).
So, I'm glad that there's no significant difference: I'll chalk that
up as a passed review ;-)
Thanks,
Philipp.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)
2022-02-04 8:43 ` Philipp Tomsich
@ 2022-02-04 23:23 ` Hans-Peter Nilsson
2022-02-04 23:25 ` Palmer Dabbelt
2022-02-04 23:27 ` Philipp Tomsich
0 siblings, 2 replies; 6+ messages in thread
From: Hans-Peter Nilsson @ 2022-02-04 23:23 UTC (permalink / raw)
To: Philipp Tomsich
Cc: Tsukasa OI, Kito Cheng, Vineet Gupta, binutils, Paul Donahue
On Fri, 4 Feb 2022, Philipp Tomsich wrote:
> Tsukasa,
>
> Last time I heard, you did not have copyright assignments in place.
> Until this is resolved, I can not look at your patches to not lose the
> ability to independently develop if needed (our community has been
> burnt in this regard before).
I'll again testify that they're in place:
In copyright.list from 2022-02-01, I see an entry
dated 2022-01-19 for BINUTILS Tsukasa OI "Assigns past and
future changes".
HTH. Happy hacking.
brgds, H-P
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)
2022-02-04 23:23 ` Hans-Peter Nilsson
@ 2022-02-04 23:25 ` Palmer Dabbelt
2022-02-04 23:27 ` Philipp Tomsich
1 sibling, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2022-02-04 23:25 UTC (permalink / raw)
To: hp; +Cc: philipp.tomsich, kito.cheng, Vineet Gupta, binutils, pdonahue
On Fri, 04 Feb 2022 15:23:50 PST (-0800), hp@bitrange.com wrote:
> On Fri, 4 Feb 2022, Philipp Tomsich wrote:
>
>> Tsukasa,
>>
>> Last time I heard, you did not have copyright assignments in place.
>> Until this is resolved, I can not look at your patches to not lose the
>> ability to independently develop if needed (our community has been
>> burnt in this regard before).
>
> I'll again testify that they're in place:
> In copyright.list from 2022-02-01, I see an entry
> dated 2022-01-19 for BINUTILS Tsukasa OI "Assigns past and
> future changes".
>
> HTH. Happy hacking.
Thanks, again ;). I think we're all just blocked on code review right
now, between all the releases and Chinese New Year things have been a
bit crazy.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)
2022-02-04 23:23 ` Hans-Peter Nilsson
2022-02-04 23:25 ` Palmer Dabbelt
@ 2022-02-04 23:27 ` Philipp Tomsich
1 sibling, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2022-02-04 23:27 UTC (permalink / raw)
To: Hans-Peter Nilsson
Cc: Kito Cheng, Paul Donahue, Tsukasa OI, Vineet Gupta, binutils
Thanks for the info. That is excellent news.
—Philipp.
On Sat 5. Feb 2022 at 00:23, Hans-Peter Nilsson <hp@bitrange.com> wrote:
> On Fri, 4 Feb 2022, Philipp Tomsich wrote:
>
> > Tsukasa,
> >
> > Last time I heard, you did not have copyright assignments in place.
> > Until this is resolved, I can not look at your patches to not lose the
> > ability to independently develop if needed (our community has been
> > burnt in this regard before).
>
> I'll again testify that they're in place:
> In copyright.list from 2022-02-01, I see an entry
> dated 2022-01-19 for BINUTILS Tsukasa OI "Assigns past and
> future changes".
>
> HTH. Happy hacking.
>
> brgds, H-P
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-02-04 23:27 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2022-02-04 0:13 [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12) Philipp Tomsich
2022-02-04 4:15 ` Tsukasa OI
2022-02-04 8:43 ` Philipp Tomsich
2022-02-04 23:23 ` Hans-Peter Nilsson
2022-02-04 23:25 ` Palmer Dabbelt
2022-02-04 23:27 ` Philipp Tomsich
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